Kenwood Ts-2000x All Mode Multi-band Transceiver Service Manual

							41
TS-2000/X
Serial-Parallel : BU2099FV
(Final unit IC205, Control unit IC530,
Display unit IC4, TX-RX 1 unit IC5,16,17,
TX-RX 2 unit IC2)

Block diagram
LPF
1
2
3
4
5
6
7
8
9
10 1112
13
14 15
16 17 18 19
20VDD
Control
circuitOE
SO
Q11
Q10
Q9
Q8
Q7
Q6
Q5
Q4 Q3 Q2
Q1 Q0 LCK CLOCKD ATANC VSS
Output buffer (Open drain)
12 bit storage register
12 bit shift register
D flip-flop : TC7WH74FU (Filter unit IC2)

Logic diagram
Q S
C
D
RQ (5)
(3)
PR
CK
D
CLR(7)
(1)
(2)
(6)

Truth table
Input Output Function
CLR PR D CK Q Q
L H X X L H Clear
H L X X H L Preset
LLXXHH –
HH L↑LH –
HHH↑HL –
HH X↓Qn Qn
No change
X : Don‘t care

Pin description
No. Name I/O Description
1 Vss – GND
2NC –NC
3 DATA I Serial data input.
4 CLOCK I Shift register shift clock
(rising edge trigger).
5 LCK I Storage register latch clock
(rising edge trigger).
6~17 Q0~Q11 O Paralle data output
(Qx) (Nch open drain FET).
18 SO O Serial data output.
19 OE I Output enable control input.
20 VDD – Power
Latch data L H
Output FET On Off
Analog Switch : TC74HC4052AFT (Control unit IC6)
Analog Switch : TC74HC4053AFT (Control unit IC5)
Mixer : TC74HC4053AFT (TX-RX 1 unit IC3)

Logic diagram
TC74HC4052AFT TC74HC4053AFT
0
1
G4A
B
INH
X-COM
Y-COM0X
1X
2X
3X
0Y
1Y
2Y
3Y (10)
(12)
(14)
(15)
(11)
(1)
(5)
(2)
(4) (9)
(6)
(13)
(3)MUXDMUX
0...30
1
2
3 4 x
3 0G2
A INH
Z-COM X-COM0X
0Y
1Y
0Z
1Z (11)(12)
(2)
(1)
(5)
(3) (6)
(4) (14)
MUXDMUX
2 x 0
2 x 1
0,10
1
1X (13)
B(10)
Y-COM(15)
C(9)

Truth table
Control inputs “ON” channel
Inhibit C* B A HC4052A HC4053A
L L L L 0X, 0Y 0X, 0Y, 0Z
L L L H 1X, 1Y 1X, 0Y, 0Z
L L H L 2X, 2Y 0X, 1Y, 0Z
L L H H 3X, 3Y 1X, 1Y, 0Z
L H L L – – 0X, 0Y, 1Z
L H L H – – 1X, 0Y, 1Z
L H H L – – 0X, 1Y, 1Z
L H H H – – 1X, 1Y, 1Z
H X X X None None
X : Don‘t care,  * : Except HC4052A
SEMICONDUCTOR DATA 
						

							42
TS-2000/X
Flash ROM for DSP : 29LV800B (Control unit IC504,508)

Block diagram
RY/BY
buffer
  Control
circuit
(Commandregister)
Y decoder
X decoderY gate
8,388,608
cell
matrix
STB Low Vcc
detectionSTB
Data latch
DQ0~DQ15RY/BY
Erase circuit
Write circuit
Vcc
Vss
WE
BYTE
RESET
CE
OE
A0~A18
A-1
Write/Erase
pulse timer
Address latch
Chip enable
output enable
circuitInput/output
buffer
No. Name Description
24 OE Output enable.
25 Vss Ground.
26 CE Chip enable.
27 A0 Address input.
28 DQ0 Data input/output.
29 DQ8 Data input/output.
30 DQ1 Data input/output.
31 DQ9 Data input/output.
32 DQ2 Data input/output.
33 DQ10 Data input/output.
34 DQ3 Data input/output.
35 DQ11 Data input/output.
36 NC No connection.
37 RY/BY Ready/Busy output.
38,39 A18,A17 Address input.
40~43 A7~A4 Address input.
44~46 A1~A3 Address input.

Pin description
No. Name Description
1~3 A13~A15 Address Input.
4~8 A12~A8 Address input.
9 NC No connection.
10 WE Write enable.
11 RESET Hardware reset.
12 Vcc Power (2.7~3.6V).
13 DQ4 Data input/output.
14 DQ12 Data input/output.
15 DQ5 Data input/output.
16 DQ13 Data input/output.
17 DQ6 Data input/output.
18 DQ14 Data input/output.
19 DQ7 Data input/output.
20 A16 Address input.
21 BYTE 8 bit/16 bit mode changeover.
22 Vss Ground.
23 DQ15/A–1 Data input/output/Address input.
SEMICONDUCTOR DATA 
						

							43
TS-2000/X
DSP : 320VC5402PGE (Control unit IC515,516)

Pin description
Pin name Type* Description
Data signal
A19~A0 O/Z Parallel address bus A19 (MSB) to A0 (LSB).  The low-order 16 bits (A0 to A15) of the address pin are multiplexed to
address to external memory (data, program) or I/O.  The high-order 4 bits (A16 to A19) are used to address to external
program space.  These pins are high impedance when in hold mode or when OFF is low.
D15~D0 I/O/Z Parallel data bus D15 (MSB) to D0 (LSB).  D15 to D0 are multiplexed to transfer data between the core CPU and
external data/program memory or I/O device.  The data bus becomes high impedance when data is not output or
RS or HOLD is low.  It also becomes high impedance when OFF is low.
The data bus has a bus holder to reduce power consumption of unused pins.  When there is a bus holder, external
bias resistors for unused pins are not necessary.  When 5402 does not drive the data bus, the bus holder retains the
preceding logic level pin.  The 5402 data bus holder is disabled on reset, and enabled/disabled through the BH bit of
the bank switching control register (BSCR).
Initialization, interrupt and reset operation
IACK O/Z Interrupt signal.  Interrupt reception and interrupt vector specified by A15 to A0 are fetched by the program counter.
It becomes high impedance when OFF is low.
INT0~ I External user interrupt input.  INT0 to INT3 have priorities and can be masked by interrupt mask resister (IMR) and
INT3 interrupt mode bit.  Polling and reset can be performed by the interrupt flag register (IFR).
NMI I Interrupt signal that cannot be masked.  This external interrupt cannot be masked by INTM or IMR.
When NMI is low, the vector is trapped.
RS I Reset.  RS stops DSP operation and initializes the CPU and peripheral.  When RS goes high, execution starts from
0FF80h address of the program memory.  RS affects various registers and status bits.
MP/MC I Microprocessor/microcomputer mode selection.  If it is low on reset, the microcomputer mode is selected, and the
internal program ROM is mapped to the high-order 4K words of the program memory space.  If it is high on reset, the
microprocessor mode is selected and the onchip ROM is erased from the program space.  This pin is sampled only on
reset, and when the MP/MC bit of the processor mode status (PMST) register is reset, the selected mode is made invalid.
Multi-processing signal
BIO I Branch control.  When BIO is active, a conditional branch can be executed.  When it is low, the processor executes a
conditional branch.  The XC instruction samples BIO condition in the pipeline decode phase.  Other instructions sample
BIO in the read phase.
XF O/Z External flag output (latch signal that can be changed by software).  It is set to high by SSBX XF instruction, and set to
low by loading an RSBX XF instruction or ST1.  This signal is used as a communication or general output signal when
several DSPs are used.  It becomes high impedance when OFF signal is at low level, and is set to high level on reset.
Memory control signal
DS O/Z Data, program, or I/O space select signal.  It is always at high level, except when it is driven at low level to access a
PS specific external memory space.  It is active while the address is effective.  In hold mode, it becomes high impedance
IS when the OFF signal is at low level.
MSTRB O/Z Memory strobe signal.  It is always at high level, except when accessing data or program memory through an external
bus.  In hold mode, it becomes high impedance when the OFF signal is at low level.
READY I Data ready signal.  It indicates that an external device has finished preparing accessing a bus.
If it is not ready (READY is at low level), it waits one cycle and checks the READY signal again.  At least two software
wait states must be programmed for the processor to detect a READY signal.  The READY signal is not sampled until
software wait states are complete.
R/W O/Z Read/write signal.  It indicates the direction of data transfer with an external device.  It is normally at high level (read
mode) except when it goes low to execute a write operation.  In hold mode, it becomes high impedance when the
OFF signal is at low level.
SEMICONDUCTOR DATA 
						

							44
TS-2000/X
Pin name Type* Description
IOSTRB O/Z I/O strobe signal.  It is always at high level (read mode) except when accessing an I/O device through an external bus.
In hold mode, it becomes high impedance when the OFF signal is at low level.
HOLD I Hold input signal.  Address, data, or control signal control input signal.  When this signal is accepted, the address,
data, or control signal becomes high impedance.
HOLDA O/Z Hold response signal.  It notifies the external circuits that the processor is in hold state and the address, data and
control signals are high impedance so that they can be used by the external circuits.  It becomes high impedance
when the OFF signal is at low level.
MSC O/Z Microstate completion signal.  MSC indicates that all software wait states are complete.  When several software wait
states are enabled, MSC becomes active at the beginning of the first software wait state and becomes inactive high
at the beginning of the last software wait state.  When READY input is connected, MSC inserts an external wait state
forcibly after completion of the last internal wait state.  It becomes high impedance when the OFF signal is at low level.
IAQ O/Z Instruction capture signal.  It becomes active low when an instruction address is on the address bus.  It becomes high
 impedance when the OFF signal is at low level.
Oscillator/timer signal
CLKOUT O/Z
Master/clock output signal.  A signal with the same frequency as the CPU machine cycle is output.  The internal machine
cycle is delimited at a rising edge of this signal.  It becomes high impedance when the OFF signal is at low level.
CLKMD1 I Clock mode select signal.  These input signals are used to select a mode that is initialized after the clock generator is
~ reset.  The CLKMD1 to CLKMD3 logic level is latched when the reset pin is low and the clock mode register is
CLKMD3 initialized in the selected mode.  The clock mode is changed by software after reset, but the clock mode select signal
is not affected until the device is reset again.
X2/CLKINI Oscillator input.  This is an input to the onchip oscillator.  If an internal oscillator is not used, X2/CLKIN functions as a
clock input and is driven by the external clock source.
X1 O Output pin from crystal internal oscillator.  If the internal oscillator is not used, do not connect this pin.  It does not
become high impedance when the OFF signal is at low level.
TOUT0 O/Z Timer 0 output.  When onchip timer 0 count exceeds 0, a pulse is output.  It has the same pulse width as CLKOUT.
It becomes high impedance when the OFF signal is at low level.
TOUT1 O/Z Timer 1 output.  When onchip timer 1 count exceeds 0, a pulse is output.  It has the same pulse width as CLKOUT.
TOUT1 is output from the HPI HINT pin.  It is disabled when HPI is disabled.  It does not become high impedance
when the OFF signal is at low level.
Multi-channel buffered serial port signal
BCLKR0 I/O/Z Receive clock input.  BCLKR can be used as input and output, and becomes input after reset.  It is a serial shift clock
BCLKR1 of the receive side buffered serial port.
BDR0 I Serial data reception input.
BDR1
BFSR0 I/O/Z Reception input frame synchronous pulse.  BFSR can be used as input and output, and becomes input after reset.
BFSR1 The BFSR pulse ends BDR and initializes data reception.
BCLKX0 I/O/Z Transmission clock.  BCLKX is a McBSP transmission serial shift clock.  BCLKX can be used as input and output, and
BCLKX1 becomes input after reset.  It becomes high impedance when the OFF signal is at low level.
BDX0 O/Z Serial data transmission output.  BDX becomes high impedance when transmission is not performed, RS is low, or
BDX1 OFF is low.
BFSX0 I/O/Z Transmission I/O frame synchronizing pulse.  The BFSX pulse initializes data transmission.  It can be used as input and
BFSX1 output, and becomes input after reset.  It becomes high impedance when the OFF signal is low.
Other signals
NC No connection.
SEMICONDUCTOR DATA 
						

							45
TS-2000/X
Pin name Type* Description
Host port interface (HPI) signal
HD0~ I/O/Z
Parallel bi-directional data bus.  The HPI data bus is used by the host device bus to exchange data with the HPI register.
HD7It becomes high impedance when data is not output or OFF is low.  The HPI data bus has a bus holder to reduce power
consumption of unused pins.  When the DSP does not drive the HPI data bus, the bus holder retains the preceding
logic level.  The HPI data bus holder is disabled on reset, and can be enabled/disabled through the HBH bit of the BSCR.
HCNTL0 I Control signal.  HCNTL0 and HCNTL1 select one of three HPI registers for accessing the host.  Control input includes
HCNTL1 an internal pull-up register that is enabled only when HPIENA = 0.
HBIL I Byte recognition signal.  HBIL recognizes the first or second byte to be transmitted.  HBIL input includes an internal
pull-up register that is enabled only when HPIENA = 0.
HCS I Chip select signal.  HCS selects HPI input and is driven to low during access.  The chip select signal includes an
internal pull-up register that is enabled only when HPIENA = 0.
HDS1 I Data strobe signal.  HDS1 and HDS2 are driven by host read and write strobe for the control signal.
HDS2 There is an internal pull-up register that is enabled only when HPIENA = 0.
HAS I Address strobe signal.  HAS is necessary for the host with multiplexed address and data pins to latch an address with
the HPIA register.  There is an internal pull-up register that is enabled only when HPIENA = 0.
HR/W IRead/write.  HR/W controls HPI transfer direction.  There is an internal pull-up register that is enabled only when HPIENA = 0.
HRDY O/Z Ready signal.  Ready output notifies the host that the HPI is ready to transmit.  It becomes high impedance when the
OFF signal is low.
HINT O/Z Host interrupt signal.  This output is used to interrupt the host.  When the DSP is reset, it goes high.  HINT can be
used as timer 1 output (TOUT1) when HPI is disabled.  It becomes high impedance when the OFF signal is low.
HPIENA I HPI module select signal.  To enable HPI, this pin must be made high on reset.  The internal pulldown register is
always active and the HPIENA pin is sampled at a rising edge of RS.  When HPIENA is open or low on reset, the HPI
module is disabled.  The HPIENA pin is not affected until the DSP is reset.
Power supply pins
CVDD S +VDD.  CPU core 1.8V power supply.
DVDD S +VDD.  I/O pin 3.3V power supply.
Vss S Ground.
Test pins
TCK I IEEE standard 1149.1 test clock.  Normally, clock input with a duty ratio of 50%.  When the input signal (TMS, TDI)
changes on the TAP (test access port), it is loaded into the TAP controller, instruction register, and test data register
at a rising edge of TCK.  The TAP output signal (TDO) data changes at a falling edge of TCK.
TDI I IEEE standard 1149.1 test data input pin with an internal pull-up device.  TDI data is loaded into a register (instruction
or data) at a rising edge of TCK.
TDO O/Z IEEE standard 1149.1 test data output pin.  The contents of a register (instruction or data) are output from TDO at a
falling edge of TCK.  TDO is high impedance except during data scan processing.  It also becomes high impedance
when the OFF signal is low.
TMS I IEEE standard 1149.1 test mode select pin with an internal pull-up device.  The serial control input is loaded into the
TAP controller at a rising edge of TCK.
TRST I IEEE standard 1149.1 test reset pin with internal pulldown device.  When it is high, the device enters the IEEE
standard 1149.1 scan system control mode.  If it is low or not connected, the IEEE standard 1149.1 signal is ignored.
EMU0 I/O/Z Emulator pin 0.  When the TRST pin is low, this pin must be high .  When the TRST pin is high, this pin is used as an
interrupt for the emulator system and becomes an I/O for the IEEE standard 1149.1 scan.
EMU1/ I/O/Z Emulator 1 pin/output control pin.  When the TRST pin is high, this pin is used as an interrupt for the emulator system
OFF and becomes an I/O for the IEEE standard 1149.1 scan system.  When the TRST pin is low, all outputs are high
impedance.  Note that the OFF pin is exclusive for test and emulation.  (They cannot be executed at the same time.)
OFF conditions are as follows; TRST = L, EMU0 = H, EMU1/OFF = L.
* I = Input, O = Output, Z = High impedance, S = Supply
SEMICONDUCTOR DATA 
						

							46
TS-2000/X
CODEC (24 bit)  : AK4524 (Control unit IC518)

Block diagram
Control Register I/F
DATT
SMUTE
HPF
DATT
Audio I/F
Controller ADC
DAC
3
2
26
1
11
25
28
27
171615
12
13
14
20
4
6
5
23
22
24
19
Clock Gen. & Divider
18218910
AINL
AINR
VCOM
AOUTL+
AOUTL–
AOUTR+
AOUTR–VD
VT
DGND
PD
LRCK
BICK
SDTO
SDTI
M/S
VREF
VA
AGND
CS CCLK CDTI CIF CLKO XTO XTI XTALE

Pin function
No. Name I/O Function
1 VCOM O Common voltage output pin, VA/2.
Bias voltage os ADC inputs and DAC
outputs.
2 AINR I Rch analog input pin.
3 AINL I Lch analog input pin.
4 VREF I Voltage reference input pin, VA.
Used as a voltage reference by ADC
& DAC, VREF is connected externally
to filtered VA.
5 AGND – Analog ground pin.
6 VA – Analog power supply pin, 4.75~5.25V
7 TEST I Test pin. (Internal pull-down pin)
8 XTO O X’tal output pin.
9 XTI I X’tal/master clock input pin.
10 XTALE I X’tal osc enable pin.
“H” : Enable, “L” : Disable
11 LRCK I/O Input/output channel clock pin.
12 BICK I/O Audio serial data clock pin.
13 SDTO O Audio serial data output pin.
14 SDTI I Audio serial data input pin.
15 CDTI I Control data input pin.
16 CCLK I Control data clock pin.
17 CS I Chip select pin.
18 CIF I Control data I/F format pin.
“H” : CS falling trigger,
“L” : CS rising trigger
19 PD I Power down mode in.
“H” : Power up, “L” : Power down
reset and initialize the control register.
Mixer : TA4101F (TX-RX 1 unit IC6)

Equivalent circuit
3 : OSC in
2 : Vcc
8 : Collector
1 : IF out
4 : Base
6 : Base
7 : GND
5 : BaseRL1 RL2
R1
RB1
RB2
R2
RB3
RB4
R3
RE1RE2 R4 Q1
Q2 Q3Q4
Q5 Q6
No. Name I/O Function
20 M/S I Master/slave mode pin.
“H” : Master mode, “L” : Slave mode
21 CLKO O Master clock output pin.
22 VT – Output buffer power supply pin,
2.7~5.25V.
23 VD – Digital power supply pin, 4.75~5.25V.
24 DGND – Digital ground pin.
25 AOUTL– O Lch negative analog output pin.
26 AOUTL+ O Lch positive analog output pin.
27 AOUTR– O Rch negative analog output pin.
28 AOUTR+ O Rch positive analog output pin.
Note : All input pins except pull-down pins should not be left floating.
SEMICONDUCTOR DATA 
						

							47
TS-2000/X
CODEC (16 bit) : AK4518
(Control unit IC522,523)

Block diagram
∆∑
Modulator
Decimation
FilterClock
Divider
Serial I/O
Interface Common
Voltage
8x
Interpolator
∆∑
Modulator
Decimation
Filter
∆∑
ModulatorLPF
8x
Interpolator ∆∑
ModulatorLPF
6
5
3
4
2
1
21
19
20
2422231413
15
12
11
10
18
17
8
7
16
9 AINL
VCML
AINR
VCMR
VRAD
VRDA
VCOM
AOUTL
AOUTRMCLK
CMODE
LRCK
SCLK
SDTO
SDTI
PWAD
PWDA
DEM1
DEM0
VA AGND VB VD DGND
No. Name I/O Function
17 DEM1 I De-emphasis frequency select pin.
18 DEM0 I De-emphasis frequency select pin.
19 AOUTL O Lch analog output pin.
20 AOUTR O Rch analog output pin.
21 VCOM O Common voltage output pin, 0.45 x VA.
Connect a 4.7µF electrolytic capacitor
and 0.1µF ceramic capacitor between
this pin and AGND.
22 AGND – Analog ground pin.
23 VB – Substrate pin.
24 VA – Analog power supply pin.
Amplifier : UPC2709TB
(TX-RX 2 unit IC405, 415,416, TX-RX 3 unit IC1)

Equivalent circuit
6 : Vcc
4 : OUT
2,5 : GND
3 : GND 1 : IN

Pin function
No. Name I/O Function
1 VRDA IVoltage reference input pin for DAC, VA.
2 VRAD IVoltage reference input pin for ADC, VA.
3 AINR I Rch analog input pin.
4 VCMR O Rch common voltage output pin,
0.45 x VA. Connect a 4.7µF electrolytic
capacitor and 0.1µF ceramic capacitor
between this pin and AGND.
5 VCML O Lch common voltage output pin,
0.45 x VA. Connect a 4.7µF electrolytic
capacitor and 0.1µF ceramic capacitor
between this pin and AGND.
6 AINL I Lch analog input pin.
7 PWAD I ADC power down mode pin.
“L” : Power down
8 PWDA I DAC power down mode pin.
“L” : Power down
9 MCLK I Master clock input pin.
10 LRCK I Input/output channel clock pin.
11 SCLK I Audio serial data clock pin.
12 SDTO O Audio serial data output pin.
13 DGND – Digital ground pin.
14 VD – Digital power supply pin.
15 SDTI I Audio serial data input pin.
16 CMODE I Master clock select pin.
“H” : 384fs or 512fs, “L” : 256fs
SEMICONDUCTOR DATA 
						

							48
TS-2000/X
DAC : M62363FP (TX-RX 1 unit IC14)

Block diagram
8-bit latch8-bit latch
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
Address
decoder
12-bit shift register
7
19
5
6
178
D-A
converterD-A
converter
23242120
18
DI
CLK
RESET VDD
GND VIN1 VOUT1 VIN8 VOUT8 VDAref LD DO


Pin function
No. Symbol Function
8 DI Serial data input terminal.
17 DO Serial data output terminal.
7 CLK Serial clock input terminal.
6 LD LD terminal input high level then latch circuit
data load.
19 RESET Reset terminal.
2 VOUT1 8-bit resolution D-A output.
3 VOUT2
10 VOUT3
11 VOUT4
14 VOUT5
15 VOUT6
22 VOUT7
23 VOUT8
5 VDD Power supply terminal.
20 GND GND terminal.
1 VIN1 D-A converter input terminal.
4 VIN2
9 VIN3
12 VIN4
13 VIN5
16 VIN6
21 VIN7
24 VIN8
18 VDAref
D-A converter reference voltage input terminal.
VO = (VIN – VDAref) x n / 256 + VDAref
SEMICONDUCTOR DATA
∑
COMP
IOUT
FSELECT
BIT REFINFS ADJUSTREFOUTDVDD
SELSRC
FREQ0 REG
FREQ1 REG MUX
Phase
Accumulator (32 bit)
SYNC
SYNCSYNC
SYNC
MUX
COS
ROM 10-bit
DAC12
PHASE0 REG
PHASE1 REG
PHASE2 REG
PHASE3 REG
16-bit Data Register
Decode Logic
Serial Register
8 MSBs 8 LSBs
Control Register
FSELECT/PSEL Register
Defer
Register
PSEL0BIT
SELSRC
9
FSYNC7
SCLK8
S D ATA11
PSEL0
PSEL1 BIT
12
14
PSEL1
16ON-Board
Reference Full-Scale
Control10
FSELECT
6
MCLK
134 DGND5 AVDD15 AGND132
DDS : AD9835 (TX-RX 1 
unit IC601~603,
                          TX-RX 2  unit IC406~408)

 Block diagram

 Pin function
No. Symbol Function
Analog signal and reference
1 FS ADJUST Full-scale adjust control.
2 REFIN Voltage reference input.
3 REFOUT Voltage reference output.
14 IOUT Current output.
16 COMP Compensation pin.
Power supply
4 DVDD Positive power supply for the digital
section.
5 DGND Digital ground.
13 AGND Analog ground.
15 AVDD Positive power suply fot the analog
section.
Digital interface and control
6 MCLK Digital clock input.
7 SCLK Serial clock, logic input.
8 SDATA Serial data in, logic input.
9 FSYNC Data synchronization signal, logic input.
10 FSELECT Frequency select input.
11 PSEL0 Phase select input.
12 PSEL1 
						

							49
TS-2000/X
PLL : LMX2306TMX (TX-RX 2 unit IC401,409~412,414)
PLL : LMX2316TMX (TX-RX 2 unit IC402, TX-RX 3 unit IC5)

Block diagram
14-bit
R counter
21-bit
Data Register18-bit
Function
LatchPhase
Comp.
Lock
DetectFast
Lock
FoLD
MUX
18-bit
N counterPrescaler
OSC
Charge
Pump OSCIN
fIN
CLOCK
LE
D ATACPo
FLo
FoLD

Pin description
No. Name I/O Description
1 FLo O FastLock output. For connection of
parallel resistor to the loop filter.
2 CPo O Charge pump output. For connection to a
loop filter for driving the input of an
external VCO.
3 GND – Charge pump ground.
4 GND – Analog ground.
5f
INI RF prescaler complementary input.
A bypass capacitor should be placed as
close as possible to this pin and be
connected directly to the ground plane.
The complementary input can be left
unbypassed, with some degradation in
RF sensitivity.
6f
INI RF prescaler input. Small signal input
from the VCO.
7 Vcc1 – Analog power supply voltage input.
Input may range from 2.3V to 5.5V.
Bypass capacitors should be placed as
close as possible to this pin and be
connected directly to the ground plane.
Vcc1 must equal Vcc2.
8 OSC
INI Oscillator input. This input is a CMOS
input with a threshold of approximately
Vcc/2 and an equivalent 100k input
resistance. The oscillator input is driven
from a reference oscillator.
9 GND – Digital ground.
No. Name I/O Description
10 CE I Chip enable. A LOW on CE powers down
the device and will TRI-STATE the charge
pump output. Taking CE HIGH will power
up the device depending on the status of
the power down bit F2.
11 Clock I High impedance CMOS clock input. Data
for the various counters is clocked in on
the rising edge into the 21-bit shift
register.
12 Data I Binary serial data input. Data entered
MSB first. The last two bits are the
control bits. High impedance CMOS input.
13 LE I Load enable CMOS input. When LE goes
high, data stored in the shift registers is
loaded into one of the 3 appropriate
latches (control bit dependent).
14 Fo/LD O Multiplexed output of the RF program-
mable of reference dividers and lock
detect. CMOS output.
15 Vcc2 – Digital power supply voltage input. Input
may range from 2.3V to 5.5V. Bypass
capacitors should be placed as close as
possible to this pin and be connected
directly to the ground plane. Vcc1 must
equal Vcc2.
16 Vp – Power supply for charge pump.
Must be ≥ Vcc.
SEMICONDUCTOR DATA 
						

							50
TS-2000/X
DDS : AD9851BRS (TX-RX 3 unit IC4)

Block diagram
6 x REFCLK
MultiplierHigh
Speed
DDS10-bit
DAC
32-bit
Tuning
WordPhase
and
Control
Words
Frequency/Phase
Data Register
Data Input Register
Parallel
Load
Ref
Clock in
Master
Reset
Frequency
Update/Data
Register
Reset
Word Load
Clock
Serial
LoadDAC RSET
Analog
out
Analog
in
Clock out
Clock out
Comparator+
–
GND
+Vs
1 bit x
40 Loads8 bits x
5 Loads
Frequency, Phase
and Control Data Input

Pin function
No. Name Function
1~4 D3~D0 8-bit data input. The data port for loading
25~28D7~D4 the 32-bit frequency and 8-bit phase/control
words. D7 = MSB, D0 = LSB. D7, pin 25,
also serves as the input pin 40-bit serial data
word.
5 PGND 6 x REFCLK multiplier ground connection.
6 PVCC 6 x REFCLK multiplier positive supply
voltage pin.
7 W CLK Word load clock. Rising edge loads the
parallel or serial frequency/phase/control
words asynchronously into the 40-bit input
register.
8 FQ UD Frequency update. Arising edge asynchro-
nously transfers the contents of the 40-bit
input register to be acted upon by the DDS
core. FQ UD should be issued when the
contents of the input register are known to
contain only valid, allowable data.
9
REFCLOCKReference clock input. CMOS/TTL level
pulse train, direct or via the 6 x REFCLK
multiplier. In direct mode, this is also the
SYSTEM CLOCK. If the 6 x REFCLK multi-
plier is engaged, then the output of the
multiplier is the SYSTEM CLOCK. The rising
edge of the SYSTEM CLOCK initiates
operations.
No. Name Function
10,19 AGND Analog ground. The ground return for the
analog circuitry (DAC and comparator).
11,18 AVDD Positive supply voltage for analog circuitry
(DAC and comparator, pin 18) and bandgap
voltage reference (pin 11).
12 RSET The DAC’s external RSET connection–
nominally a 3.92kΩ resistor to ground for
10mA out. This sets the DAC full-scale
output current available from IOUT and
IOUTB. RSET = 39.93/IOUT.
13 VOUTN Voltage output negative. The comparator’s
“complementary” CMOS logic level output.
14 VOUTP Voltage output positive. The comparator’s
“true” CMOS logic level output.
15 VINN Voltage input negative. The comparator’s
inverting input.
16 VINP Voltage input positive. The comparator’s
noninverting input.
17 DACBP DAC bypass connection. This is he DAC
voltage reference bypass connection
normally NC (no connect) for optimum
SFDR performance.
20 IOUTB The “complementary” DAC output with
same characteristics as IOUT except that
IOUTB = (full-scale output – IOUT). Output
load should equal that of IOUT for best
SFDR performance.
21 IOUT The “true” output of the balanced DAC.
Current is “sourcing” and requires current
to voltage conversion, usually a resistor or
transformer referenced to GND.
IOUT = (full-scale output – IOUTB).
22 RESET Master reset pin, active high, clears DDS
accumulator and phase offset register to
achieve 0Hz and 0° output phase.
Sets programming to parallel mode and
disengages the 6 x REFCLK multiplier.
Reset does mot clear the 40-bit input
register. On power up, asserting RESET
should be the first priority before program-
ming commences.
23 DVDDPositive supply voltage pin for digital circuitry.
24 DGND Digital ground. The ground return pin for the
digital circuitry.
SEMICONDUCTOR DATA