Casio Qt6000 Service Manual

							— 59 —
NO. PIN NAME I/O DESCRIPTION
110 WE3/ICIOWR O D31–D24 select signal
111 VDD Power Internal VDD
112 VSS Power Internal GND
113 SLEEP I Sleep
114 PCIGNT4 O Bus grant (host function)
115 PCIGNT3 O Bus grant (host function)
116 PCIGNT2 O Bus grant (host function)
117 PCIREQ4 I* Bus request (host function)
118 PCIREQ3/MD10 I* Bus request (host function)/mode
119 VDDQ Power IO VDD
120 VSSQ Power IO GND
121 PCIREQ2/MD9 I* Bus request (host function)/mode
122 IDSEL I Configuration device select
123 INTA O Interrupt (async)
124 PCIRST O Reset output
125 PCICLK I PCI input clock
126 PCIGNT1/REQOUT O Bus grant (host function)/bus request
127 PCIREQ1/GNTIN I Bus request (host function)/bus grant
128 SERR I/O System error
129 AD31 I/O PCI address/data/port
130 AD30 I/O PCI address/data/port
131 VDDQ Power IO VDD
132 VSSQ Power IO GND
133 AD29
134 AD28
135 AD27
I/O PCI address/data/port
136 AD26
137 AD25
138 AD24
139 C/BE3 I/O Command/byte enable
140 AD23
141 AD22 I/O PCI address/data/port
142 AD21
143 VDDQ Power IO VDD
144 VSSQ Power IO GND
145 VDD Power Internal VDD
146 VSS Power Internal GND
147 AD20
148 AD19
149 AD18 I/O PCI address/data/port
150 AD17
151 AD16
152 C/BE2 I/O Command/byte enable
153 PCIFRAME I/O Bus cycle
154 IRDY I/O Initiator ready
155 TRDY I/O Target read
156 DEVSEL I/O Device select
157 VDDQ Power IO VDD
158 VSSQ Power IO GND
159 PCISTOP I/O Transaction stop
160 PCILOCK  I/O Exclusive access
161 PERR I/O Parity error
162 PAR I/O Parity
163 C/BE1 I/O Command/byte enable
164 AD15 I/O PCI address/data/port 
						

							— 60 —
NO. PIN NAME I/O DESCRIPTION
165 AD14
166 AD13
I/O PCI address/data/port
167 AD12
168 AD11
169 VDDQ Power IO VDD
170 VSSQ Power IO GND
171 AD10
172 AD9 I/O PCI address/data/port
173 AD8
174 C/BE0 I/O Command/byte enable
175 VDD Power Internal VDD
176 VSS Power Internal GND
177 AD7
178 AD6
179 AD5
I/O PCI address/data/port
180 AD4
181 AD3
182 AD2
183 VDDQ Power I/O VDD
184 VSSQ Power I/O GND
185 AD1 I/O PCI address/data/port
186 AD0 I/O PCI address/data/port
187 IRL0  I Interrupt 0
188 IRL1  I Interrupt 1
189 IRL2 I Interrupt 2
190 IRL3 I Interrupt 3
191 VSSQ Power I/O GND
192 VDDQ Power I/O VDD
193 XTAL2 O RTC crystal resonator pin
194 EXTAL2 I RTC crystal resonator pin
195 VDD-RTC Power RTC VDD
196 VSS-RTC Power RTC GND
197 CA I Hardware standby
198 RESET I Reset
199 TRST I Reset (H-UDI)
200 MRESET I Manual reset
201 NMI I Nonmaskable interrupt
202 BACK/BSREQ O Bus acknowledge/bus request
203 BREQ/BSACK I Bus request/bus acknowledge
204 MD6/IOIS16 I Mode/IOIS16 (PCMCIA)
205 RDY I Bus ready
206 TXD O SCI data output
207 VDDQ Power IO VDD
208 VSSQ Power IO GND
209 VDD Power Internal VDD
210 VSS Power Internal GND
211 MD2/RXD2 I Mode/SCIF data input
212 RXD I SCI data input
213 TCLK I/O RTC/TMU clock
214 MD8/576  I/O Mode/SCIF data control (RTS)
215 SCK I/O SCIF clock
216 MD1/TXD2 I/O Mode/SCIF data output
217 MD0/SCK2 I/O Mode/SCIF clock
218 MD7/CTS2 I/O Mode/SCIF data control (CTS) 
						

							— 61 —
NO. PIN NAME I/O DESCRIPTION
219 AUDSYNC–AUD sync
220 AUDCK–AUD clock
221 VDDQ Power IO VDD
222 VSSQ Power IO GND
223 AUDATA0
–AUD data
224 AUDATA1
225 VDD Power Internal VDD
226 VSS Power Internal GND
227 AUDATA2
–AUD data
228 AUDATA3
229 Reserved–Do not connect
230 MD3/CE2A I/O Mode/PCMCIA-CE
231 MD4/CE2B I/O Mode/PCMCIA-CE
232 MD5 I Mode MD5
233 VDDQ Power IO VDD
234 VSSQ Power IO GND
235 DACK0 O DMAC0 bus acknowledge
236 DACK1 O DMAC1 bus acknowledge
237 DRAK0 O DMAC0 request acknowledge
238 DRAK1 O DMAC1 request acknowledge
239 VDD Power Internal VDD
240 VSS Power Internal GND
241 STATUS0
O Status
242 STATUS1
243 DREQ0 I Request from DMAC0
244 DREQ1 I Request from DMAC1
245 ASEBRK/BRKACK I/O Pin break/acknowledge (H-UDI)
246 TDO O Data out (H-UDI)
247 VDDQ Power IO VDD
248 VSSQ Power IO GND
249 VDD-PLL2 Power PLL2 VDD
250 VSS-PLL2 Power PLL2 GND
251 VDD-PLL1 Power PLL1 VDD
252 VSS-PLL1 Power PLL1 GND
253 VDD-CPG Power CPG VDD
254 VSS-CPG Power CPG GND
255 XTAL O Crystal resonator
256 EXTAL I External input clock/crystal resonator
I: Input
O: Output
I/O: Input/output
Power: Power supply
Notes: 1. Except in hardware standby mode, supply power to all power pins. In hardware standby mode, supply power to RTC as a
minimum.
2. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the on-chip PLL circuits are used.
3. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the on-chip crystal resonator is used.
4. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the on-chip RTC is used.
5. For the handling of the PCI bus pins in PCI-disabled mode, see table D.4 in appendix D.
* I/O attribute is I/O when used as a port. 
						

							— 62 —
8-8. I/O CONTROLLER (IC44: uPD784215AGC8018EU)
8-8-1. Pin Assignment
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20   
21
22
23
24
2575
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51 10076
P120/RTP0
P121/RTP1
P122/RTP2
P123/RTP3
P124/RTP4
P125/RTP5
P126/RTP6
P127/RTP7
V
DD  
X2
X1
V
SS  
XT2
XT1
RESET
P00/INTP0
P01/INTP1
P02/INTP2/NMI
P03/INTP3
P04/INTP4
P05/INTP5
P06/INTP6
AV
DD  
AVREF0  
P10/ANI0
P62/A18  
P61/A17  
P60/A16  
V
SS  
P57/A15  
P56/A14  
P55/A13  
P54/A12  
P53/A11  
P52/A10  
P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
P87/A7
P86/A6
P85/A5
P84/A4
P83/A3
P95
P94
P93
P92
P91
P90
TEST/V
PP
  
P37/EXA   
P36/TI01
P35/TI00
P34/TI2
P33/TI1
P32/TO2
P31/TO1
P30/TO0
P103/TI8/TO8
P102/TI7/TO7
P101/TI6/TO6
P100/TI5/TO5
V
DD  
P67/ASTB
P66/WAIT
P65/WR
P64/RD
P63/A19 P11/ANI1
P12/ANI2
P13/ANI3
P14/ANI4
P15/ANI5
P16/ANI6
P17/ANI7
AV
SS  
P130/ANO0
P131/ANO1
AV
REF1
  
P70/RxD2/SI2
P71/TxD2/SO2
P72/ASCK2/SCK2
P20/RxD1/SI1
P21/TxD1/SO1
P22/ASCK1/SCK1
P23/PCL
P24/BUZ
P25/SI0/SDA0  
P26/SO0
P27/SCK0/SCL0  
P80/A0
P81/A1
P82/A2
77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
2650 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
27 
						

							— 63 —
8-8-2. Block Diagram
INTP2/NMI
INTP0, INTP1,
INTP3-INTP6 PROGRAMMABLEINTERRUPTCONTROLLER
REAL-TIME
OUTPUT PORT
TIMER/COUNTER7 TIMER/COUNTER6 TIMER/COUNTER5 TIMER/COUNTER2 TIMER/COUNTER1
(8 BITS)
(8 BITS) (8 BITS) (8 BITS) (8 BITS) (8 BITS)
TIMER/COUNTER(16 BITS)
WATCH TIMER
TIMER/COUNTER8
WATCHDOG TIMER
TI00
TI01
TO0
TI1
TO1
TI2
TO2
TI5/TO5
TI6/TO6
TI7/TO7
TI8/TO8
RTP0-RTP7
CLOCK OUTPUTCONTROLA/D
CONVERTER AVDDAVSSP03
NMI/INTP2
PCL
BUZ AV
REF0ANI0-ANI7D/A
CONVERTER
ANO0
AV
SS
AVREF1
ANO178K/IV
CPU COREROM
RAMBAUD-RATE
GENERATOR
RxD1/SI1TxD1/SO1
ASCK1/SCK1
RxD2/SI2TxD2/SO2
ASCK2/SCK2
SI0
SO0
SCK0
BUS I/F
UART/IOE1
RD
ASTB
WRWAIT A0-A7 AD0-AD7
A8-A15
A16-A19
PORT1
P10-P17 PORT0
P00-P06
PORT2
P20-P27
PORT3
P30-P37
PORT4
P40-P47
PORT5
P50-P57
PORT6
P60-P67
PORT7
P70-P72
PORT8
P80-P87
PORT9
P90-P95
PORT10
P100-P103
PORT12
P120-P127
PORT13
P130,P131
BUZZER OUTPUT
SYSTEM CONTROL
RESET
XT2
X1
XT1
X2
V
SS
VDD
CLOCKED
SERIAL
INTERFACE BAUD-RATE
GENERATOR
UART/IOE2 
						

							— 64 —
8-8-3. Pin Function
PIN NO.PIN NAME I / O DESCRIPTION
1 P120/RTP0
2 P121/RTP1
3 P122/RTP2
4 P123/RTP3
5 P124/RTP4
6 P125/RTP5
7 P126/RTP6
8 P127/RTP7
9 VDD - Power Supply
10 X2 -
11 X1 I
12 VSS - GND
13 XT2 -
14 XT1 I
15 RESET IReset
16 P00/INTP0
17 P01/INTP1
18 P02/INTP2/NMI
19 P03/INTP3
20 P04/INTP4
21 P05/INTP5
22 P06/INTP6
23 AVDD -A/D CONVERTER POWER SUPPLY
24 AVREF0 -Application of Standard Voltage for A/D CONVERTER
25 P10/ANI0
26 P11/ANI1
27 P12/ANI2
28 P13/ANI3
29 P14/ANI4
30 P15/ANI5
31 P16/ANI6
32 P17/ANI7
33 AVSSA/D CONVERTER & D/A CONVERTER GND
34 P130/ANO0
35 P131/ANO1
36 AVREF1Application of Standard Voltage for D/A CONVERTER
37 P70/RxD2/SI2
38 P71/TxD2/SO2
39 P72/ASCK2/SCK2
40 P20/RxD1/SI1
41 P21/TxD1/SO1
42 P22/ASCK1/SCK1
43 P23/PCL
44 P24/BUZ
45 P25/SI0/SDA0
46 P26/SO0
47 P27/SCK0/SCL0
48 P80/A0
49 P81/A1
50 P82/A28 bit input/output PORT
Main system Clock
Sub system Clock IO
I O 7 bit input/output PORT
I 8 bit input PORT
I O 2 bit input/output PORT
I O 3 bit input/output PORT
I O 8 bit input/output PORT
I O 8 bit input/output PORT 
						

							— 65 —
PIN NO.PIN NAME I / O DESCRIPTION
51 P83/A3
52 P84/A4
53 P85/A5
54 P86/A6
55 P87/A7
56 P40/AD0
57 P41/AD1
58 P42/AD2
59 P43/AD3
60 P44/AD4
61 P45/AD5
62 P46/AD6
63 P47/AD7
64 P50/A8
65 P51/A9
66 P52/A10
67 P53/A11
68 P54/A12
69 P55/A13
70 P56/A14
71 P57/A15
72 VSS - GND
73 P60/A16
74 P61/A17
75 P62/A18
76 P63/A19
77 P64/RD
78 P65/WR
79 P66/WAIT
80 P67/ASTB
81 VDD - Power Supply
82 P100/TI5/TO5
83 P101/TI6/TO6
84 P102/TI7/TO7
85 P103/TI8/TO8
86 P30/TO0
87 P31/TO1
88 P32/TO2
89 P33/TI1
90 P34/TI2
91 P35/TI00
92 P36/TI01
93 P37/EXA
94 TEST/VPP -TEST pin
95 P90
96 P91
97 P92
98 P93
99 P94
100 P95I O 8 bit input/output PORT
I O 8 bit input/output PORT
I O 8 bit input/output PORT
I O 8 bit input/output PORT
I O 4 bit input/output PORT
I O 8 bit input/output PORT
I O 6 bit input/output PORT 
						

							— 66 —
8-9. G/A (IC14: uPD65945GJ-093-JEU)
8-9-1. Pin Function
PIN NO PIN NAME I / ODESCRIPTINPIN NO PIN NAME I / ODESCRIPTIN1 VDD VDD VDD 73 VDD VDD VDD
2  GD0 I/O ARC DATA (D0) 74CLKOUT OCLOCK 8MHz
3  GD1 I/O ARC DATA (D1) 75  CLKIN I CLOCK  8MHz
4  GD2 I/O ARC DATA (D2) 76 GND I GND
5  GD3 I/O ARC DATA (D3) 77  CS I Chip Select 5
6  GD4 I/O ARC DATA (D4) 78   A0 I ADDRESS  (A1)
7 TVDD VDD VDD 79  A1 I ADDRESS (A2)
8 TGND GND GND 80  A2 I ADDRESS (A3)
9  GD5 I/O ARC DATA (D5) 81   A3 I GND
10  GD6 I/O ARC DATA (D6) 82   A23 I ADDRESS  (A23)
11  GD7 I/O ARC DATA (D7) 83   A20 I ADDRESS  (A20)
12  GD8 I/O VDD 84   A21 I ADDRESS  (A21)
13  GD9 I/O VDD 85   A22 I ADDRESS  (A22)
14 TGND GND GND 86  RD I IO READ
15  GD10 I/O VDD 87   WE I IO WRITE
16  GD11 I/O VDD 88 INT6 I INT for ARC
17  GD12 I/O VDD 89  INT7 IInt for PCMCIA
18  GD13 I/O VDD 90 TVDD VDD VDD
19  GD14 I/O VDD 91  RESET IRESET
20 TVDD VDD VDD 92  RD_WE I READ/WRITE  signal
21 TGND GND GND 93  TESTB I VDD
22  GD15 I/O VDD 94   U1_CTSB I CST2
23  GA0 O ARC ADDRESS (A0) 95  U1_DSRB IDSR2
24  GA1 O ARC ADDRESS (A1) 96  U1_SIN IRXD2
25  GA2 O ARC ADDRESS (A2) 97  U1_DTRB ODTR2
26  GA3 O Not  used 98  U1_RTSB O RTS2
27 TGND GND GND 99  U1_SOUT O TXD2
28  D0 I/O DATA (D0) 100  U2_CTSB I CTS3
29  D1 I/O DATA (D1) 101   U2_DSRB IDSR3
30  D2 I/O DATA (D2) 102  U2_SIN IRXD3
31 TVDD VDD VDD 103  U2_DTRB ODTR3
32 TGND GND GND 104  U2_RTSB O RTS3
33  D3 I/O DATA (D3) 105  U2_SOUT O TXD3
34  D4 I/O DATA (D4) 106  U3_CTSB I CTS4
35  D5 I/O DATA (D5) 107   U3_DSRB IDSR4
36 VDD VDD VDD 108 VDD VDD VDD
3 7 GND GND GND 1 0 9 GND GND GND
3 8 GND GND GND 1 1 0 GND GND GND
39  D6 I/O DATA (D6) 111  U3_SIN IRXD4
40  D7 I/O DATA (D7) 112  U3_DTRB ODTR4
41  D8 I/O VDD 113  U3_RTSB O RTS4
42 TGND GND GND 114  U3_SOUT O TXD4
43  D9 I/O VDD 115  U4_CTSB I VDD
44  D10 I/O VDD 116  U4_DSRB I VDD
45  D11 I/O VDD 117  U4_SIN I VDD
46 TVDD VDD VDD 118  U4_DTRB O NOT USED
47 TGND GND GND 119  U4_RTSB O NOT USED
48  D12 I/O VDD 120  U4_SOUT O NOT USED
49  D13 I/O VDD 121  U5_CTSB I VDD
50  D14 I/O VDD 122  U5_DSRB I VDD
51 TGND GND GND 123  U5_SIN I VDD
52  D15 I/O VDD 124  U5_DTRB O NOT USED
53  INTC2 O INT for ARC 125   U5_RTSB O NOT USED
54  INTC1 O INT for UART 126  U5_SOUT O NOT USED
55  GCS1 O Chip Select for ARC 127 TVDD VDD VDD
56  GCS2 O EST-CS 128   PCMIN IPCMCD1
57  GRD O Read signal for ARC 129  CE1B I CE1
58  GWE O Write signal for ARC 130  CE2B I CE2
59  PCIN O PCMCIA IN/OUT signal 131  CFIN ICFCD1
60  PCMG O Enable for PCMCIA 132  CE1A I CE1
61  CFCE1A O Chip Enable1 for CF CARD 133  CFCE I ADDRESS (A23)
62  CIN O CF CARD IN/OUT signal 134   CE2A I CE2
63  CFG O Enable for CF CARD 135  BFI1 I CI1
64  CFCE2A O Chip Enable2 for CF CARD 136  BFI2 I CD1
65  ANDO1 O WAIT signal 137  BFI3 IRXD1
66  ANDO2 O DSR 138  BFI4 I CTS1
67  BFO1 O CI 139  ANDI1 I WAIT for CF CARD
68  BFO2 O CD  140  ANDI2 I WAIT for PCMCIA
69  BFO3 O RXD 141  ANDI3 IDSR1
70  BFO4 O CTS 142  ANDI4 IDSR1
7 1 GND GND GND 1 4 3 GND GND GND
7 2 GND GND GND 1 4 4 GND GND GND 
						

							— 67 —
8-10. SDRAM (IC12: EDS2532AABH)
DQ261A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
23456789
DQ28
VSSQ
VSSQ
VDDQ
VSS
A4
A7
CLKDQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKEVSS
VSSQ
DQ25
DQ30
NC
A3
A6
NC
A9VDD
VDDQ
DQ22
DQ17
NC
A2
A10
NC
BA0DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
BA1
/CSDQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A1
A11
/RAS
(Top view)
DQM1 NC NC /CAS /WEDQM0
VDDQ DQ8 VSS VDD DQ7
VSSQ
VSSQ DQ10 DQ9 DQ6 DQ5
VDDQ
VSSQ DQ12 DQ14 DQ1 DQ3
VDDQ
DQ11 VDDQ VSSQ VDDQ VSSQ
DQ4
DQ13 DQ15 VSS VDD DQ0
DQ2
90-ball FBGA
ClockGenerator
Mode
Register
Command Decoder
Control Logic
Row
Address
Buffer
      &
Refresh
Counter
Column
Address
Buffer
      &
Burst
Counter
Data Control Circuit
Latch Circuit
Input & OutputBuffer
DQ
DQM CLK
CKE
Address
/CS
/RAS
/CAS
/WE
Bank 3
Bank 2
Bank 1
Sense Amplifier
Column Decoder &
Latch CircuitBank 0
Row Decoder 
						

							— 68 —
8-11. FLASH RAM (IC1: MBM29QM12DH)
RESET
RY/BY
A
0A1A2A3A4A5VCCDQ0DQ1DQ2DQ3VSSQVCCQDQ4DQ5DQ6DQ7VSSN.C.
A6A7A8A9A10A11A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
2856
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29 TSOP (1)
(Top View)
WP/ACC
WE
N.C.
A
22A21A20OE
N.C.
CE
V
SSDQ15DQ14DQ13DQ12VSSQVCCQDQ11DQ10DQ9DQ8VCCA19A18A17A16A15A14A13
(Marking Side)
(FPT-56P-M01)
VCC
VSS
A22 to A0
RESET
WE
CE
OE
WP/ACC
DQ
15 to DQ0
DQ15to
DQ0
Bank A
address
Bank C AddressBank B Address
Bank D
address State
Control
&
Command
RegisterStatusRY/BY
ControlCell Matrix
16 Mbit
(Bank A)
X-Decoder
Y-Gating
Cell Matrix
16 Mbit
(Bank D) X-Decoder
Y-Gating
Cell Matrix
48 Mbit
(Bank B)
X-Decoder
Y-Gating
Cell Matrix
48 Mbit
(Bank C) X-Decoder
Y-Gating
23
A
22  to A0
OE 
CE 
RESETDQ
15 to DQ0
    16
WP/ACC
WERY/BY