Casio Qt6000 Service Manual
Have a look at the manual Casio Qt6000 Service Manual online for free. It’s possible to download the document as PDF or print. UserManuals.tech offer 338 Casio manuals and user’s guides for free. Share the user manual or guide on Facebook, Twitter or Google+.
— 89 — 2 error point: Indicates the point on the memory where the operation instruction that causes the above general exception is located (program counter). However, an illegal address may be displayed depending on the exception code. 3 access adrs: Indicates the address that is accessed according to the operation instruction that causes the above general exception. However, the address is 0 (zero) and has no meaning if the access is not the cause. 4 Error Code Correspondence Table 5 Causes of error occurrence (1) error no. 40: TLB address comparison results in address mismatch (2) error no. 60: TLB entry is invalid Description of phenomenon: The CPU performs a conversion from logical address to physical address when accessing the external memory. TLB is what caches that information. If an error occurs in the process of the caching, a general exception of the CPU occurs. Possible causes: A malfunction of the CPU, because this is an internal operation of the CPU. (3) error no. 80: Initial page write exception Description of phenomenon: This exception occurs if the address conversion table of the above TLB is illegally written. Possible causes: A malfunction of the CPU, because this is an internal operation of the CPU. (4) error no. A0: TLB protection exception (read) (5) error no. C0: TLB protection exception (write) Description of phenomenon: TLB is protected by setting access right. An access that violates the access right causes one of these exceptions to occur. Possible causes: A malfunction of the CPU, because this is an internal operation of the CPU. (6) error no. E0: CPU address error (read) (7) error no. 100: CPU address error (write) Description of phenomenon: This exception occurs if an illegal address is accessed (read or written). Possible causes: • An illegal address is accessed by software (a software bug). • The address to be accessed has changed due to insufficient charge of the backup battery for RAM. error no. error point access adrs Description of error 40 Location where error occurs Logical address of comparison sourceTLB address comparison results in address mismatch 60 Location where error occurs Logical address of error source TLB entry is invalid 80 Location where error occurs Logical address of error source Initial page write exception A0 Location where error occurs Logical address of error source TLB protection exception (read) C0 Location where error occurs Logical address of error source TLB protection exception (write) E0 Location where error occurs Address of read destination CPU address error (read) 100 Location where error occurs Address of write destination CPU address error (write) 180 Location where error occurs 0 Reservation instruction code exception 1A0 Location where error occurs 0 Slot illegal instruction exception
— 90 — (8) error no. 180: Reservation instruction code exception (9) error no. 1A0: Slot illegal instruction exception Description of phenomenon: These exceptions occur when an illegal instruction is performed. Possible causes: It is hard to think that this phenomenon is caused by software, because these errors occur due to an internal operation of the CPU. This phenomenon is apt to occur when backup of RAM is not performed normally and the memory has been changed. It is possible that the data in RAM has become illegal data. 9-6. Booster Error An error in Booster part processing (IPL, INT or FINT) is indicated as follows: ERR XX XX: Error No. Error Code Correspondence Table Error No. Description of error 1 CF card is not inserted. 2 CF card has no IPL file. 3 Flash erase error 4 Flash write error 5 Reserved (error not occurring this time) 6 CF card read error (bad CF card) 7 COM1 open error (bad CPU) 8 Reserved (error not occurring this time) 9 Bad read IPL data (IPL data is not valid) 10 Checksum error (checksum of read IPL data does not match) 11 Reserved (error not occurring this time) 12 Communication error on COM1 13 Communication error on COM1 (same as 12; 12 or 13 occurs depending on timing of occurrence)
— 91 — 10. IC DATA MAIN PCB (E820-1 PCB) 1. ALVCH16244 (IC13, 17) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 2448 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 251OE 1Y1 1Y2 GND 1Y3 1Y4 V CC2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 V CC4Y1 4Y2 GND 4Y3 4Y4 4OE 2OE 1A1 1A2 GND 1A3 1A4 V CC2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 V CC4A1 4A2 GND 4A3 4A4 3OE 1OE 1A1 1A2 1A3 1A41Y1 1Y2 1Y3 1Y4 1 47 46 44 432 3 5 6 2OE 2A1 2A2 2A3 2A42Y1 2Y2 2Y3 2Y4 48 41 40 38 378 9 11 12 3OE 3A1 3A2 3A3 3A43Y1 3Y2 3Y3 3Y4 25 36 35 33 3213 14 16 17 4OE 4A1 4A2 4A3 4A44Y1 4Y2 4Y3 4Y4 24 30 29 27 2619 20 22 23 logic diagram (positive logic) terminal assignments 123456 A 1OENCNCNCNC2OE B 1Y21Y1GNDGND1A11A2 C 1Y41Y3 VCCVCC1A31A4 D 2Y22Y1GNDGND2A12A2 E 2Y42Y32A32A4 F 3Y13Y23A23A1 G 3Y33Y4GNDGND3A43A3 H 4Y14Y2 VCCVCC4A24A1 J 4Y34Y4GNDGND4A44A3 K 4OENCNCNCNC3OE NC No internal connectionFUNCTION TABLE (each 4-bit buffer) INPUTS OUTPUT OEA OUTPUTY LHH LLL HXZ
— 92 — 2. ALVCH16245 (IC8) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 2448 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 251DIR 1B1 1B2 GND 1B3 1B4 V CC1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 V CC2B5 2B6 GND 2B7 2B8 2DIR 1OE 1A1 1A2 GND 1A3 1A4 V CC1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 V CC2A5 2A6 GND 2A7 2A8 2OE To Seven Other Channels 1DIR 1A1 1B1 1OE 1 4748 2 logic diagram (positive logic) terminal assignments 123456 A 1DIRNCNCNCNC1OE B 1B21B1GNDGND1A11A2 C 1B41B3 VCCVCC1A31A4 D 1B61B5GNDGND1A51A6 E 1B81B71A71A8 F 2B12B22A22A1 G 2B32B4GNDGND2A42A3 H 2B52B6 VCCVCC2A62A5 J 2B72B8GNDGND2A82A7 K 2DIRNCNCNCNC2OE NC No internal connectionFUNCTION TABLE (each 8-bit section) INPUTSOPERATIONOEDIROPERATION LLB data to A bus LHA data to B bus HXIsolation
— 93 — 3. BR93L46RF (IC35) Vcc NC NC GND CS SK DI DO Pin Name I/O Function Vcc - Power Supply GND - GND CS INPUT Chip Selct SK INPUT Serial Clock Input DI INP Start bit,Cord,Address,Serial data DO OUTPUT Serial data input, READY/BUSY status 4. HD74LV00 (IC29) 1 2 3 4 5 7 6 1A 1B 1Y 2A 2B GND2YVCC 4B 4A 4Y 3B 3Y 3A 14 13 12 11 10 8 9 5. HD74LV74 (IC25) TGC C TG C TGC C C C TGC C PRE CLK D CLRQQ C logic diagram, each flip-flop (positive logic) 1 2 3 4 5 6 714 13 12 11 10 9 8 1CLR 1D 1CLK 1PRE 1Q 1Q GNDVCC 2CLR 2D 2CLK 2PRE 2Q 2QFUNCTION TABLE INPUTSOUTPUTS PRECLRCLKDQQ LHXXHL HLXXLH LLXXHÜ HÜ HH HHL HH LLH HHLXQ0Q0 Ü This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level.
— 94 — 6. HD74LVC08 (IC20) 8. HD74LVC244 (IC4,5) 11 1213 14V CC 4B 4A 4Y 3B 3A 1 2 3 4 5 6 7 89 10 1A GND1B 1Y 2A 2B 2Y 3Y 11 1213 14V CC1 2 3 4 5 6 7 10 A GND89 15 16 AB C Y 7 G1 G2B G2A Y0 Y1 Y2 Y3 Y4 Y5 B C G 2A G2B G1 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Y6 7. HD74LVC138 (IC11) 11G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GNDVcc 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 2 3 4 5 6 7 8 9 1020 19 18 17 16 15 14 13 12 11 Inputs GA HX LH LLOutput Y Z H L H : High L : Low X: Don’t care Z: High impedance 1T/R A0 A1 A2 A3 A4 A5 A6 A7 GNDVcc OE B0 B1 B2 B3 B4 B5 B6 B7 2 3 4 5 6 7 8 9 1020 19 18 17 16 15 14 13 12 11 Inputs OE T / R LL LH HXOutput Y Bus B Data to Bus A Bus A Data to Bus B Z H : High L: Low X: Don t care Z: High impedance 9. HD74LVC245 (IC6,7)
— 95 — 10. HIN202CBNZ-T (IC24) 11. HIN211CAZ-T (IC3,9,23,27) 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 C1+ V+ C1- C2+ C2- R2 IN T2OUT VCC T1OUT R1IN R1OUT T1IN T2IN R2OUT GND V- VCC +5V 2 V+ 16 T1 OUT T2OUT T1IN T2IN T1 T2 11 1014 7 +5V 400k +5V400k R1OUTR1INR113 125k R2OUTR2INR28 95k +10V TO -10V VOLTAG E INVERTER 0.1 F 6 V- C2+C2- + 0.1 F45 +5V TO 10V VOLTAG E INVERTER C1+ C1- + 0.1 F13+0.1F + GND 15 T3OUT T1OUT T2OUT R2IN R2OUT T2IN T1IN R1OUT R1IN GND V CC C1+ V+ C1-T4 OUT R3OUT SD EN R4 IN T4IN R5OUT R5IN V- C2- C2+ R3 IN R4OUT T3IN 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 11 V CC+5V TO 10V VOLTA GE DOUBLER +10V TO -10V VOLTAGE INVERTER T1 OUT T2OUT T3OUT T1IN T2IN T3IN T1 T2 T3 +5V +0.1 F +0.1 F + 0.1 F 7 62 3 20 1 12 1413 17 V+ V- C1+ C1- C2+ C2- +5V 40 0k +5V 400k +5V 400k + 0.1 F1516 R1OUTR1INR195k R2OUTR2INR24 55k R3OUTR3INR327 265k R4OUTR4INR423 225k R5OUTR5INR518 195k EN248T4 OUTT4IN T4 21 28+5V 400k SD25 GND 10
— 96 — 12. IDT2305 (IC40) PLL 8 CLK1 CLK2 CLK3 CLK 4 Control Logic REF CLKOUT 1 3 2 5 7 REF CLK12 3 48 7 6 5 1 CLK2 GNDCLKOUT CLK4 V DD CLK FUNCTIONALBLOCKDIAGRAM 13. LM4876M (IC18) SHUTDOWN1 BYPASS 2 + IN 3 – IN 4Vol2 8 GND 7 V DD6 Vol1 5+ 10kΩ 10kΩVo1 Vo2 Av= –1 100kΩ 100kΩ GND 7 1 2 3 46 5 8 Amp2 Amp1 V DD/2 +IN – IN Bypass Shutdown–+ – Bias Typical Application 14. M51957BFP (IC33) INPUT OUTPUT GND 1.25V5uA 25uA + - - POWER DELAY VALUE NC INPUT NC GNDPOWER OUTPUTNC DELAY VALUE 1 2 3 4 5 6 78
— 97 — 15. RTC-7301DG (IC19) 1 2 3 4 5 7 6 8VDD VDD CS1 D0 D1 D2D3 9 WR VDD CS0 IRQ A0 A1 A2 A3 RD GND FOUT 14 15 16 17 18 13 12 1110 32.768 kHz 7301SF 7301DGOSC DIVIDERDigital Trimming REGISTER CLOCK and CALENDAR TIMER REGISTER ALARM REGISTER CONTROL REGISTER SYSTEM REGISTER FOUT CONTROLLER INTERRUPTS CONTROLLER BUS INTERFACE CIRCUIT Temperature Sensor VTEMP FOUT FCON IRQ A0 - A3 D0 - D3 WR RD CS 0CS1 *1 Control Line and 16. S-80828CLNB-B6N-T2 (IC55) OUT V + - DD VSS VRF.F * * 2 4143 12 VNC OUT V DD SS 17. SG-8002JFSCB14.318M (IC41): Programmable High-Frequency Crystal Oscillator (14.318 MHz) SG-8002JFSCB33M (IC43): Programmable High-Frequency Crystal Oscillator (33 MHz) 18. SN74AHCT08 (IC49) 11 1213 14V CC 4B 4A 4Y 3B 3A 1 2 3 4 5 6 7 89 10 1A GND1B 1Y 2A 2B 2Y 3Y
— 98 — 20. SN74LV04APWR (IC10) 1 2 3 4 5 6 7 816 15 14 13 12 11 10 94 5 6 7 EI A2 A1 GNDVCC EO GS 3 2 1 0 A0 logic diagram (positive logic) 11 A0 9 1 A1 7 A2 6GS 14EO 15 122 133 14 25 5EI 47 3 610 0 FUNCTION TABLE INPUTSOUTPUTS EI01234567A2A1A0GSEO HXXXXXXXXHHHHH LHHHHHHHHHHHHL LXXXXXXX LLLLLH LXXXXXXLHLLHLH LXXXXX LHHLHLLH LXXXXLHHHLHHLH LXXX LHHHHH L LLH LXXLHHHHHH L HLH LXLHHHHHHHH LLH LLHHHHHHHHHHLH 1A 1Y 2A 2Y1 2 3 4 5 7 6 3A GND3YVCC 6A 6Y 5A 5Y 4Y 4A 14 13 12 11 10 8 9 19. SN74HC148 (IC32) 21. SSN74LV07A (IC37) AY 1A 1Y 2A 2Y1 2 3 4 5 7 6 3A GND3YVCC 6A 6Y 5A 5Y 4Y 4A 14 13 12 11 10 8 9