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Acer Aspire One Model Nav Service Guide

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Page 131

Chapter 4121
POST Code Reference Tables
These tables describe the POST codes and components of the POST process. 
Sec:
NO_EVICTION_MODE_DEBUG EQU 1 (CommonPlatform\sec\Ia32\SecCore.inc)
Memory:
DEBUG_BIOS equ 1 (Chipset\Alviso\MemoryInitAsm\IA32\IMEMORY.INC)
CodeDescription
0xC2 MTRR setup
0xC3 Enable cache
0xC4 Establish cache tags
0xC5 Enter NEM, Place the BSP in No Fill mode, set CR0.CD = 1, CR0.NW = 0.
0xCF Cache Init Finished
CodeDescription
0xA0 First memory check point
0x01 Enable MCHBAR
0x02...

Page 132

122Chapter 4
BDS & Specific action:
0x27 Enable DRAM Channel I/O Buffers
0x28 Enable all clocks on populated rows
0x29 Perform JEDEC memory initialization for all memory rows
0x30 Perform steps required after memory init
0x31 Program DRAM throttling and throttling event registers
0x32 Setup DRAM control register for normal operation and enable
0x33 Enable RCOMP
0x34 Clear DRAM initialization bit in the SB
0x35 Initialization Sequence Completed, program graphic clocks
0x43 Program Thermal Throttling...

Page 133

Chapter 4123
Each PEIM entry point used in 80_PORT
Each Driver entry point used in 80_PORT
CodeDescription
0x00
0x01 PEI_EVENT_LOG
0xA1 PEI_OEM_SERVICE
0xA2 PEI_SIO_INIT
0xA3 PEI_MONO_STATUS_CODE
0xA4 PEI_CPU_IO_PCI_CFG
0x06 PEI_CPU_IO
0x07 PEI_PCI_CFG
0xA5 PEI_CPU_PEIM
0xA6 PEI_PLATFORM_STAGE1
0xA7 PEI_VARIABLE
0xA8 PEI_SB_INIT
0x0C PEI_CAPSULE
0xAA PEI_PLATFORM_STAGE2
0xAC PEI_SB_SMBUS_ARP_DISABLED
0x0F PEI_HOST_TO_SYSTEM
0x40 PEI_MEMORY_INIT
0x41 PEI_S3_RESUME
0xAD PEI_CLOCK_GEN
0xAB PEI_OP_PRESENCE...

Page 134

124Chapter 4
0xC4 SECURITY_STUB
0xC5 DXE_CPU_IO
0xC6 CF9_RESET
0xC7 PC_RTC
0xC8 STATUS_CODE
0xC9 VARIABLE 
EMU_VARIABLE
0xD9 DXE_CHIPSET_INIT
0x45 DXE_ALERT_FORMAT
0xD6 PCI_HOST_BRIDGE
0xD7 PCI_EXPRESS
0xD5 DXE_SB_INIT
0xDA IDE_CONTROLLER
0xDB SATA_CONTROLLER
0xDD
0xE7SB_SM_BUS
ISA_ACPI_DRIVER
0xE8 ISA_BUS
0xE9 ISA_SERIAL
0xED BUS_PCI_UNDI
0xEC PCI_BUS
0xF6 BOOT_PRIORITY
0xF7 FVB_SERVICE
0xF8 ACPI_PLATFORM
0xFB PCI_HOT_PLUG
0xFC DXE_PLATFORM
0xFD PLATFORM_IDE
0x97 SMBIOS
0x98 MEMORY_SUB_CLASS
0x99...

Page 135

Chapter 4125
0x72 MONITER_KEY
0x73 LEGACY_BIOS
0x75 LEGACY_BIOS_PLATFORM
0x76 PCI_PLATFORM
0x6C ISA_FLOOPY
0x6D PS2_MOUSE
0x6E USB_BOT
0x6F USB_CBI0
0x74 USB_MOUSE
0xFA SETUP_UTILITY
0x90 FW_BLOCK_SERVICE
0x78 SMM_USB_LEGACY
0x86 GRAPHICS_CONSOLE
0x87 TERMINAL
0x8A DATA_HUB_STD_ERR
0x7C FAT
0x7D PARTITION
0x7E ENGLISH
0x7F FRENCH
0x9E HII_DATABASE
0x9F OEM_SETUP_BROWSER
0x8C OEM_BADGING_SUPPORT
0xF9 SETUP_MOUSE
0x72 MONITOR_KEY
0xBD PLATFORM_BDS
0x8D RESERVED
0x8E RESERVED
0x8F RESERVED
0xA0...

Page 136

126Chapter 4
Each SmmDriver entry point used in 80_PORT
CodeDescription
0xD4 SMM_ACCESS
0xDE SMM_CONTROL
0xCC SMM_BASE
0xD2 SMM_RUNTIME
0xDF SB_SMM_DISPATCH
0xD0 SMM_THUNK
0xCA SMM_ACPI_SW_CHILD
0xFE SMM_PLATFORM
0xD8 SMM_GMCH_MBI
0x90 SMM_FW_BLOCK_SERVICE
0x91 SMM_VARIABLE
0x92 SMM_IHISI
0x93 SMM_INT15_MICROCODE
0x94 SMM_PNP
0x95 SMM_INIT_PPM
0xD3 SMM_OEM_SERVICE 

Page 137

Chapter 5127
Jumper and Connector Locations
Mainboard Top View
ItemDescription
SW1 NAV50 Power Button
LED1 NAV50 Power LED
PJP1 AC-IN Jack
JP3 SIM Connector
JLVDS1 LCD Connector
JP18 LED/B Connector
JP23 NAV60 Power/B Connector
JKB1 Internal Keyboard Connector
JP11 T/P Connector
JP2 Bridge/B Connector
JBT1 B/T connector
Chapter 5 

Page 138

128Chapter 5
Mainboard Bottom View
ItemDescription
PJP2 Battery Connector
JCRT1 CRT Connector
JUSB1 USB Connector
JUSTB2 USB Connector
JHDD1 HDD Connector
JDIM1 WWAN Connector
JP12 FAN Connector
JDIM1 RAM Connector 

Page 139

Chapter 5129
Button Board
ItemDescription
SW1 T/P Left Button
SW2 T/P Right Button 

Page 140

130Chapter 5
LED Board
ItemDescription
LED1 Power/Suspend LED
LED2 Battery LED
LED3 Media LED
LED4 Num LED
LED5 Cap LED
LED6 WWAN/WLAN LED
LED7 BT LED 
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