Acer Aspire 6530 Service Guide
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Chapter 4131 POST Codes Tables These tables describe the chipset and core POST codes, functions, phases, and components for the POST. The following table details the chipset POST codes and functions used in the POST. CodeBeepsPOST Routine Description 02h Verify Real Mode 03h Disable Non-Maskable Interrupt (NMI) 04h Get CPU type 06h Initialize system hardware 08h Initialize chipset with initial POST values 09h Set IN POST flag 0Ah Initialize CPU registers 0Bh Enable CPU cache 0Ch Initialize caches to initial POST values 0Eh Initialize I/O component 0Fh Initialize the local bus IDE 10h Initialize Power Management 11h Load alternate registers with initial POST values 12h Restore CPU control word during warm boot 13h Initialize PCI Bus Mastering devices 14h Initialize keyboard controller 16h 1-2-2-3 BIOS ROM checksum 17h Initialize cache before memory autosize 18h 8254 timer initialization 1Ah 8237 DMA controller initialization 1Ch Reset Programmable Interrupt Controller 20h 1-3-1-1 Test DRAM refresh 22h 1-3-1-3 Test 8742 Keyboard Controller 24h Set ES segment register to 4 GB 26h Enable A20 line 28h Autosize DRAM 29h Initialize POST Memory Manager 2Ah Clear 512 KB base RAM 2Ch 1-3-4-1 RAM failure on address line xxxx* 2Eh 1-3-4-3 RAM failure on data bits xxxx* of low byte of memory bus 2Fh Enable cache before system BIOS shadow 30h 1-4-1-1 RAM failure on data bits xxxx* of high byte of memory bus 32h Test CPU bus-clock frequency 33h Initialize Phoenix Dispatch Manager 36h Warm start shut down 38h Shadow system BIOS ROM 3Ah Autosize cache 3Ch Advanced configuration of chipset registers 3Dh Load alternate registers with CMOS values
132Chapter 4 42h Initialize interrupt vectors 45h POST device initialization 46h 2-1-2-3 Check ROM copyright notice 48h Check video configuration against CMOS 49h Initialize PCI bus and devices 4Ah Initialize all video adapters in system 4Bh QuietBoot start (optional) 4Ch Shadow video BIOS ROM 4Eh Display BIOS copyright notice 50h Display CPU type and speed 51h Initialize EISA board 52h Test keyboard 54h Set key click if enabled 58h 2-2-3-1 Test for unexpected interrupts 59h Initialize POST display service 5Ah Display prompt Press F2 to enter SETUP 5Bh Disable CPU cache 5Ch Test RAM between 512 and 640 KB 60h Test extended memory 62h Test extended memory address lines 64h Jump to UserPatch1 66h Configure advanced cache registers 67h Initialize Multi Processor APIC 68h Enable external and CPU caches 69h Setup System Management Mode (SMM) area 6Ah Display external L2 cache size 6Bh Load custom defaults (optional) 6Ch Display shadow-area message 6Eh Display possible high address for UMB recovery 70h Display error messages 72h Check for configuration errors 76h Check for keyboard errors 7Ch Set up hardware interrupt vectors 7Eh Initialize coprocessor if present 80h Disable onboard Super I/O ports and IRQs 81h Late POST device initialization 82h Detect and install external RS232 ports 83h Configure non-MCD IDE controllers 84h Detect and install external parallel ports 85h Initialize PC-compatible PnP ISA devices 86h Re-initialize onboard I/O ports. 87h Configure Motherboard Configurable Devices (optional) 88h Initialize BIOS Data Area CodeBeepsPOST Routine Description
Chapter 4133 89h Enable Non-Maskable Interrupts (NMIs) 8Ah Initialize Extended BIOS Data Area 8Bh Test and initialize PS/2 mouse 8Ch Initialize floppy controller 8Fh Determine number of ATA drives (optional) 90h Initialize hard-disk controllers 91h Initialize local-bus hard-disk controllers 92h Jump to UserPatch2 93h Build MPTABLE for multi-processor boards 95h Install CD ROM for boot 96h Clear huge ES segment register 97h Fixup Multi Processor table 98h 1-2 Search for option ROMs. One long, two short beeps on checksum failure 99h Check for SMART Drive (optional) 9Ah Shadow option ROMs 9Ch Set up Power Management 9Dh Initialize security engine (optional) 9Eh Enable hardware interrupts 9Fh Determine number of ATA and SCSI drives A0h Set time of day A2h Check key lock A4h Initialize Typematic rate A8h Erase F2 prompt AAh Scan for F2 key stroke ACh Enter SETUP AEh Clear Boot flag B0h Check for errors B2h POST done - prepare to boot operating system B4h 1 One short beep before boot B5h Terminate QuietBoot (optional) B6h Check password (optional) B9h Prepare Boot BAh Initialize DMI parameters BBh Initialize PnP Option ROMs BCh Clear parity checkers BDh Display MultiBoot menu BEh Clear screen (optional) BFh Check virus and backup reminders C0h Try to boot with INT 19 C1h Initialize POST Error Manager (PEM) C2h Initialize error logging C3h Initialize error display function C4h Initialize system error handler CodeBeepsPOST Routine Description
134Chapter 4 * If the BIOS detects error 2C, 2E, or 30 (base 512K RAM error), it displays an additional word-bitmap (xxxx) indicating the address line or bits that failed. For example, 2C 0002 means address line 1 (bit one set) has failed. 2E 1020 means data bits 12 and 5 (bits 12 and 5 set) have failed in the lower 16 bits. Note that error 30 cannot occur on 386SX systems because they have a 16 rather than 32-bit bus. The BIOS also sends the bitmap to the port-80 LED display. It first displays the check point code, followed by a delay, the high-order byte, another delay, and then the low-order byte of the error. It repeats this sequence continuously. C5h PnPnd dual CMOS (optional) C6h Initialize notebook docking (optional) C7h Initialize notebook docking late C8h Force check (optional) C9h Extended checksum (optional) D2h Unknown interrupt CodeBeepsFor Boot Block in Flash ROM E0h Initialize the chipset E1h Initialize the bridge E2h Initialize the CPU E3h Initialize system timer E4h Initialize system I/O E5h Check force recovery boot E6h Checksum BIOS ROM E7h Go to BIOS E8h Set Huge Segment E9h Initialize Multi Processor EAh Initialize OEM special code EBh Initialize PIC and DMA ECh Initialize Memory type EDh Initialize Memory size EEh Shadow Boot Block EFh System memory test F0h Initialize interrupt vectors F1h Initialize Run Time Clock F2h Initialize video F3h Initialize System Management Mode F4h 1 Output one beep before boot F5h Boot to Mini DOS F6h Clear Huge Segment F7h Boot to Full DOS CodeBeepsPOST Routine Description
Chapter 4135 Chipset POST Codes The following table details the Chipset POST codes and components used in the POST. POST CodeFunctionPhaseComponent 0xA0 MRC Entry PEI chipset/MRC 0x01 Enable MCHBAR PEI chipset/MRC 0x02 Check ME existence PEI chipset/MRC 0x03 Check for DRAM initialization interrupt and reset fail PEI chipset/MRC 0x04 Determine the system Memory type based on first populated socketPEI chipset/MRC 0x05 Verify all DIMMs are DDR2 and SO-DIMMS, which are unbufferedPEI chipset/MRC 0x06 Verify all DIMMs are Non-ECC PEI chipset/MRC 0x07 Verify all DIMMs are single or double sided and not mixed PEI chipset/MRC 0x08 Verify all DIMMs are x8 or x16 width PEI chipset/MRC 0x09 Calculate number of Row and Column bits PEI chipset/MRC 0x10 Calculate number of banks for each DIMM PEI chipset/MRC 0x11 Determine raw card type PEI chipset/MRC 0x12 Find a common CAS latency between the DIMMS and the MCHPEI chipset/MRC 0x13 Determine the memory frequency and CAS latency to program PEI chipset/MRC 0x14 Determine the smallest common timing value for all DIMMS PEI chipset/MRC 0x17 Power management resume PEI chipset/MRC 0x18 Program DRAM type (DDR2/DDR3) and Power up sequence PEI chipset/MRC 0x19 Program the correct system memory frequency PEI chipset/MRC 0x20 Program the correct Graphics memory frequency PEI chipset/MRC 0x21 Early DRC initialization PEI chipset/MRC 0x22 Program the DRAM Row Attributes and DRAM Row Boundary registers PRE JEDEC.PEI chipset/MRC 0x23 Program the RCOMP SRAM registers PEI chipset/MRC 0x24 Program DRAM type (DDR2/DDR3) and Power up sequence PEI chipset/MRC 0x25 Program the DRAM Timing PEI chipset/MRC 0x26 Program the DRAM Bank Architecture register PEI chipset/MRC 0x27 Enable all clocks on populated rows PEI chipset/MRC 0x28 Program MCH ODT PEI chipset/MRC 0x29 Program tRD PEI chipset/MRC 0x30 Miscellaneous Pre JEDEC steps PEI chipset/MRC 0x31 Program clock crossing registers PEI chipset/MRC 0x32 Program the Egress port timings PEI chipset/MRC 0x33 Program the Memory IO registers PEI chipset/MRC 0x34 Perform steps required before JEDEC PEI chipset/MRC 0x35 Perform JEDEC memory initialization for all memory rows PEI chipset/MRC 0x36 Setup DRAM control register for normal operation and enable PEI chipset/MRC 0x37 Do ZQ calibration for DDR3 PEI chipset/MRC 0x38 Perform final Dra/Drb programming, Set the mode of operation for the memory channelsPEI chipset/MRC
136Chapter 4 0x39 Set Enhanced addressing mode for each channel PEI chipset/MRC 0x40 Perform steps required after JEDEC init PEI chipset/MRC 0x41 Program the receive enable reference timing control register PEI chipset/MRC 0x42 Post receive enable initialization PEI chipset/MRC 0x43 Enable sense amps. Reset read/write DQS pointers PEI chipset/MRC 0x44 Perform ME steps PEI chipset/MRC 0x45 Clear DRAM initialization bit in the ICH. PEI chipset/MRC 0x46 Program Thermal Management PEI chipset/MRC 0x47 Program TS on DIMM PEI chipset/MRC 0x48 Program TS on Board PEI chipset/MRC 0xAF Exit MRC PEI chipset/MRC 0xE0 #define MEM_ERR_BAD_DIMM (S11) PEI chipset/MRC 0xE1 #define MEM_ERR_ECC_DIMM (S06) PEI chipset/MRC 0xE2 #define MEM_ERR_SIDES (S07) PEI chipset/MRC 0xE3 #define MEM_ERR_WIDTH (S08, S10) PEI chipset/MRC 0xE4 #define MEM_ERR_TRFC (FindTrasTrpTrcd) PEI chipset/MRC 0xE5 #define MEM_ERR_CAS_LATENCY (S12, S13) PEI chipset/MRC 0xE6 #define MEM_ERR_REFRESH (ProgDrt) PEI chipset/MRC 0xE7 #define MEM_ERR_BL8 (S14) PEI chipset/MRC 0xE9 #define MEM_ERR_FREQUENCY (findTCLTacTClk, S13, S12, ProgramGraphicsFrequency, ProgMchOdt, GetPlatformData)PEI chipset/MRC 0xEA #define MEM_ERR_SIZE (S14) PEI chipset/MRC 0xEC #define MEM_ERR_TRAS (FindTrasTrpTrcd) PEI chipset/MRC 0xED #define MEM_ERR_TRP (FindTrasTrpTrcd) PEI chipset/MRC 0xEE #define MEM_ERR_TRCD (FindTrasTrpTrcd) PEI chipset/MRC 0xEF #define MEM_ERR_TWR (FindTrasTrpTrcd) PEI chipset/MRC 0xF0 #define MEM_ERR_RCVEN_FINDLOW (CalibrateRcvenForGroup)PEI chipset/MRC 0xF1 #define MEM_ERR_RCVEN_FINDEDGE (CalibrateRcvenForGroup)PEI chipset/MRC 0xF2 #define MEM_ERR_RCVEN_FINDPREAMBLE (CalibrateRcvenForGroup)PEI chipset/MRC 0xF6 #define MEM_ERR_RCVEN_PREAMBLEEDGE (CalibrateRcvenForGroup)PEI chipset/MRC 0xF3 #define MEM_ERR_RCVEN_FINDCENTER (CalibrateRcvenForGroup)PEI chipset/MRC 0xF4 #define MEM_ERR_TYPE (S11, S04) PEI chipset/MRC 0xF5 #define MEM_ERR_RAWCARD (S11) PEI chipset/MRC 0xFA #define MEM_ERR_SFF (ProgWrioDll) PEI chipset/MRC 0xFB #define MEM_ERR_THERMAL (ProgramThrottling) PEI chipset/MRC 0xA0xx Launch BIOS ACMSclean PEI chipset/MRC 0xA4xx Launch BIOS ACMScheck PEI chipset/MRC 0xE5 Wait for ME ready DXE HECI/iAMT 0xE6 ME Ready DXE HECI/iAMT POST CodeFunctionPhaseComponent
Chapter 4137 Core POST Code Table The following table details the core POST codes and functions used in SecureCore. POST CodeFunctionPhaseComponent 0x00 Early Microcode update for CAR CEI / SEC Core 0x01 Enable CAR CEI / SEC Core 0x02 CAR Done, initial stack CEI / SEC Core 0xEE unknown CPU ID to load uCode CEI / SEC CPU 0xEF unknown DT CPU to load uCode CEI / SEC CPU 0xnn File count found in a volume PEI Core 0x11 Debug Test driver for debug test PPI 1 (If install debugTest driver)PEI Core 0x22 Debug Test driver for debug test PPI 2 (If install debugTest driver)PEI Core 0x33 Debug Test driver for debug test PPI 3 (If install debugTest driver)PEI Core 0x44 Entry point of loadfile PEI Core 0x88 Entry point of apMuLoader PEI Core 0x80 A PEIM found PEI Core 0x82 PEIM not dispatched yet PEI Core 0x84 PEIM satisfies depex PEI Core 0x86 Image loaded but fail on security PEI Core 0x88 Executing a PEIM PEI Core 0x8A Processing notify event for newly installed PPI PEI Core 0x8C Handing off to next phase (DXE) PEI Core 0x8F Fail to hand off to next phase, system halt PEI Core 0x90 All PEIM dispatched! Going to DxeIpl PEI Core 0xCC AP Micro-code update PEI Core 0x20 S3 resume entry S3 resume Core 0x21 Start running Boot-time bootscripts S3 resume Core 0x22 Start running Run-time bootscripts S3 resume Core 0x23 End of S3 resume, jump back to Waking vector S3 resume Core 0x80 Initialize the chipset Crisis Recovery Core 0x81 Initialize the bridge Crisis Recovery Core 0x82 Initialize the CPU Crisis Recovery Core 0x89 Set Huge Segment Crisis Recovery Core 0x83 Initialize system timer Crisis Recovery Core 0x84 Initialize system I/O Crisis Recovery Core 0x88 Initialize Multi Processor Crisis Recovery Core 0x8A Initialize OEM special code Crisis Recovery Core 0x8B Initialize PIC and DMA Crisis Recovery Core 0x8C Initialize Memory type Crisis Recovery Core 0x8D Initialize Memory size Crisis Recovery Core 0x8F Initialize SMM Crisis Recovery Core 0x90 System memory test Crisis Recovery Core
138Chapter 4 0x91 Initialize interrupt vectors Crisis Recovery Core 0x92 Initialize Run Time Clock Crisis Recovery Core 0x99 Initialize security Crisis Recovery Core 0x93 Initialize video Crisis Recovery Core 0x94 Output one beep Crisis Recovery Core 0x98 USB Initialization Crisis Recovery Core 0x95 Initialize the installed boot devices Crisis Recovery Core 0x96 Clear Huge segment Crisis Recovery Core 0x97 Boot Crisis Disk Crisis Recovery Core 0x20 DXE starts DXE Core 0x30 BIOSPSM DXE Core 0x02 BIOSBlockIO DXE Core 0x00 BIOSPSM Exception Handler / Divide error BIOSPSM Core 0x38 Cannot locate LegacyRegion DXE BIOSPSM Core 0xB1 ACPISupport driver Installed DXE Core 0xE0 BDS Entry DXE Core 0x07 IA32 variable driver entry DXE Core 0x0D conspliter driver entry DXE Core 0x10 partition driver entry DXE Core 0x49 pciRootBridge driver entry DXE Core 0xC6 pciBusDriver entry DXE Core 0xE0 Go to legacy BIOS or BDS Entry Point DXE Core 0x90 Start Image DXE Core 0x90 Start Image Successfully DXE Core 0x90 Start Image Failed DXE Core 0x33 Debug Test driver for debug test PPI 1 DXE Core 0x22 Debug Test driver for debug test PPI 2 DXE Core 0x11 Debug Test driver for debug test PPI 3 DXE Core 0x02 Invalid event # for measuring Separator Event DXE TCG 0x02 Invalid event # for measuring Separator Event DXE TCG 0x02 PCR Index over limit (PCR > 23) DXE TCG 0x02 TCG copy memory failed DXE TCG 0x09 TCG log event failed DXE TCG 0x09 Setup event log failed DXE TCG 0x12 TIS set active locality failed DXE TCG 0x12 TIS relinquish active locality failed DXE TCG 0x12 TIS wait command ready failed (prepare to send) DXE TCG 0x12 TIS abort send command due to timeout DXE TCG 0x12 TIS abort sendAndGo command due to timeout DXE TCG 0x04 TIS wait bit set failed before send last byte DXE TCG 0x12 TIS abort command due to timeout before send last byte DXE TCG 0x04 TIS wait bit clear failed when sending last byte DXE TCG POST CodeFunctionPhaseComponent
Chapter 4139 0x22 TCG Physical Presence execution DXE TCG 0xB1 TCG DXE common pass through DXE TCG 0xE3 First Legacy BIOS Task table for legacy reset LBT Core 0x20 Verify that DRAM refresh is operating by polling the refresh bit in PORTB.LBT Core 0xDA Dummy PCIE Init entry, now handled by driver LBT Core 0x29 PMM (POST Memory Manager) init LBT Core 0xE5 WHEA init LBT Core 0x33 PDM (Post Dispatcher Manager) init LBT Core 0x01 IPMI init LBT Core 0xD8 ASF Init LBT Core 0x09 Set in-POST flag in CMOS that indicates we are in POST. If this bit is not cleared by postClearBootFlagJ(AEh), the TrustedCore on next boot determines that the current configuration caused POST to fail and uses default values for configuration.LBT Core 0x2B Enhanced CMOS init LBT Core 0xE0 EFI Variable Init LBT Core 0xC1 PEM (Post Error Manager) init LBT Core 0x3B Debug Service Init (ROM Polit) LBT Core 0xDC POST Update Error LBT Core 0x3A Autosize external cache and program cache size for enabling later in POST.LBT Core 0x0B Enable CPU cache. Set bits in cmos related to cache. LBT Core 0x0F Enable the local bus IDE as primary or secondary depending on other drives detected.LBT Core 0x10 Initialize Power Management. LBT Core 0x14 Verify that the 8742 keyboard controller is responding. Send a self-test command to the 8742 and wait for results. Also read the switch inputs from the 8742 and write the keyboard controller command byte.LBT Core 0x1A Initialize DMA command register with these settings: 1. Memory to memory disabled 2. Channel 0 hold address disabled 3. Controller enabled 4. Normal timing 5. Fixed priority 6. Late write selection 7. DREQ sense active 8. DACK sense active low. InitializeLBT Core 0x22 Reset the keyboard. LBT Core 0x40 Test A20 line LBT Core 0x67 Quick initialization of all Application Processors in a multi- processor systemLBT Core 0x32 Compute CPU speed. LBT Core 0x69 Initialize the handler for SMM. LBT Core POST CodeFunctionPhaseComponent
140Chapter 4 0x6B If CMOS is bad, load Custom Defaults from flash into CMOS. If successful, reboot.LBT Core 0x3C If CMOS is valid, load chipset registers with values from CMOS, otherwise load defaults and display Setup prompt. If Auto Configuration is enabled, always load the chipset registers with the Setup defaults (Rel 6.0).LBT Core 0x3D Load alternate registers with CMOS values LBT Core 0x42 Initialize interrupt vectors 0 thru 77h LBT Core 0x46 Verify the ROM copyright notice LBT Core 0x45 Initialize all motherboard devices. LBT Core 0x49 1. Size the PCI bus topology and set bridge bus numbers. 2. Set the system max bus number. 3. Write a 0 to the command register of every PCI device. 4. Write a 0 to all 6 base registers in every PCI device. 5. Write a -1 to the status register of every PCLBT Core 0xC6 Initialize note dock LBT Core 0xC5 PnPnd dual CMOS (optional) LBT Core 0x48 Verify that the equipment specified in the CMOS matches the hardware currently installed. If the monitor type is set to 00 then a video ROM must exist. If the monitor type is 1 or 2 set the video switch to CGA. If monitor type 3, set the video switch to mLBT Core 0xD1 Initialize BIOS stack LBT Core 0xD3 Setup E820h and WAD memory map LBT Core 0x24 Set segment-register addressability to 4 GB LBT Core 0xCC Redirect Int 10h to enable target board to use a remote serial video (PICO BIOS).LBT Core 0x8A Initialize Extended BIOS Data Area and initialize the mouse. LBT Core 0x9D Initialize Security Engine. LBT Core 0x55 USB Initialization LBT Core 0x52 Verify keyboard reset. LBT Core 0x54 Initialize keystroke clicker if enabled in Setup. LBT Core 0x76 Check status bits for keyboard-related failures. Display error messages on the screen.LBT Core 0x4A Initialize all video adapters in system LBT Core 0x4C Shadow video BIOS ROM if specified by Setup, and CMOS is valid and the previous boot was OK.LBT Core 0x59 Register POST Display Services, fonts, and languages with the POST Dispatch Manager.LBT Core 0x57 Initialize 1394 Firewire LBT Core 0xD6 Initialize PC card LBT Core 0x58 Test for unexpected interrupts. First do an STI for hot interrupts. Secondly, test the NMI for an unexpected interrupt. Thirdly, enable the parity checkers and read from memory, checking for an unexpected interrupt.LBT Core 0x3F ROMPolit memory init LBT Core 0xC4 Install the IRQ vectors (Sever Hotkey) LBT Core POST CodeFunctionPhaseComponent