Acer Aspire 5940g Service Guide
Have a look at the manual Acer Aspire 5940g Service Guide online for free. It’s possible to download the document as PDF or print. UserManuals.tech offer 720 Acer manuals and user’s guides for free. Share the user manual or guide on Facebook, Twitter or Google+.
Chapter 4151 Post Codes These tables describe the POST codes and descriptions during the POST. Chipset POST Codes The following table details the chipset POST codes and functions used in the POST. Port 80 Code Driver Name Port 80 CodeDriver Name 01 PeiEventLog 41 StatusCode 02 OemServices 42 Variable 03 SioInit CF SmmVariable 04 MonoStatusCode 43 EmuVariable 08 PentiumMCpuPeim A2 TcgDxe 09 PlatformStage1 A3 PhysicalPresence 0A Variable AE TpmDriver 0B IchInit AE TcgSmm 0D PlatformStage2 AE PhysicalPresenceReadyT oBoot 0E IchSmbusArpDisabled AD DataHubRecordPolicy 12 ClockGen 86 Undi 13 OpPresence 90 SNP 14 TcgPei 91 BC 15 FindFv 92 PxeDhcp4 2F DxeIpl 93 Ebc 10 LightMemoryInit 4D IsaBus 11 S3ResumeSoftSmi 4E IsaSerial 31 Crc32SectionExtract 6D Ps2Mouse A4 OemServices 4F IdeBus A5 EventLog 50 LightPciBus 32 ScriptSave 6E UsbBot 33 AcpiS3Save 6F UsbCbi0 34 SmartTimer 70 UsbCbi1 35 JpegDecoder 71 UsbKb 36 PcxDecoder 72 UsbMassStorage 8A PlatformBds 74 UsbMouse 37 MpCpu 8F Ehci 38 LegacyMetronome 73 Uhci 39 FtwLite 75 UsbBus 3A Runtime C2 SmmBase 3B MonotonicCounter C5 SmmDisp 3C WatchDogTimer C4 SmmReloc 3D SecurityStub C7 SmmRuntime 3E CpuIo C9 SmmThunk 3F Cf9Reset D8 OemServices 40 PcRtc 44 ChipsetInit
152Chapter 4 Port 80 Code Driver Name Port 80 CodeDriver Name C0 SmmAccess 7F Font (French) 46 PciHostBridge 8D Font (Chinese) 47 PciExpress B1 UnicodeCollation CD GmchMbi 5A ConPlatform 48 IchInit 5D ConSplitter 49 IdeController 79 GraphicsConsole 4A SataController 7A Terminal 4B IchSmbusLight 5E VgaClass C1 SmmControl 5B SaveMemoryConfig C8 Ich7MSmmDispatcher 5C AcpiSupport 4C IsaAcpiDriver 53 AcpiPlatform 52 Fwh 5F DataHub CE SmmFwh 7B DataHubStdErr 54 PciHotPlug 61 GenericMemoryTest 51 BootOptionPolicy 60 DiskIo 76 SetupUtility 7C Fat 55 Platform 7D Partition 56 PlatformIde 6B PciPlatform D9 Ppm 45 AlertStandardForma CC Platform A8 PciSerial D0 Ihisi A7 AsfInit f9 SetupMouse A9 IdeRController D1 Int15Microcode 63 Legacy8259 D2 SmmPnp 64 LegacyRegion 57 Smbios 65 LegacyInterrupt 58 MemorySubClass 66 BiosKeyboard 59 MiscSubclassDriver 67 BiosVideo AB SysPassword 68 MonitorKey AC PswdConsole 69 LegacyBios D7 HddPswdServiceBody 6A LegacyBiosPlatform A6 HddPswdService 77 LegacyMouse 80 HiiDatabase 78 SmmUsbLegacy 82 OemSetupBrowser AA AmtbxInvoke 7E Font(English) 83 OemBadgingSupport CodeBeepsPOST Routine Description 02h Verify Real Mode 03h Disable Non-Maskable Interrupt (NMI) 04h Get CPU type 06h Initialize system hardware 08h Initialize chipset with initial POST values 09h Set IN POST flag
Chapter 4153 0AhInitialize CPU registers 0Bh Enable CPU cache 0Ch Initialize caches to initial POST values 0Eh Initialize I/O component 0Fh Initialize the local bus IDE 10h Initialize Power Management 11h Load alternate registers with initial POST values 12h Restore CPU control word during warm boot 13h Initialize PCI Bus Mastering devices 14h Initialize keyboard controller 16h 1-2-2-3 BIOS ROM checksum 17h Initialize cache before memory autosize 18h 8254timer initialization 1Ah 8237DMA controller initialization 1Ch Reset Programmable Interrupt Controller 20h 1-3-1-1 Test DRAM refresh 22h 1-3-1-3 Test 8742 Keyboard Controller 24h Set ES segment register to 4 GB 26h Enable A20 line 28h Autosize DRAM 29h Initialize POST Memory Manager 2Ah Clear 512 KB base RAM 2Ch 1-3-4-1 RAM failure on address line xxxx* 2Eh 1-3-4-3 RAM failure on data bits xxxx* of low byte of memory bus 2Fh Enable cache before system BIOS shadow 30h 1-4-1-1 RAM failure on data bits xxxx* of high byte of memory bus 32h Test CPU bus-clock frequency 33h Initialize Phoenix Dispatch Manager 36h Warm start shut down 38h Shadow system BIOS ROM 3Ah Autosize cache 3Ch Advanced configuration of chipset registers 3Dh Load alternate registers with CMOS values 42h Initialize interrupt vectors 45h POST device initialization 46h 2-1-2-3 Check ROM copyright notice 48h Check video configuration against CMOS 49h Initialize PCI bus and devices 4Ah Initialize all video adapters in system 4Bh QuietBoot start (optional) 4Ch Shadow video BIOS ROM 4Eh Display BIOS copyright notice 50h Display CPU type and speed CodeBeepsPOST Routine Description
154Chapter 4 51hInitialize EISA board 52h Test keyboard 54h Set key click if enabled 58h 2-2-3-1 Test for unexpected interrupts 59h Initialize POST display service 5Ah Display prompt Press F2 to enter SETUP 5Bh Disable CPU cache 5Ch Test RAM between 512 and 640 KB 60h Test extended memory 62h Test extended memory address lines 64h Jump to UserPatch1 66h Configure advanced cache registers 67h Initialize Multi Processor APIC 68h Enable external and CPU caches 69h Setup System Management Mode (SMM) area 6Ah Display external L2 cache size 6Bh Load custom defaults (optional) 6Ch Display shadow-area message 6Eh Display possible high address for UMB recovery 70h Display error messages 72h Check for configuration errors 76h Check for keyboard errors 7Ch Set up hardware interrupt vectors 7Eh Initialize coprocessor if present 80h Disable onboard Super I/O ports and IRQs 81h Late POST device initialization 82h Detect and install external RS232 ports 83h Configure non-MCD IDE controllers 84h Detect and install external parallel ports 85h Initialize PC-compatible PnP ISA devices 86h Re-initialize onboard I/O ports. 87h Configure Motherboard Configurable Devices (optional) 88h Initialize BIOS Data Area 89h Enable Non-Maskable Interrupts (NMIs) 8Ah Initialize Extended BIOS Data Area 8Bh Test and initialize PS/2 mouse 8Ch Initialize floppy controller 8Fh Determine number of ATA drives (optional) 90h Initialize hard-disk controllers 91h Initialize local-bus hard-disk controllers 92h Jump to UserPatch2 93h Build MPTABLE for multi-processor boards 95h Install CD ROM for boot CodeBeepsPOST Routine Description
Chapter 4155 96hClear huge ES segment register 97h Fixup Multi Processor table 98h 1-2Search for option ROMs. One long, two short beeps on checksum failure 99h Check for SMART Drive (optional) 9Ah Shadow option ROMs 9Ch Set up Power Management 9Dh Initialize security engine (optional) 9Eh Enable hardware interrupts 9Fh Determine number of ATA and SCSI drives A0h Set time of day A2h Check key lock A4h Initialize Typematic rate A8h Erase F2 prompt AAh Scan for F2 key stroke ACh Enter SETUP AEh Clear Boot flag B0h Check for errors B2h POST done - prepare to boot operating system B4h 1One short beep before boot B5h Terminate QuietBoot (optional) B6h Check password (optional) B9h Prepare Boot BAh Initialize DMI parameters BBh Initialize PnP Option ROMs BCh Clear parity checkers BDh Display MultiBoot menu BEh Clear screen (optional) BFh Check virus and backup reminders C0h Try to boot with INT 19 C1h Initialize POST Error Manager (PEM) C2h Initialize error logging C3h Initialize error display function C4h Initialize system error handler C5h PnPnd dual CMOS (optional) C6h Initialize notebook docking (optional) C7h Initialize notebook docking late C8h Force check (optional) C9h Extended checksum (optional) D2h Unknown interrupt CodeBeepsFor Boot Block in Flash ROM E0h Initialize the chipset E1h Initialize the bridge CodeBeepsPOST Routine Description
156Chapter 4 * If the BIOS detects error 2C, 2E, or 30 (base 512K RAM error), it displays an additional word-bitmap (xxxx) indicating the address line or bi ts that failed. For example, 2C 0002 means address line 1 (bit one set) has failed. 2E 1020 means data bits 12 and 5 (bits 12 and 5 set) have failed in the lower 16 bits. Note that error 30 cannot occur on 386SX systems because they have a 16 rather than 32-bit bus. The BIOS also sends the bitmap to the port-80 LED display. It first displays th e check point code, followed by a delay, the high-order byte, another delay, and then the low-order byte of the error. It repeats this sequence continuously. E2h Initialize the CPU E3h Initialize system timer E4h Initialize system I/O E5h Check force recovery boot E6h Checksum BIOS ROM E7h Go to BIOS E8h Set Huge Segment E9h Initialize Multi Processor EAh Initialize OEM special code EBh Initialize PIC and DMA ECh Initialize Memory type EDh Initialize Memory size EEh Shadow Boot Block EFh System memory test F0h Initialize interrupt vectors F1h Initialize Run Time Clock F2h Initialize video F3h Initialize System Management Mode F4h 1 Output one beep before boot F5h Boot to Mini DOS F6h Clear Huge Segment F7h Boot to Full DOS CodeBeepsFor Boot Block in Flash ROM
Chapter 5157 Jumper and Connector Locations Top View ItemDescriptionItemDescription J56 Subwoofer Connector JP47 Touch pad Connector SW1 Power button JP33 VR board Connector JP7 Backlight on/off Connector JP54 Digital MIC Connector JLVDS Speaker (Right) Connector SW2 Touch pad lock button JP2 Launch board Connector JP3 board to board Connector JP34 Keyboard backlight Connector JP37 Blue tooth Connector JEXP1 New (Express) card Connec tor JP44 Finger Print Connector JKB1 Keyboard Connector LED11 HDD_LED JP38 POWER SAVING Co nnector LED10 NUM_LED JP48 USB cable Connector LED9 CAPS_LED JP55 Speaker Connector LED1 PWR_LED JP6 Media board Connector LED6 Battery charger_LED JP39 LOGO Backlight Connector LED16 Touch pad lock_LED Chapter 5
158Chapter 5 Bottom View ItemDescriptionItemDescription PCN1 AC-IN Connector JLINE1 LINE IN JACK JRJ45 RJ45 Connector JMIC1 MIC IN JACK JCRT1 CRT Connector JHP1 Head-Phone Jack JP32 Fan Connector JCPU1 CPU Socket JMXM2 MXM Connector JDIMM2 Memory DIMM2 Connector JHDMI1 HDMI Connector JDIMM1 Memory DIMM1 Connector JESATA1 ESATA Connector PJP1 Battery Connector JUSB2 USB Connector JSATA1 HDD Connector JUSB3 USB Connector JSATA2 ODD Connector
Chapter 5159 LS-5011P LCD Backlight Board ItemDescription JP1 Backlight on/off Connector
160Chapter 5 LS-5012P Launch Board ItemDescription LED1 Backup LED LED2 Bluetooth LED LED3 Wireless LED