Yamaha Tyros 3 Service Manual

							41 Tyros3
PIN
NO.I/OFUNCTION
NAMEPIN
NO.I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21P1
3D0D1D2D3D4D5D6/CNTR0
D7/CNTR1P50P51P52P53P20/SCKP21/SOUTP22/SINRESET
CNVSSXOUTXINVSS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
O
I
–Port P1 serves as a 4-bit I/O port
Each pin of port D has an independent 1-bit 
wide I/O function
Each pin of port D has an independent 1-bit wide I/O function / CNTR0
Each pin of port D has an independent 1-bit wide I/O function / CNTR1
Port P5 serves as a 4-bit I/O port
Port P2 serves as a 3-bit I/O port / Serial I/O data transfer synchronous clock I/O pinPort P2 serves as a 3-bit I/O port / Serial I/O data output pinPort P2 serves as a 3-bit I/O port / Serial I/O data input pinAn N-channel open-drain I/O pin for a system resetConnect CNVSS to VSS and apply “L” (0V) to CNVSS certainly
I/O pins of the main clock generating circuit 
Ground22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42V
DDVDCE
P30/INT0
P31/INT1
P32P33P60/AIN0P61/AIN1P62/AIN2P63/AIN3P40/AIN4P41/AIN5P42/AIN6P43/AIN7P00P01P02P03P10P11P12
–
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/OPower supply +5V This pin is used to operate/stop the voltage drop detection circuitPort P3 serves as a 4-bit I/O port / INT0 pin 
and INT1 pin accept external interrupts
Port P3 serves as a 4-bit I/O port 
Port P6 serves as a 4-bit I/O port / A/D
converter analog input pins
Port P4 serves as a 4-bit I/O port / A/D 
converter analog input pins
Port P0 serves as a 4-bit I/O port
Port P1 serves as a 4-bit I/O port
M34519M6-521FP (X5646200) CPLD (Complex Programmable Logic Device)PNL: IC2, 3
PNR: IC2, 3
PIN
NO.I/O FUNCTION NAMEPIN
NO.I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24BGRES
RXVDD25RX+
RX-
RXGND
TXGND
TX+
TX-
TXVDD25SD7
SD6
SD5
SD4
SD3
GND
SD2
SD1
SD0
EEDIO
EECK
EECS
SD15
V
DDSD14I/O
-
I/O
I/O
-
-
I/O
I/O
-
I/O
I/O
I/O
I/O
I/O
-
I/O
I/O
I/O
I/O
O
O
I/O
-
I/OBandgap pin
Power output +2.5 V
TP RX input
RX ground
TX ground
TP TX output
Power output +2.5 V
Processor data bus
Digital ground
Processor data bus
IO data to EEPROM
Clock to EEPROM
Chip select to EEPROM
Processor data bus
Digital power supply +3.3 V
Processor data bus25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48SD13
SD12
SD11
SD10
SD9
V
DDSD8
CMD
GND
INT
IOR
IOW
CS
LED2
LED1
PWRST
TEST
V
DDX2
X1
GND
SD
RXGND
BGGNDI/O
I/O
I/O
I/O
I/O
-
I/O
I
-
O
I
I
I
O
O
I
I
-
O
I
-
I
-
-Processor data bus
Digital power supply +3.3 V
Processor data bus
Command type
Digital ground
Interrupt request
Processor read command
Processor write command
Chip select
Link/Active LED
Speed LED
Power on reset
Operation mode
Digital power supply +3.3 V
Crystal 25 MHz out
Crystal 25 MHz in
Digital ground
Fiber-optic signal detect
RX ground
Bandgap ground
DM9000AEP (X7029A00) LAN CONTROLLERDM: IC210
PIN
NO.I/O
FUNCTION
NAMEPIN
NO.I/O
FUNCTION NAME
1
2
3
4
5
6
7
8AINR
AINL
CKS1
VCOM
AGND
VA
VD
DGNDI
I
I
O
-
-
-
-Rch Analog input pin
Lch Analog input pin
Mode select 1 pin
Common voltage output pin
Analog ground
Analog power supply
Digital power supply
Digital ground9
10
11
12
13
14
15
16SDTO
LRCK
MCLK
SCLK
PDN
DIF
CKS2
CKS0O
I/O
I
I/O
I
I
I
IAudio serial data output pin
Output channnel clock pin
Master clock input pin
Audio serial data clock pin
Power down mode pin
Audio interface format pin
Mode select 2 pin
Mode select 0 pin
DM: IC902AK5381VT-E2 (X5219A0R) ADC (Analog to Digital Converter) 
						

							Tyros3
42
PIN
NO.I/O FUNCTION NAMEPIN
NO.I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14DV
SSDVDDMCLK
PDN
BICK
SDATA
LRCK
SMUTE/CSNDFS0/CAD0DEM0/CCLKDEM1/CDTI
DIF0
DIF1
DIF2-
-
I
I
I
I
I
I
I
I
I
I
I
IDigital ground
Digital power supply +3.3 V
Master clock input
Power-down mode
Audio serial data clock
Audio serial data input
L/R clock
Soft mute/Chip select
Sampling speed mode select/Chip address 0De-emphasis enable 0/Control data clock
De-emphasis enable 1/Control data input
Digital input format15
16
17
18
19
20
21
22
23
24
25
26
27
28TTL
VREFL
VREFH
AV
DDAVSSAOUTR-
AOUTR+
AOUTL-
AOUTL+
VCOM
P/S
TST1/DZFL
TST2/CAD1
ACKS/DZFR
I
I
I
-
-
O
O
O
O
O
I
O
I
I/OCMOS/TTL level select
Low level voltage reference input
High level voltage reference input
Analog power supply +5 V
Analog ground
Rch negative analog output
Rch positive analog output
Lch negative analog output
Lch positive analog output
Common voltage output
Parallel/serial select
Test 1/Lch zero input detect
Test 2/Chip address 1
Master clock auto setting mode/Rch zero input detect
AK4396VF-E2(X8324A00) DAC (Digital to Analog Converter)DM: IC900, 901
PIN
NO.I/O FUNCTION NAMEPIN
NO.I/O FUNCTION NAME
DS99R103TSQX/NOPB (X9323A00) LV D SDM: IC8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
DCAOFF
VssL
V
DDL
DCBOFF
TPWDNB
TCLK
TRFB
VODSEL
RESRVD
V
DDPT1
VssPT1
V
DDPT0
VssPT0
DENI
I
I
I
I
I
I
I
I
I
I
I
Transmitter Parallel Interface Data Inputs Pins.Tie LOW if unused.
RESERVED - This pin MUST be tied LOW.
Digital Ground, Tx Logic Ground
Digital Voltage supply, Tx Logic Power
RESERVED - This pin MUST be tied LOW.
Transmitter Power Down Bar
ÔTPWDNB = H; Transmitter is Enabled and ON.ÔTPWDNB = L; Transmitter is in power down mode (Sleep),LVDS Driver DOUT (+/-) Outputs are in TRI-STATE stand-by 
mode, PLL is shutdown to minimize power consumption.
Transmitter Parallel Interface Clock Input Pin. 
Strobe edge set by TRFB configuration pin
Transmitter Clock Edge Select Pin
ÔTRFB = H; Parallel Interface Data is strobed on the Rising Clock EdgeÔTRFB = L; Parallel Interface Data is strobed on the Falling Clock EdgeVOD Level SelectÔVODSEL = L; LVDS Driver Output is ~400 mV (RL = 100 
)ÔVODSEL = H; LVDS Driver Output is ~800 mV (RL = 100
)For normal applications, set this pin LOW. For long cable ap- 
plications where a larger VOD is required, set this pin HIGH.
RESERVED - This pin MUST be tied LOW.
Analog Voltage supply, PLL Power
Analog Ground, PLL Ground
Analog Voltage supply, VCO Power
Analog Ground, VCO Ground
Transmitter Data Enable
ÔDEN = H; LVDS Driver Outputs are Enabled (ON).ÔDEN = L; LVDS Driver Outputs are Disabled (OFF),Transmitter LVDS Driver DOUT (+/-) Outputs are in TRI- 
STATE, PLL still operational and locked to TCLK.
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48DOUT-
DOUT+
VssDR
V
DDDR
PRE
Vss
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
V
DDT
VssT
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
V
DDIT
VssIT
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Transmitter LVDS Inverted (-) Output. This output is inten- 
ded to be loaded with a 100 ohm load to the DOUT- pin.Transmitter LVDS True (+) Output. This output is intend- 
ed to be loaded with a 100 ohm load to the DOUT+ pin.
Analog Ground, LVDS Output Ground
Analog Voltage Supply, LVDS Output Power
PRE-emphasis select pin.
ÔPRE = (RPRE ¾ 3 k
); Imax = [(1.2/R) 20], Rmin = 3 k
ÔPRE = H or floating; pre-emphasis is disabledESD Ground
Transmitter Parallel Interface Data Inputs Pins. 
Tie LOW if unused.
Digital Voltage supply, Tx Serializer Power
Digital Ground, Tx Serializer Ground
Transmitter Parallel Interface Data Inputs Pins. 
Tie LOW if unused.
Digital Voltage supply, Tx Input Power
Digital Ground, Tx Input Ground
Transmitter Parallel Interface Data Inputs Pins. 
Tie LOW if unused. 
						

							43 Tyros3
PIN
NO.I/O FUNCTION NAMEPIN
NO.I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32P50/A8
P51/A9
P51/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
Vss0
V
DD0
P30
P31
P32/SDA0P33/SCL0P34
P35
P36
P20/SI30
P21/SO30P22/SCK30P23/RxD0P24/TxD0P25/ASCK0VDD1
AVss
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
I
I
I
I
I
I
IPort 5 / Higher address bus
Ground
Power supply +5 V
Port 3
Port 3 / Serial data input/output
Port 3 / Serial clock input/output
Port 3
Port 2 / Serial data input
Port 2 / Serial data output
Port 2 / Serial clock input/output
Port 2 / Serial data input
Port 2 / Serial data output
Port 2 / Serial clock input/output
Power supply +5 V
Ground
Port 1 / A/D converter analog input33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64P10/ANI0AVREFAVDDRESET
XT2
XT1
IC
X2
X1
Vss1
P00/INTP0
P01/INTP1
P02/INTP2
P03/INTP3/ADTRGP70/TI00/TO0P71/TI01P72/TI50/TO50
P73/TI51/TO51
P74/PCL
P75/BUZ
P64/RD
P65/WR
P66/WAIT
P67/ASTB
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
A47/AD7I
I
-
I
-
I
-
-
I
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/OPort 1 / A/D converter analog input
A/D converter reference voltage input
Analog power supply +5 V
System reset input
Subsystem clock oscillation
Internally connected
Main system clock oscillation
Ground
Port 0 / External interrupt request input
Port 0 / External interrupt request input / Trigger signai inputPort 7 / External count clock input / 16-bit timer/event counter 0 outputPort 7 / Capture trigger inputPort 7 / External count clock input / 8-bit timer/event counter 50 output
Port 7 / External count clock input / 8-bit timer/event counter 51 output
Port 7 / Clock output
Port 7 / Buzzer output
Port 6 / Strobe signal output for reading
Port 6 / Strobe signal output for writing
Port 6 / Wait insertion
Port 6 / Strobe output
Port 4 / Lower address/data bus
μPD780031AYGK-N09(XZ916300) E-PNS2a LED/SWITCH DRIVERPNL: IC1
PNR: IC1
PIN
NO.I/O FUNCTION NAMEPIN
NO.I/O FUNCTION NAME
DS99R104TSQX/NOPB (X9324A00) LV D SLCL: IC2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25RPWDNB
RESRVD
ROUT[23:16]
ROUT[23:16]
ROUT[23:16]
ROUT[23:16]
VDDOR3
VssOR3
ROUT[23:16]
ROUT[23:16]
ROUT[23:16]
ROUT[23:16]
ROUT[15:8]
ROUT[15:8]
ROUT[15:8]
ROUT[15:8]
LOCK
RCLK
VssOR2
V
DDOR2ROUT[15:8]
ROUT[15:8]
ROUT[15:8]
ROUT[15:8]
ROUT[7:0]I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
OReceiver Data Enable
ÔREN = H; ROUT[23-0] and RCLK are Enabled (ON).ÔREN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs are in TRI- 
STATE, PLL still operational and locked to TCLK.
RESERVED - This pin MUST be tied LOW.
LVDS SERIAL INTERFACE PINS
Receiver Parallel Interface Data Outputs _ Group 3
Digital Voltage supply, LVCMOS Output PowerDigital Ground, LVCMOS Output Ground
Receiver Parallel Interface Data Outputs _ Group 3
Receiver Parallel Interface Data Outputs - Group 2
LOCK indicates the status of the receiver PLLÔ LOCK = H; receiver PLL is lockedÔ LOCK = L; receiver PLL is unlocked, 
ROUT[23-0] and RCLK are TRI-STATED
Parallel Interface Clock Output Pin. 
Strobe edge set by RRFB configuration pin.
Digital Ground, LVCMOS Output Ground
Digital Voltage supply, LVCMOS Output Power
Receiver Parallel Interface Data Outputs - Group 2
Receiver Parallel Interface Data Outputs - Group 1
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48ROUT[7:0]
ROUT[7:0]
ROUT[7:0]
VssOR1
V
DDOR1
ROUT[7:0]
ROUT[7:0]
ROUT[7:0]
ROUT[7:0]
VssR0
V
DDR0
VDDR1
VssR1
V
DDIR
VssIR
RIN+
RIN
-
RRFB
VssPR1
V
DDPR1
VssPR0
V
DDPR0
RENO
O
O
O
O
O
O
O
O
I
I
I
I
Receiver Parallel Interface Data Outputs - Group 1
Digital Ground, LVCMOS Output GroundDigital Voltage supply, LVCMOS Output Power
Receiver Parallel Interface Data Outputs - Group 1
Digital Ground, Logic Ground
Digital Voltage supply, Logic Power
Digital Voltage supply, Logic Power
Digital Ground, Logic Ground
Analog LVDS Voltage supply, Power
Analog LVDS Ground
Receiver LVDS True (+) Input
This input is intended to be terminated with a 
100 ohm load to the RIN+ pin.
Receiver LVDS Inverted (
-) Input
This input is intended to be terminated with a 
100 ohm load to the RIN
- pin.
Receiver Clock Edge Select Pin
ÔRRFB = H; ROUT LVCMOS Outputs strobed on the Rising Clock Edge.ÔRRFB = L; ROUT LVCMOS Outputs strobed on the Falling Clock Edge.Analog Ground, PLL VCO Ground
Analog Voltage supply, PLL VCO Power
Analog Ground, PLL Ground
Analog Voltage supply, PLL Power
Receiver Data Enable
ÔREN = H; ROUT[23-0] and RCLK are Enabled (ON).ÔREN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs are in TRI- 
STATE, PLL still operational and locked to TCLK. 
						

							Tyros3
44
 IC BLOCK DIAGRAM
SN74AHC14PWR (X3098A00)
SN74LV14APWR (X6688A0R)
TC74VHC14FT (XV890B0R)
DM: IC4, 5, 7, 510
Hex Inverter 
1
2
3
4
5
6
7
1A
1Y
2A
2Y
3A
3Y
GND14
13
12
11
10
9
8
VDD
6A
6Y
5A
5Y
4A
4Y
SN74LV21APWR (X2377A0R)
TC74VHC21FT (X5542A00)
DM: IC20
Dual 4 Input AND
1
2
31A
NC
41C
51D
61Y
7GND1B
14
13
12Vcc
2C
11NC
102B
92A
82Y 2D
SN74LV32APWR (X5647A00)DM: IC6
SN74LVC32APWR (X5405A00)DM: IC212
Quad 2 Input OR
1
2
31A
1Y
42A
52B
62Y
7GND1B
14
13
12Vcc
4A
114Y
103B
93A
83Y 4B
SN74ACT74PWR (X9486A00)
TC74ACT74FT (X6536A0R)
DM: IC404
Dual D-Type Flip-Flop 
INPUTS OUTPUTS
PR CLR CLK D Q Q
L
H
H
L
H
Q
O
H
L
H
H
L
Q
O
X
X
X
H
L
X X
X
X
f
f
L H
L
L
H
H
H L
H
L
H
H
H
1
2
3
4
5
6
7
1CLR
1D
1CK
1PR
1Q
1Q
GND14
13
12
11
10
9
8
VCC
2CLR
CLR2DD
2CKCK
2PRPR
2Q
2Q
Q Q
CLRD
CK
PR
QQ
SN74LVC138APWR (X7074A00)
DM: IC502
3 to 8 Demultiplexer
1
2
3
4
5
6
7
AASelect
Enable
OutputOutput BB
CC
G2AG2A
G2B
G2B
G1
G1
Y7Y7 Y5Y4 Y3 Y2 Y1 Y0
Y6
16
15
14
13
12
11
10
Vcc
YO
Y1
Y2
Y3
Y4
Y5
8GND9Y6
HD74LVC139TELL (X4963A0R)
SN74LVC139APWR (X7227A00)
DM: IC24, 25
Dual 2 to 4 Demultiplexer
1
2
3
4
5
6
7
1G
1A
1B
1Y0
1Y1
1Y2
1Y3
AG
B
Y0
Y1
Y2
Y3
16
15
14
13
12
11
10
Vcc
2G
2A
2B
2Y0
2Y1
2Y2
8GND92Y3
Y2
Y3Y1 Y0BA G
SN74AHCT245PWR (X2709A0R)
TC74VHCT245AFT (XT744B0R)DM: IC200
SN74LV245APWR (X3693A0R)
TC74VHC245FT (XU797B00)DM: IC201
SN74LVC245APWR (XZ287A0R)DM: IC16•19, 21, 22, 808•811
Octal 3-State Bus Transceiver  
1 D1R
2
3
4
5
6
7
8
9
10 A1
A2
A3
A4
A5
A6
A7
A8
GND11 12 13 14 15 16 171819 20V
CC
G
B1
B2
B3
B4
B5
B6
B7
B8
SN74LV273APWR (X5074A00)
TC74VHC273FT (X7942B00)
DM: IC23
Octal D-Type Flip-Flop
CLEAR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GNDVCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLOCK120
219
318
417
516
615
714
813
912
1011
Q
DCKCL
D
QCK
CL
Q
DCKCL
D
QCK
CL
D
Q CK
CL
Q
D CK CL
D
Q CK
CL
Q
D CK CL
SN74LVC1G32DCKR (X5825A00)
DM: IC213 
2-Input OR Gate
15
2
3
4
IN B
GNDVcc
OUT Y IN A
INPUTSFUNCTION TABLE
OUTPUT
AB Y
H
H
L X
H
L H
X
L 
						

							45 Tyros3
1
2
3
41
2
3
4
8
7
6
5
8
7
6
5 CTALA
FLAGB
CTALBOUTA
VDD
GND
OUTB FLAGA
CTALA
FLAGB
CTALB FLAGAOUTA
VDD
GND
OUTB
Thermal
ShutdownOscillator Control
Logic Over
Current
Detector
Over
Current
DetectorCharge
Pump
Control
LogicCharge
Pump1
4CTRLA
CTRLBControl input
Error flag output
Switch output
Switch input Ground FLAGA
FLAGB
OUTB
OUTA
GND
VDD 2
3
5
8
6
7Pin Name Pin No. Pin Function
BD6517F-E2 (X7951A00)
DM: IC206
High Side Switch
1
2
3
4
5
6
7
8
9 1011 1213 14 15 16OUT1
IN1
VDD
NC
NC
IN2
OUT2
Balance/Indivdual
Volume control Refarence Voltage
Filter
NC
GND
Volume/Volume2 control
Noise reduction
Balance/VOLUME2
Pass/VCA Switching
Switching
Controled
Voltage
Regulater
M51132L (XE470A0R)
AJK: IC3
VCA
PCA9564PW (X6155A0R)
DM: IC208
Parallel bus to I2C-bus controller
D0
D1
D2
D3
D4
D5
D6
D7
DNU
V
SS
VDD
SDA
SCL
RESET
INT
A1
A0
CE
RD
WR
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SD7SD6SD5SD4SD3SD2SD1SD0I2CDAT – DATA REGISTER – READ/WRITEBUS BUFFERSDA CONTROL
AAENSIOSTA
STO
SI
FILTER
SCL CONTROL
ENSIO STA STO SI
FILTER
PCA9564SDA
SCL
TETO6TO5TO4TO3TO2TO1TO0I2CTO – TIMEOUT REGISTER – WRITE ONLY
BIT7BIT6BIT5BIT4BIT3BIT2BIT1BIT0I2CADR – OWN ADDRESS – READ/WRITE
ST7ST6ST5ST4ST3ST2ST1ST0I2CST – SATATUS REGISTER – READ ONLY
AAENSIOSTASTOSICR2CR1CR0I2CCON – CONTROL REGISTER – READ/WRITE
CR0
CR1
CR2CLOCK SELECTOR 
OSCILLATORCONTROL BLOCK
CE WRRD
INT
RESETA1 A0 VDD
A1 A0
01
00
10
00
11
INTERRUPT CONTROLPOWER–ON
RESET
CONTROL SIGNALS
D7 D6 D5 D4 D3 D2 D1 D0DATA
12765438
19
18
1311121617151420910DNV:  Do not use
Vss:  Ground
TC7SH08FU(XR680A00)
DM: IC202, 209, 812, 813
2 Input AND Gate
15
2
3
4
IN B
GNDVcc
OUT Y IN A
TC7SH32FU(XW633A0R)
DM: IC27, 211
TC7SET32FU(XW814A0R)
DM: IC9
2-Input OR Gate
15
2
3
4
IN B
GNDVcc
OUT Y IN A
TC7WU04FU (XQ805A00)
DM: IC400, 401
Triple Inverter
1
2
3
48
7
6
5
1A
GND3Y
2AVcc
2Y 1Y
3A 
						

							Tyros3
46
TC7WT126FU(X7703A00)
DM: IC405
Dual Bus Buffer
1
2
3
48
7
6
5
G1
GNDA1
Y2Vcc
A2 G2
Y1
LA6517M-TRM-E-R(XT131A0R)
AJK: IC6
Dual Power Operational Amplifier
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Thermal Shut
Doun and
Current LimiterAmp1
Amp2
NC
NC
OUT 1
VCC
OUT 2
VEE
NC
NC
NC NC
INPUT -2 INPUT +2 INPUT +1 INPUT -1 NC NC
NJM2068M-D(TE2) (X3505A00)AJK: IC4, 5, 7, 8  DM: IC903, 904, 906
NJM2100V(X2538A00)EMKS-FD: IC002
NJM4580E(TE2)(X2331A0R)AJK: IC2
Dual Operational Amplifier
1
2
3
4-V8
7
6
5
Output A+V
Non-Inverting
Input A
-DC Voltage Supply+DC Voltage
Supply
Output B
Inverting
Input B
Non-Inverting
Input B Inverting
Input A+-
+-
NE5532DR(X5482A00)
DM: IC903, 904, 906
Dual Operational Amplifier
1
2
3
48
7
6
5
Output A+V
Non-Inverting
Input A
Ground+DC Voltage
Supply
Output B
Inverting
Input B
Non-Inverting
Input B Inverting
Input A+-
+- 
						

							47
Tyros3
 CIRCUIT BOARDS
AJK Circuit Board (X6041D0) ............................................................................................. 48
CK Circuit Board (X6042C0) ............................................................................................... 58
DJK Circuit Board (X6042C0) ............................................................................................. 54
DM Circuit Board (X9371C0) .......................................................................................... 50/52
EMKS-FD Circuit Board (X6577A0) ............................................................................... 72/73
EN Circuit Board (X9411B0) ................................................................................................ 61
HDSB Circuit Board (X6800B0) .......................................................................................... 57
HP Circuit Board (X6042C0) ............................................................................................... 56
LCL Circuit Board (X9412C0) ........................................................................................ 72/73
LCR Circuit Board (X9412C0) ........................................................................................ 74/75
MICVR Circuit Board (X9409C0) ......................................................................................... 58
MK61L Circuit Board (X6578C0) .................................................................................... 76/77
MKH-D Circuit Board (X6579B0) .................................................................................... 72/74
SPOL Circuit Board (X6042C0) ........................................................................................... 56
SPOR Circuit Board (X6042C0) .......................................................................................... 56
PNC Circuit Board (X9411B0) ............................................................................................. 60
PNR Circuit Board (X9410C0) ........................................................................................ 62/64
PNL Circuit Board (X9409C0) ........................................................................................ 68/70
PNLS Circuit Board (X9409C0) ........................................................................................... 59
USB Circuit Board (X9410C0) ............................................................................................. 59
Note:  See parts list for details of circuit board component parts. 
						

							48 Tyros3
 AJK Circuit Board
2NA-WM18510
B
B
A
A
to HP-CN100
to SPOR-CN302
to SPOL-CN303L
R
TO SUB WOOFER
LINE IN /  MIC
TRIM
MIN MAX
L/L+R/ MICL/L+R RRAUX OUT / 
LOOP SEND
(LEVEL FIXED) 
						

							49 Tyros3
Component side2NA-WM18510  
Pattern sideScale: 90/100
A
A
to MICVR-CN301to SWITCHING
 POWER
 SUPPLY-CN3to DM-CN2to DM-CN900
TRIM
MIN MAX
L/L+R RAUX IN / LOOP RETURN
LINE OUT
MAIN
L/L+R R 1 2SUB
B
B 
						

							50 Tyros3
 DM Circuit Board
2NA-WM15450
C
C
to AJK-CN7
to AJK-CN1to LCR-CN202
to PNR-CN4
N.C.