Yamaha Tyros 3 Service Manual

							31 Tyros3
PIN
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
11 0
111
11 2
11 3
11 4
11 5
11 6
11 7
11 8
11 9
120
Vcc-RTC
XTAL2
EXTAL2
Vss-RTC
MD1
MD2
NMI
IRQ0/IRL0_/PTH[0]
IRQ1/IRL1_/PTH[1]
IRQ2/IRL2_/PTH[2]
IRQ3/IRL3_/PTH[3]
IRQ4/PTH[4]
VEPWC
VCPWC
MD5
/BREQ
/BACK
VssQ
CKIO2
VccQ
D31/PTB[7]
D30/PTB[6]
D29/PTB[5]
D28/PTB[4]
D27/PTB[3]
D26/PTB[2]
D25/PTB[1]
D24/PTB[0]
VssQ
D23/PTA[7]
VccQ
D22/PTA[6]
D21/PTA[5]
D20/PTA[4]
Vss
D19/PTA[3]
Vcc
D18/PTA[2]
D17/PTA[1]
D16/PTA[0]
D15
VssQ
D14
VccQ
D13
D12
D11
D10
D9
D8
D7
D6
VssQ
D5
VccQ
D4
D3
D2
D1
D0
A0
A1
A2
VssQ
A3
VccQ
A4
A5
A6
A7
A8
A9
A10
A11
VssQ
A12
VccQ
A13
A14
A15
A16
A17
A18
A19
A20
VssQ
A21
VccQ
A22
A23
Vss
A24
Vcc
A25
BS_/PTK[4]
RD_
WE0_/DQMLL
WE1_/DQMLU/WE
WE2_/DQMUL/ICIORD_/PTK[6]
VssQ
WE3_/DQMUU/ICIOWR_/PTK{7}
VccQ
RD/WR_
PTE[7]/PCC0RDY/AUDSYNC_
/CS0
/CS2
/CS3
/CS4/PTK[2]
/CS5/CE1A_/PTK[3}
/CS6/CE1B_
CE2A_/PTE[4]
CE2B_/PTE[5]
AFE_HC1/USB1d_DPLS/PTK[0]
AFE_RLYCNT_/USB1d_DMNS/PTK[1]
VssQ
AFE_SCLK/USB1d_TXDPLS
VccQ
PTM[7]/PTINT[7]/AFE_FS/USB1d_RCV
PTM[6]/PTINT[6]/AFE_RXIN/USB1d_SPEED
PTM[5]/PTINT[5]/AFE_TXOUT/USB1d_TXSE0-
-
-
-
-
-
-
I
I
I
I
I
O
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
I/O
-
I/O
I/O
I/O
-
I/O
-
I/O
I/O
I/O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
O
-
O
O
O
-
O
-
O
O
-
-
-
O
O
O
O
O
O
O
-
I
-
I
I
IPower supply for RTC (1.9V)
Not in use (XTAL for internal RTC)
Power supply for RTC (0V)
Clock mode setting
Not in use (Non-maskable interrupt request)
External interrupt request
VEE control pin for LCD panel
VCC control pin for LCD panel
Big endian setting
Not in use (bus request)
Bus acknowledge
VssQ
System clock output
VccQ
Data bus
VssQ
Data bus
VccQ
Data bus
Vss
Data bus
Vcc
Data bus
VssQ
Data bus
VccQ
Data bus
VssQ
Data bus
VccQ
Data bus
Address bus
VssQ
Address bus
VccQ
Address bus
VssQ
Address bus
VccQ
Address bus
VssQ
Address bus
VccQ
Address bus
Vss
Address bus
Vcc
Address bus
Not connected (bus cycle start signal)
Read strobe
Write 0 signal
Write 1 signal
Write 2 signal
VssQ
Write 3 signal
VccQ
Read/Write
I/O
Chip Select 0
Chip Select 2
Chip Select 3
Chip Select 4
Chip Select 5
Chip Select 6
Output port (SWP50 Reset)
Output port (PLG Board Reset)
SPD  DATA
SPD  CL
VssQ
Not in use (USB1 D+ transmission)
VccQ
Not in usePIN
NO.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240PTM[4]/PINT[4]/AFE_RDET_/USB1d_TXDMNS
Reserved/USB1d_SUSPEND
USB1_ovr_crnt/USBF_VBUS
USB2_ovr_crnt_
RTS2_/USB1d_TXENL
PTE[2]/USB1_pwr_en
PTE[1]/USB2_pwr_en
CKE/PTK[5]
/RAS3/PTJ[0]
Reserved/PTJ[1]
Reserved//CAS/PTJ[2]
VssQ
Reserved/PTJ[3]
VccQ
Reserved/PTJ[4]
Reserved/PTJ[5]
Vss
PTD[5]/CL1
Vcc
PTD[7]/DON
PTE[6]/M_DISP
PTE[3]/FLM
PTE[0]/TDO
PCC0RESET/DRACK0
PCC0DRV_/DACK0_
/WAIT
/RESETM
/ADTRG/PTH[5]
/IOIS16/PTG[7]
/ASEMD0
PTG[5]/ASEBRKAK_
PTG[4]
PCC0BVD2/PTG[3]/AUDATA[3]
PCC0BVD1/PTG[2]/AUDATA[2]
Vss
PCC0CD2/PTG[1]/AUDATA[1]
Vcc
PCC0CD1/PTG[0]/AUDATA[0]
VssQ
PTF[7]/PINT[15]/TRST_
VccQ
PTF[6]/PINT[14]/TMS
PTF[5]/PINT[13]/TDI
PTF[4]/PINT[12]/TCK
PTF[3]/PINT[11]/Reserved
PCCREG_/PTF[2]/Reserved
PCC0VS1_/PTF[1]/Reserved
PCC0VS2_/PTF[0]/Reserved
MD0
Vcc-PLL1
CAP1
Vss-PLL1
Vss-PLL2
CAP2
Vcc-PLL2
PCC0WAIT_/PTH[6]/AUDCK
Vss
Vcc
XTAL
EXTAL
LCD15/PTM[3]/PINT[10]
LCD14/PTM[2]/PINT[9]
LCD13/PTM[1]/PINT[8]
LCD12/PTM[0]
STATUS0/PTJ[6]
STATUS1/PTJ[7]
CL2/PTH[7]
VssQ
CKIO
VccQ
TxD0/SCPT[0]
SCK0/SCPT[1]
TxD_SIO/SCPT[2]
SIOMCLK/SCPT[3]
TxD2/SCPT[4]
SCK_SIO/SCPT[5]
SIOFSYNC/SCPT[6]
RxD0/SCPT[0]
RxD_SIO/SCPT[2]
Vss
RxD2/SCPT[4]
Vcc
SCPT[7]/CTS2_/IRQ5
LCD11/PTC[7]/PINT[3]
LCD10/PTC[6]/PINT[2]
LCD9/PTC[5]/PINT[1]
VssQ
LCD8/PTC[4]/PINT[0]
VccQ
LCD7/PTD[3]
LCD6/PTD[2]
LCD5/PTC[3]
LCD4/PTC[2]
LCD3/PTC[1]
LCD2/PTC[0]
LCD1/PTD[1]
LCD0/PTD[0]
DREQ0_/PTD[4]
LCK/UCLK/PTD[6]
/RESETP
CA
MD3
MD4
/Scan_testen
Avcc_USB
USB1_P
USB1_M
Avss_USB
USB2_P
USB2_M
Avcc_USB
Avss
AN[2]/PTL[2]
AN[3]/PTL[3]
AN[4]/PTL[4]
AN[5]/PTL[5]
Avcc
AN[6]/PTL[6]/DA[1]
AN[7]/PTL[7]/DA[0]
AvssI
O
I
-
O
O
O
O
O
O
O
-
O
-
O
O
-
O
-
O
O
O
O
O
O
-
-
I
I
-
I
I
I
-
I
-
I
-
I
-
I
I
I
I
I
I
I
-
-
-
-
-
-
-
I
-
-
-
-
I
I
I
I
O
O
O
-
-
-
O
O
O
O
O
O
O
i
i
-
i
-
I
O
O
O
-
O
-
O
O
O
O
O
O
O
O
I
I
-
-
-
-
-
-
IO
IO
-
IO
IO
-
-
I
I
I
I
-
I
O
-Not in use
USB function VBUS
USB2_HOST2 over current detection
Not in use
USB1 voltage control
USB2 voltage control
Enable (SDRAM)
RAS for SDRAM
Not in use
CAS for SDRAM
VssQ
Output port (DAC Reset)
VccQ
Output port (SIO Reset)
Output port (DAC Mute)
Vss
LCD line clock
Vcc
LCD DISPLAY ON
LCD alternater
LCD frame line marker
JTAG (test data output)
DMA request acceptance
DMA acknowledge
Hardware wait request
Manual reset request
Analog A/D  trigger
Not in use
Vss
Not in use
Vcc
Not in use
VssQ
Not in use
VccQ
Not in use
Clock mode setting
Power supply for Vcc_PLL1 - PLL1(1.9V)
External capacitance for CAP1 _ PLL1
Power supply for Vss_PLL1 _ PLL1(0V)
Power supply for Vss_PLL2 _ PLL2 (0V)
External capacitance for CAP2 _ PLL2
Power supply for Vcc_PLL2 _ PLL2 (1.9V)
Not in use
Vss
Vcc
Clock oscillator
External clock
Not in use
Input port (Flash ROM RY/BY)
Output port (Flash ROM write protect)
Output port (Flash ROM ACC)
LCD clock output
VssQ
System clock input/output (for SDRAM)
VccQ
Output port for SCI
Not in use
Output port for SCI
Not in use
Receiving data 0
Not in use
Vss
Receiving data 2
Vcc
Not in use
Output port (PLG CLOCK  ON/OFF)
Not in use
VssQ
Not in use
VccQ
LCD DATA7
LCD DATA6
LCD DATA5
LCD DATA4
LCD DATA3
LCD DATA2
LCD DATA1
LCD DATA0
DMA request
USB clock
Power on reset request
Hardware standby request
Bus width setting for area0
Test pin (fixed to 3.3V)
USB analog power supply (3.3V)
USB1 data input/output (+)
USB1 data input/output (-)
USB analog power supply (0V)
USB2 data input/output (+)
USB2 data input/output (-)
USB analog power supply (3.3V)
A/D analog power supply (0V)
AD converter input
A/D analog power supply (3.3V)
AD converter input
DA converter output (LCD contrast)
A/D analog power supply (0V) I/OI/O
NAME FUNCTIONFUNCTION NAME
HD6417727F160CV (X2890B00) CPUDM: IC3 
						

							Tyros3
32
PIN
NO.I/O FUNCTION NAMEPIN
NO.I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52RD
PA 8  /
RD/WR
PVss
PC1 /
A1
A2
A3
A4
A5
A6
A7
A8
A9
Vcc
Vss
PVss
PVcc
A10
A11
A12
A13
A14
A15
A16
Vcc
Vss
A17
A18
A19
A20
PA18 /
BREQ /
TEND0 /
PINT2
PVcc
CKIO
PVss
PLLVss
PLLVcc
PVcc
RES
PVss
XTAL
EXTAL
PVss
PVcc
NMI
PVss
PVss
PB9 /
A21 /
IRQ7 / ADTRG /POE8
PA5 / SCK1 /
DREQ1 / IRQ1 /A22
PA 4  /
TxD1 / A23
PA 3  /
RxD1 /
A24
PA2 / SCK0 / 
DREQ0 / IRQ0 / 
A25
PC0 /
A0
PE16 /
CS8O
I/O
O
I
I
O
O
O
O
O
O
O
O
O
I
I
I
I
O
O
O
O
O
O
O
I
I
O
O
O
O
I/O
I
O
I
I
I/O
I
I
I
I
I
I
O
I
I
I
I
I
I
I/O
O
I
I
I/O
I
O
I/O
O
I/O
I
O
I/O
I
O
I/O
O
I/O
ORead
General port /
Read/write signal
Ground for I/O circuits
General port /
Address bus
Address bus
Power supply
Ground
Ground for I/O circuits
Power supply for I/O circuits
Address bus
Power supply
Ground
Address bus
General port /
Bus-mastership request /
DMA-transfer end output /
Interrupt requests 2
Power supply for I/O circuits
System clock I/O
Ground for I/O circuits
Ground for PLL
Power supply for PLL
Power supply for I/O circuits
Power-on reset
Ground for I/O circuits
Crystal
External clock
Ground for I/O circuits
Power supply for I/O circuits
Non-maskable interrupt
Ground for I/O circuits
General port /
Address bus /
Interrupt requests 7 / A/D conversion trigger input
/ Port output control
General port / Serial clock /DMA-transfer request / Interrupt requests 1 /Address bus
General port /
Transmit data / Address bus
General port /
Receive data /
Address bus
General port / Serial clock /
DMA-transfer request / Interrupt requests 0 /Address bus
General port /
Address bus
General port /
Chip select 8
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83PE15 /
TIOC4D /
DACK1 /
IRQOUT / CKE
MD_CLK2
MD_CLK0
Vss
Vcc
MD2
MD0
PA 9  /
TCLKD /IRQ3 /
FRAME / CKE
PE9 / TIOC3B /SCK3/RTS3
PA17 /
WAIT /
DACK2
PVcc
PVss
PVss
PE13 /
TIOC4B /
MRES
CS0
PA 11  /
CS1 /
POE5
PE8 /
TIOC3A /
SCK2
PA24 /
CE2A /
DREQ3 / PINT6
PA25 /
CE2B /
DACK3 /
PINT7 / POE8
PB3 / IRQ1 / POE1 /SDA
PB2 / IRQ0 /
POE0 /
SCL
PE7 /
TIOC2B /
RxD2 /
BS / UBCTRG
PE0 /
TIOC0A /
DREQ0 /
AUDCK
PVcc
PVss
Vss
Vcc
PE3 /
TIOC0D /
TEND1 / AUDATA3PA 1  /
TxD0 /
PINT1 /
CS5/CE1A
PE5 /
TIOC1B /
TxD3 / AUDATA1 /CS6/CE1B
PE1 /
TIOC0B /
TEND0I/O
I/O
O
O
I
I
I
I
I
I
I/O
I
O
I/O
I/O
O
I/O
I
O
I
I
I
I/O
I/O
I
O
I/O
O
I
I/O
I/O
I/O
I/O
O
I
I/O
O
O
I
I
I/O
I
I
I/O
I/O
I/O
I
O
I/O
I/O
I
O
I
I
I
I
I/O
I/O
O
I/O
O
I
O
I/O
I/O
O
O
I/O
I/O
OGeneral port /
MTU2 input capture/output compare (channel 4) /DMA-transfer request accept /
Interrupt request output / CK enable
Clock mode set
Ground
Power supply
Mode set
General port /
MTU2 timer clock input / Interrupt requests 3 /FRAME signal / CK enableGeneral port / MTU2 input capture/output 
compare (channel 3) / Serial clock /
Transmit request
General port /
Wait /
DMA-transfer request accept
Power supply for I/O circuits
Ground for I/O circuits
General port /
MTU2 input capture/output compare (channel 4) /Manual reset
Chip select 0
General port /
Chip select 1 /
Port output control
General port /
MTU2 input capture/output compare (channel 3) /Serial clock
General port /
Upper byte select for PCMCIA card /
DMA-transfer request / Interrupt requests 6General port /
Upper byte select for PCMCIA card /
DMA-transfer request accept /
Interrupt requests 7 / Port output controlGeneral port / Interrupt requests1 / Port output control /Serial data pin
General port / Interrupt requests 0 /
Port output control /
Serial clock pin
General port /
MTU2 input capture/output compare (channel 2) /Receive data /
Bus start / User break trigger output
General port /
MTU2 input capture/output compare (channel 0) /DMA-transfer request /
AUD clock
Power supply for I/O circuits
Ground for I/O circuits
Ground
Power supply
General port /
MTU2 input capture/output compare (channel 0) /DMA-transfer end output / AUD data
General port /
Transmit data /
Interrupt requests 1 /
Chip select 5/Lower byte select for PCMCIA cardGeneral port /MTU2 input capture/output compare (channel 1) /Transmit data / AUD dataChip select 6/Lower byte select for PCMCIA cardGeneral port /MTU2 input capture/output compare (channel 0) /DMA-transfer end output
R5S72060W200FPV(X8924A00) CPUDM: IC507 
						

							33 Tyros3
PIN
NO.I/O FUNCTION NAMEPIN
NO.I/O FUNCTION NAME
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
11 0
111
11 2
11 3
11 4
11 5
11 6
11 7
11 8
11 9
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134PE6 / SCK3 /
TIOC2A /
AUDATA0 / CS7PA 0  /
RxD0 / PINT0 /
CS4
PE4
PE2 /
TIOC0C /
DREQ1
PE14
AVss
PF0 / AN0
PF1 / AN1
PF2 / AN2
PF3 / AN3
PF4 / AN4
PF5 / AN5
PF6 / AN6 /
DA0
PF7 / AN7 /
DA1
AVref
AVcc
PE10 /
TIOC3C /
TxD2
Vcc
Vss
PE11 /
TIOC3D /
RxD3 / CTS3
ASEBRKAK/ASEBRKPE12 /
TIOC4A /
TxD3
WDTOVF
ASEBCK
PVcc
PA19 /
BACK /
TEND1 /
PINT3
TCK
TRST
TDI
PVss
Vss
Vcc
TMS
PVcc
PVss
ASEMD
TDO
PD31 / D31
PD30 / D30
PD29 / D29
PD28 / D28
PVcc
PVss
PD27 / D27
PD26 / D26
PD25 / D25
PD24 / D24
PVcc
PD23 / D23
PVss
PD22 / D22I/O
I/O
O
I/O
I
O
I/O
I/O
I/O
I
I/O
I
I
I
I
I
I
I
I
O
I
O
I
I
I/O
I/O
O
I
I
I/O
I/O
I
I/O
I/O
I/O
O
O
O
I
I/O
O
O
I
I
I
I
I
I
I
I
I
I
I
O
I/O
I/O
I/O
I/O
I
I
I/O
I/O
I/O
I/O
I
I/O
I
I/OGeneral port / Serial clock /
MTU2 input capture/output compare (channel 2) /AUD data / Chip select 7
General port /
Receive data / Interrupt requests 0 /
Chip select 4
General port
General port /
MTU2 input capture/output compare (channel 0) /
DMA-transfer request
General port
Analog ground
General port / Analog input pins
General port / Analog input pins /
Analog output pins
General port / Analog input pins /
Analog output pins
Analog reference voltage
Analog power supply
General port /
MTU2 input capture/output compare (channel 3) /
Transmit data
Power supply
Ground
General port
MTU2 input capture/output compare (channel 3) /
Receive data / Transmit enable
Break mode acknowledge/Break requestGeneral port /MTU2 input capture/output compare (channel 4) /
Transmit data
Watchdog timer overflow
ASECK output
Power supply for I/O circuits
General port /
Bus-mastership request acknowledge /
DMA-transfer end output /
Interrupt requests 3
Test clock
Test reset
Test data input
Ground for I/O circuits
Ground
Power supply
Test mode select
Power supply for I/O circuits
Ground for I/O circuits
Debugging mode
Test data output
General port / Data bus
Power supply for I/O circuits
Ground for I/O circuits
General port / Data bus
Power supply for I/O circuits
General port / Data bus
Ground for I/O circuits
General port / Data bus
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176PD21 / D21
PD20 / D20
PD19 / D19
PD18 / D18
PD17 / D17
PD16 / D16
PD15 / D15
PD14 / D14
PD13 / D13
Vss
Vcc
PD12 / D12
PVss
PD11 / D11
PVcc
PD10 / D10
PD9 / D9
PD8 / D8
D7
D6
D5
D4
D3
Vss
Vcc
D2
D1
PVss
PVcc
D0
PA21 /
CS5/CE1A /
CASU /
TIC5U /
PINT5
PB5 /
IRQ3 / POE3 /
CASL
PA16 /
WE3/DQMUU/AH/ICIOWR/
DREQ2 /
AUDSYNC / CKEPA 6  /
TCLKA /
CS2 /
PA 7  /
TCLKB /
CS3 /
PA23 /
WE3/DQMUU/AH/ICIOWR/
TIC5W
PA22 /
WE2/DQMUL/ICIORD/
TIC5V
PA13 /
WE1/DQMLU/WE/
POE7
PA12 /
WE0/DQMLL /
POE6
PB4 /
IRQ2 /
POE2 /
RASL
PA20 /
CS4 / RASU /
PINT4
PVccI/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I/O
I
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I/O
I/O
I
I
I/O
I/O
O
O
I
I
I/O
I
O
I/O
O
I
O
I/O
I
O
I/O
I
O
I/O
O
I
I/O
O
I
I/O
O
I
I/O
O
I
I/O
I
I
O
I/O
O
I
IGeneral port / Data bus
Ground
Power supply
General port / Data bus
Ground for I/O circuits
General port / Data bus
Power supply for I/O circuits
General port / Data bus
Data bus
Ground
Power supply
Data bus
Ground for I/O circuits
Power supply for I/O circuits
Data bus
General port /
Chip select 5/Lower byte select for PCMCIA card /
CAS /
MTU2 input capture (channel 5) /
Interrupt requests 5
General port /
Interrupt requests 3/ Port output control /
CAS
General port /
Byte select/Byte select/Address hold/Write strobe for PCMCIA I/O /
DMA-transfer request /
AUD sync signal / CK enable
General port /
MTU2 timer clock input /
Chip select 2
General port /
MTU2 timer clock input /
Chip select 3
General port /
Byte select/Byte select/Address hold/Write strobe for PCMCIA I/O /
MTU2 input capture (channel 5)
General port /
Byte select/Byte select/Read strobe for PCMCIA I/O /
MTU2 input capture (channel 5)
General port /
Byte select/Byte select/Write strobe for PCMCIA memory /
Port output control
General port /
Byte select/Byte select /
Port output control
General port /
Interrupt requests 2 /
Port output control /
RAS
General port /
Chip select 4 / RAS /
Interrupt requests 4
Power supply for I/O circuits 
						

							Tyros3
34
PIN
NO.I/O
FUNCTION NAMEPIN
NO.I/O
FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
OUTER
NO.
E5
D4
C3
B2
A1
D5
E6
C4
B3
A2
A3
D6
E7
C5
B4
A4
D7
C6
E8
D8
B5
A5
C7
B6
E9
D9
C8
A6
B7
A7
E10
D10
C9
B8
A8
B9
E11
D11
C10
A9
B10
A10
E12
D12
C11
B11
A11
C12
B12
E13
D13
C13
A12
B13
A13
A14
E14
D14
C14
B14
B15
C15
D15
E15
A15
A16
B16
C16
D16
E16
A17
B17
A18
C17
D17
E17
B18
A19
C18
B19
D18
E18
C19
A20
B20
C20
D19
E19
A21
B21
A22
D20
C21
E20
D21
B22
A23
C22
B23
E21
D22
C23
A24
B24
A25VSS
VDD1
CD15
CD13
CD14
CD6
CD2
CD9
CD11
CD12
CD10
CD1
VSS
CD5
CD8
CD7
VSS
CD0
VSS
VDD3
CD4
CD3
CA2
CA0
CA8
CA9
CA5
CA1
CA3
CA4
VSS
VDD1
CA10
CA6
CA7
CA11
CA14
CA15
CA13
CA12
CSN0
CSN1
VSS
VDD3
WRN
RDN
WAITo
IRQo
DREQo
TCK
TRST
VSS
XO
XI
VDD3
SLAVE
TMS
TDO
ICN
RFCLKo
PLL_
TSTN
PLL_
BP
VDD3
VSS
RFCLKi
VDD1
TMODE
PLL_
AV D
NC
NC
PLL_
AV S
TEST1
VSS
SYI
VDD1
VSS
KONTRGo
KONTRGi
CK512
CK128
BCLK
SYO
HMA20
HMA21
HMA19
HMA18
VDD3
VSS
HMA9
HMA7
HMA6
HMA8
HMA10
HMA17
VDD3
HMA11
HMA4
HMA5
HMA13
VSS
HMA12
HMA3
HMA14
HMA2
HMA1-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
I/O
I/O
I/O
-
I/O
-
-
I/O
I/O
I
I
I
I
I
I
I
I
-
-
I
I
I
I
I
I
I
I
I
I
-
-
I
I
O
O
O
I
I
-
O
I
-
I
I
O
I
O
I
I
-
-
I
-
I
-
-
-
-
I
-
I
-
-
O
I
O
O
O
O
O
O
O
O
-
-
O
O
O
O
O
O
-
O
O
O
O
-
O
O
O
O
OGround
Power supply +1.5 V
Data bus of internal register
Ground
Data bus of internal register
Ground
Data bus of internal register
Ground
Power supply +3.3 V
Data bus of internal register
Address bus of internal regisuter
Ground
Power supply +1.5 V
Address bus of internal regisuter
Chip select
Ground
Power supply +3.3 V
Write strobe
Read strobe
Hardware wait request
Interrupt request
DMA request
Test pin
Ground
Crystal osc. output
Crystal osc. input
Power supply +3.3 V
Master/Slave select
Test pin
Initial clear
PLL Clock
Test pin
Power supply +3.3 V
Ground
PLL Clock
Power supply +1.5 V
Test pin
Analog power supply +1.5 V (PLL)
Not used
Not used
Analog ground (PLL)
Test pin
Ground
Sync. clock
Power supply +1.5 V
Ground
Key on data
Master clock (512 Fs)
Master clock (256 Fs)
Master clock (64 Fs)
Sync. clock
Wave memory address bus
Power supply +3.3 V
Ground
Wave memory address bus
Power supply +3.3 V
Wave memory address bus
Ground
Wave memory address bus106
107
108
109
11 0
111
11 2
11 3
11 4
11 5
11 6
11 7
11 8
11 9
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
OUTER
NO.
E22
D23
C24
B25
A26
E23
F22
D24
C25
B26
C26
F23
G22
E24
D25
D26
G23
F24
H22
H23
E25
E26
G24
F25
J22
J23
H24
F26
G25
G26
K22
K23
J24
H25
H26
J25
L22
L23
K24
J26
K25
K26
M22
M23
L24
L25
L26
M24
M25
N22
N23
N24
M26
N25
N26
P26
P22
P23
P24
P25
R25
R24
R23
R22
R26
T26
T25
T24
T23
T22
U26
U25
V26
U24
U23
U22
V25
W26
V24
W25
V23
V22
W24
Y26
Y25
Y24
W23
W22
AA26
AA25
AB26
Y23AA24Y22AA23
AB25
AC26
AB24
AC25
AA22
AB23
AC24
AD26
AD25
AE26
VSS
VDD1
HMA15
HMA16
HMA22
HMA25
VDD3
HMA27
HMA0
HMA23
HMA24
VDD3
HMA26
HMA30
HMA28
HMA29
LMA17
LMA19
VSS
VDD3
LMA20
LMA21
LMA9
LMA18
LMA12
LMA4
LMA6
LMA8
LMA7
LMA10
VSS
VDD1
LMA13
LMA11
LMA5
LMA3
LMA16
LMA0
LMA2
LMA14
LMA15
LMA1
VSS
VDD3
LMA22
LMA23
LMA24
LMA27
LMA28
LMA25
LMA26
LMA30
LMA29
MOEN
MWEN
LMD15
VSS
VDD3
LMD13
LMD14
LMD11
LMD10
VDD3
VSS
LMD12
LMD9
LMD8
LMD7
VSS
VSS
LMD6
LMD5
LMD3
LMD4
VDD1
VSS
LMD2
LMD0
LMD1
DCSL0
VDD3
VDD1
DCSL1
DQML3
DQML1
DMAL14
VDD3
VSS
DMAL13
DMAL12
DMAL9
VSS
DMAL11
VSS
DMAL10
DMAL8
DMAL6
DMAL7
DMAL5
VSS
VSS
DMAL4
DMAL3
DMAL2
DMAL0-
-
O
O
O
O
-
O
O
O
O
-
O
O
O
O
O
O
-
-
O
O
O
O
O
O
O
O
O
O
-
-
O
O
O
O
O
O
O
O
O
O
-
-
O
O
O
O
O
O
O
O
O
O
O
I/O
-
-
I/O
I/O
I/O
I/O
-
-
I/O
I/O
I/O
I/O
-
-
I/O
I/O
I/O
I/O
-
-
I/O
I/O
I/O
O
-
-
O
O
O
O
-
-
O
O
O
-
O
-
O
O
O
O
O
-
-
O
O
O
OGround
Power supply +1.5 V
Wave memory address bus
Power supply +3.3 V
Wave memory address bus
Power supply +3.3 V
Wave memory address bus
Wave memory address bus (Lower data memory)
Ground
Power supply +3.3 V
Wave memory address bus (Lower data memory)
Ground
Power supply +1.5 V
Wave memory address bus (Lower data memory)
Ground
Power supply +3.3 V
Wave memory address bus (Lower data memory)
Wave memory output enable
Wave memory write enable
Wave memory data bus (Lower 16 bit)
Ground
Power supply +3.3 V
Wave memory data bus (Lower 16 bit)
Power supply +3.3 V
Ground
Wave memory data bus (Lower 16 bit)
Ground
Ground
Wave memory data bus (Lower 16 bit)
Power supply +1.5 V
Ground
Wave memory data bus (Lower 16 bit)
Wave memory chip select (Low)
Power supply +3.3 V
Power supply +1.5 V
Wave memory chip select (Low)
MASK signal
Address bus (DIMM, SDRAM)
Power supply +3.3 V
Ground
Address bus (DIMM, SDRAM)
Ground
Address bus (DIMM, SDRAM)
Ground
Address bus (DIMM, SDRAM)
Ground
Ground
Address bus (DIMM, SDRAM)
T6TZ2XBG-0002 (X7376B00) SWP51 (Tone Generator)DM: IC505, 506 
						

							35 Tyros3
PIN
NO.I/O
FUNCTION NAMEPIN
NO.I/O
FUNCTION NAME
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315VSS
VDD1
DMAL1
DCSL2
DRAS0
DCAS0
VDD3
DCLKIN
DQML2
DCSL3
DQML0
VDD3
VSS
DWEN0
DCLK0
DCLK1
DCLKE
HMD13
VSS
VDD3
HMD15
HMD14
HMD10
HMD12
VDD1
VDD3
HMD7
HMD11
HMD9
HMD8
VSS
VDD1
HMD4
HMD6
HMD5
HMD3
VSS
VSS
HMD1
HMD2
HMD0
DCSH0
VSS
VDD3
DCSH1
DQMH3
DQMH1
DMAH14
DMAH13
VSS
VSS
DMAH11
DMAH12
DMAH10
DMAH9
DMAH8
VDD3
VDD3
DMAH6
DMAH7
DMAH4
DMAH3
VDD3
VSS
DMAH5
DMAH2
DMAH1
DMAH0
VSS
VSS
DRAS1
DCSH2
DQMH2
DCSH3
VDD1
VSS
DQMH0
DWEN1
DCAS1
DCLK2
VDD3
VDD1
DCLK3
MELO0
MELO1
MELO2
VDD3
VSS
MELO3
MELO4
MELO5
MELO6
MELO7
WCLK0
WCLK1
EIRQ
EICN
ESDA
ESCL
MELI0
MELI1
MELI2
MELI3
MELI4
MELI5-
-
O
O
O
O
-
I
O
O
O
-
-
O
O
O
O
I/O
-
-
I/O
I/O
I/O
I/O
-
-
I/O
I/O
I/O
I/O
-
-
I/O
I/O
I/O
I/O
-
-
I/O
I/O
I/O
O
-
-
O
O
O
O
O
-
-
O
O
O
O
O
-
-
O
O
O
O
-
-
O
O
O
O
-
-
O
O
O
O
-
-
O
O
O
O
-
-
O
O
O
O
-
-
O
O
O
O
O
O
O
O
O
I/O
I/O
I
I
I
I
I
IGround
Power supply +1.5 V
Address bus (DIMM, SDRAM)
Wave memory chip select (Low)
DIMM, SDRAM row address strobe (RAS signal)
DIMM, SDRAM column address strobe (CAS signal)Power supply +3.3 V
DIMM, SDRAM clock input
MASK signal
Wave memory chip select (Low)
MASK signal
Power supply +3.3 V
Ground
DIMM, SDRAM write enable
DIMM, SDRAM clock signal
DIMM, SDRAM clock enable
Wave memory data bus (Upper data memory)
Ground
Power supply +3.3 V
Wave memory data bus (Upper data memory)
Power supply +1.5 V
Power supply +3.3 V
Wave memory data bus (Upper data memory)
Ground
Power supply +1.5 V
Wave memory data bus (Upper data memory)
Ground
Ground
Wave memory data bus (Upper data memory)
Wave memory chip select (High)
Ground
Power supply +3.3 V
Wave memory chip select (High)
MASK signal
Address bus (DIMM, SDRAM)
Ground
Ground
Address bus (DIMM, SDRAM)
Power supply +3.3 V
Power supply +3.3 V
Address bus (DIMM, SDRAM)
Power supply +3.3 V
Ground
Address bus (DIMM, SDRAM)
Ground
Ground
DIMM, SDRAM row address strobe (RAS signal)
Wave memory chip select (High)
MASK signal
Wave memory chip select (High)
Power supply +1.5 V
Ground
MASK signal
DIMM, SDRAM write enable
DIMM, SDRAM column address strobe (CAS signal)DIMM, SDRAM clock signal
Power supply +3.3 V
Power supply +1.5 V
DIMM, SDRAM clock signal
MEL wave data output
Power supply +3.3 V
Ground
MEL wave data output
For DAC word clock
E bus interrupt request
E bus initial clear
E bus data
E bus clock
MEL wave data input316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
OUTER
NO.OUTER
NO.
AB22
AC23
AD24
AE25
AF26
AC22
AB21
AD23
AE24
AF25
AF24
AC21
AB20
AD22
AE23
AF23
AC20
AD21
AB19
AC19
AE22
AF22
AD20
AE21
AB18
AC18
AD19
AF21
AE20
AF20
AB17
AC17
AD18
AE19
AF19
AE18
AB16
AC16
AD17
AF18
AE17
AF17
AB15
AC15
AD16
AE16
AF16
AD15
AE15
AB14
AC14
AD14
AF15
AE14
AF14
AF13
AB13
AC13
AD13
AE13
AE12
AD12
AC12
AB12
AF12
AF11
AE11
AD11
AC11
AB11
AF10
AE10
AF9AD10
AC10
AB10
AE9
AF8
AD9
AE8
AC9
AB9
AD8
AF7
AE7
AD7
AC8
AB8
AF6
AE6
AF5
AC7
AD6
AB7
AC6
AE5
AF4
AD5
AE4
AB6
AC5
AD4
AF3
AE3
AF2AB5
AC4
AD3
AE2
AF1
AB4
AA5
AC3
AD2
AE1
AD1
AA4
Y5
AB3
AC2
AC1
Y4
AA3
W5
W4
AB2
AB1
Y3
AA2
V5
V4
W3
AA1
Y2
Y1
U5
U4
V3
W2
W1
V2
T5
T4
U3
V1
U2
U1
R5
R4
T3
T2
T1
R3
R2
P5
P4
P3
R1
P2
P1
N1
N5
N4
N3
N2
M2
M3
M4
M5
M1
L1
L2
L3
L4
L5
K1
K2
J1
K3
K4
K5
J2
H1
J3
H2
J4
J5
H3
G1
G2
G3
H4
H5
F1
F2
E1
G4
F3
G5
F4
E2
D1
E3
D2
F5
E4
D3
C1
C2
B1VSS
VDD1
MELI6
MELI7
ADLR
DITo
VSS
AFRM
ACLK
ADIR
ADAT0
VDD3
ADAT9
ADAT3
ADAT1
ADAT2
ADAT10
ADAT6
VSS
VDD3
ADAT4
ADAT5
ADAT11
ADAT7
ADAT14
ADAT15
ADAT13
ADAT8
ADAT12
TDI
VSS
VDD1
HRD13
HRD15
HRD14
HRD12
HRD7
HRD6
HRD10
HRD11
HRD9
HRD8
VSS
VDD3
HRD5
HRD4
HRD3
HRD2
HRD1
VDD3
HRD0
RWEN
RQML
RCAS
RRAS
RA13
VDD3
VDD3
RA10
RA12
RA1
RA2
VDD3
VSS
RA0
RA3
RA4
RA5
VSS
VSS
RA6
RA7
RA9
RA8
VDD1
VSS
RA11
RCLK
RCLKE
RCLKIN
VDD3
VDD1
RQMH
LRD15
LRD14
LRD13
VDD3
VSS
LRD12
LRD11
LRD8
VDD3
LRD10
VDD3
LRD9
LRD7
LRD5
LRD6
LRD4
VSS
VSS
LRD3
LRD2
LRD1
LRD0-
-
I
I
O
O
-
I/O
I/O
O
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
I/O
I/O
I/O
I/O
I/O
-
I/O
O
O
O
O
O
-
-
O
O
O
O
-
-
O
O
O
O
-
-
O
O
O
O
-
-
O
O
O
I
-
-
O
I/O
I/O
I/O
-
-
I/O
I/O
I/O
-
I/O
-
I/O
I/O
I/O
I/O
I/O
-
-
I/O
I/O
I/O
I/OGround
Power supply +1.5 V
MEL wave data input
For ADC word clock
Digital audio output
Ground
Frame signal (ABUS)
Clock signal (ABUS)
Direction signal (ABUS)
Data bus (ABUS)
Power supply +3.3 V
Data bus (ABUS)
Ground
Power supply +3.3 V
Data bus (ABUS)
Test pin
Ground
Power supply +1.5 V
DRAM data bus
Ground
Power supply +3.3 V
DRAM data bus
Power supply +3.3 V
DRAM data bus
DRAM write enable
MASK signal (SDRAM)
DRAM column address strobe (CAS signal)
DRAM row address strobe (RAS signal)
DRAM address bus
Power supply +3.3 V
Power supply +3.3 V
DRAM address bus
Power supply +3.3 V
Ground
DRAM address bus
Ground
Ground
DRAM address bus
Power supply +1.5 V
Ground
DRAM address bus
SDRAM clock signal
SDRAM clock enable
SDRAM, DRAM clock input
Power supply +3.3 V
Power supply +1.5 V
MASK signal (SDRAM)
DRAM data bus (Lower data)
Power supply +3.3 V
Ground
DRAM data bus (Lower data)
Power supply +3.3 V
DRAM data bus (Lower data)
Power supply +3.3 V
DRAM data bus (Lower data)
Ground
Ground
DRAM data bus (Lower data) 
						

							Tyros3
36
Pin No. NAME I/O FUNCTION/CONNECTIONPin No. NAMEI/O
FUNCTION/CONNECTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50GND
TDI
DGA_AUDIO_INI/O
DGA_OUT
I/O
GND
I/O
IDERD_O
IDEWR_O
IDEMACK_O
CLOCK_INPUTVCCO
DMACLR
I/O
I/O
I/O
GND
HDIRQ
XHDIRQ
I/O
I/O
FS64DGA
TCK
VCC
GND
I
I/O
I/O
I/O
I/O
GND
VCCO
I/O
I/O
I/O
I/O
CK512
FS128
I/O
I/O
I/O
I/O
I/O
VCCO
GND
I/O
I/O
I/O
I/O
-
I
O
I
-
I
I
I
I
-
I
-
I
O
I
I
-
-
-
I
I
-
-DGND
for CPLD data writing    (JTAG pin)
Digital audio signal output
   (to +3.3V
D)
Digital audio signal input
   (to +3.3V
D)
DGND
   (to +3.3V
D)
IDE READ signal  (active-low)
IDE WRITE signal  (active-low)
DMA ACKNOWLEDGE signal  (active-low)DMA REQUEST signal  (active-low)Power supply +3.3VDDMA CLEAR signal  (active-low)
(to +3.3VD)
DGNDINTERRUPT signal (HDD to CPU) (active-high)INTERRUPT signal (HDD to CPU) (active-low)
(to +3.3VD)
Bit clock for data between DGA and MATClock for CPLD data communication (JTAG pin)Power supply +3.3VDDGND
DGND
Power supply +3.3V
D
(to +3.3VD)
Master clock (22.5792KHz)Bit clock for data between SWP50 and MAT (11.2894MHz)
(to +3.3VD)
Power supply +3.3VDDGND
(to +3.3VD)51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100GND
TMS
MELO_0
I/O
MELO_2
MELI_0
GND
I/O
I/O
I/O
I/O
I
VCCO
I/O
I/O
I/O
DGAMCLK
GND
DGAWCLK
I/O
I
DEMARQ512DDMAERR
I
TDD
VCCO
GND
I
I/O
WCLK1
I/O
WCLK0
GND
VCCO
ADLR
I/O
FS640UT
I/O/GOE1
FS
FS256
VCCO
I/O/GOE0
I/O
I/O
I/O
VCCO
GND
I/O
I/O
I/O
IDMARQ_0512HDL
-
O
O
I
-
-
O
-
O
O
O
I
O
-
O
O
-
-
O
O
I
I
-
-
-
ODGNDfor CPLD data communication (JTAG pin)Data for PLAYBACK tracks1 and 2   (to +3.3VD)Data for PLAYBACK tracks 3 and 4Data for RECORD tracks 1 and 2
DGND
    (to +3.3V
D)
Power supply +3.3VD
    (to +3.3VD)
System master clock (22.5792MHz)DGND
System word clock (44.1kHz)
   (to +3.3V
D)IDE DMA request
   (Not used)
   (to DGND)
for CPLD data communication
Power supply +3.3V
DDGND
   (to +3.3VD)   (to DGND)
Word clock for DAC (Not used)
   (to DGND)
Word clock for DAC (Not used)
DGND
Power supply +3.3V
DLR signal for DAC (Not used)
   (to DGND)
Maste clock for DAC (Not used)
   (to DGND)
Sampling frequency (44.1kHz)
256FS (11.2896MHz)
Powe supply +3.3V
D
    (to +3.3VD)
Powe supply +3.3VDGround
    (to +3.3V
D)
Output  in case that the DMA request
signal is negated by the rising or falling
edge of 512FS. (Not used.)
LC4256V-75TN100 (X6046B0R) CPLD (MAT)DM: IC205
(to +3.3VD) 
						

							37 Tyros3
PIN
NO.I/O FUNCTION NAMEPIN
NO.I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88A23
A22
A21
A20
V
DDA19
VSSA18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
V
DDVSSA7
A6
A5
A4
A3
A2
A1
WRH_N
WRL_N
RD_N
RESET_N
V
SSCS_N
VDDDREQ_N
INT_N
READY_N
WAIT_N
D15
D14
D13
D12
V
SSD11
D10
V
DDD9
D8
D7
D6
D5
D4
V
SSD3
D2
D1
D0
V
DDSDQ0
SDQ15
V
SSSDQ1
SDQ14
SDQ2
SDQ13
SDQ3
V
SSSDQ12
VDDSDQ4
SDQ11
SDQ5
SDQ10
V
SSSDQ6
SDQ9
SDQ7
SDQ8
V
DDLDQM
VSSWE_N
UDQM
CAS_N
SDCKOUT
RAS_N
V
SSSCS_NI
I
I
I
-
I
-
I
I
I
I
I
I
I
I
I
I
I
-
-
I
I
I
I
I
I
I
I
I
I
I
-
I
-
O
O
O
O
I/O
I/O
I/O
I/O
-
I/O
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O
-
I/O
I/O
I/O
I/O
-
I/O
I/O
-
I/O
I/O
I/O
I/O
I/O
-
I/O
-
I/O
I/O
I/O
I/O
-
I/O
I/O
I/O
I/O
-
O
-
O
O
O
O
O
-
OCPU address bus
Digital power supply +3.3 V
CPU address bus
Digital ground
CPU address bus
Digital power supply +3.3 V
Digital ground
CPU address bus
Write strobe input
Read pulse input
Reset input
Digital ground
Chip select
Digital power supply +3.3 V
Direct memory access
Interrupt
CPU bus ready
CPU bus wait
CPU data bus
Digital ground
CPU data bus
Digital power supply +3.3 V
CPU data bus
Digital ground
CPU data bus
Digital power supply +3.3 V
Video memory data bus
Digital ground
Video memory data bus
Digital ground
Video memory data bus
Digital power supply +3.3 V
Video memory data bus
Digital ground
Video memory data bus
Digital power supply +3.3 V
Video memory data mask output
Digital ground
Video memory write enable
Video memory data mask output
Video memory column address strobe output
Video memory clock output
Video memory low address strobe output
Digital ground
Video memory chip enable
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
11 0
111
11 2
11 3
11 4
11 5
11 6
11 7
11 8
11 9
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176SA13
VDDSA11
SA12
SA9
SA10
SA8
SA0
V
SSSA1
SA6
SA7
V
DDSA2
SA5
SA3
SA4
V
SSGCK2OUT
VDDDRO0
DRO1
DRO2
DRO3
DRO4
DRO5
DGO0
DGO1
V
SSDGO2
DGO3
V
DDDGO4
DGO5
DBO0
DBO1
DBO2
DBO3
V
SSDBO4
DBO5
YS_N
BLANK_N
V
DDDACVSSR
G
B
IREF
DACV
DDTEST2_N
TEST1_N
TEST0_N
CSYNC_N
VSYNC_N
GCK1OUT
V
DDGCK2IN
DRI0
V
SSDRI1
DRI2
DRI3
DRI4
DRI5
DGI0
DGI1
DGI2
DGI3
V
DDDGI4
VSSDGI5
DBI0
DBI1
DBI2
DBI3
DBI4
DBI5
HSIN_N
VSIN_N
V
DDVSSGCK1IN
SYCKIN
PLLV
DDPLLVSSFILTERO
-
O
O
O
O
O
O
-
O
O
O
-
O
O
O
O
-
O
-
O
O
O
O
O
O
O
O
-
O
O
-
O
O
O
O
O
O
-
O
O
O
O
-
-
O
O
O
-
-
I
I
I
O
O
O
-
I
I
-
I
I
I
I
I
I
I
I
I
-
I
-
I
I
I
I
I
I
I
I
I
-
-
I
I
-
-
-Video memory address bus
Digital power supply +3.3 V
Video memory address bus
Digital ground
Video memory address bus
Digital power supply +3.3 V
Video memory address bus
Digital ground
Dot clock output 2
Digital power supply +3.3 V
Digital R signal output
Digital G signal output
Digital ground
Digital G signal output
Digital power supply +3.3 V
Digital G signal output
Digital B signal output
Digital ground
Digital B signal output
YS signal output
Non-display interval output
Digital power supply +3.3 V
DAC analog ground
Analog R signal output
Analog G signal output
Analog B signal output
DAC reference electric-current input
DAC analog power supply +3.3 V
Test pin
Horizontal synchronized signal / Compound synchronized signal outputVertical synchronized signal output
Dot clock output 1
Digital power supply +3.3 V
Dot clock input 2
Digital R signal input
Digital ground
Digital R signal input
Digital G signal input
Digital power supply +3.3 V
Digital G signal input
Digital ground
Digital G signal input
Digital B signal input
Horizontal synchronized signal input
Vertical synchronized signal input
Digital power supply +3.3 V
Digital ground
Dot clock input 1
System clock input
PLL analog power supply +3.3 V
PLL analog ground
Filter connect pin for PLL
YGV628B-VZ(X6356B00) RGB CONTROLLER AVDP7DM: IC402 
						

							Tyros3
38
PIN
NO.I/O
FUNCTION NAMEPIN
NO.I/O
FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74OC3_N
REF5V
ID
GND
VREG(1V8)
VCC(5V0)
VCC(5V0)
GND
VREG(3V3)
VCC(I/O)
XTAL1
XTAL2
CLKIN
GND
GND
RREF1
GND
DM1
GND
DP1
PSW1_N
GND
RREF2
GND
DM2
GND
DP2
PSW2_N
GND
RREF3
GND
DM3
GND
DP3
PSW3_N
GND
DATA0
DATA1
DATA2
VCC(I/O)
DATA3
DATA4
DATA5
GND
DATA6
DATA7
DATA8
VCC(I/O)
DATA9
VREG(1V8)
DATA10
DATA11
GND
DATA12
GND
DATA13
DATA14
DATA15
VCC(I/O)
DATA16
DATA17
DATA18
GND
DATA19
DATA20
DATA21
VCC(I/O)
DATA22
DATA23
DATA24
GND
DATA25
DATA26
DATA27I
I
I
O
I
I
O
I
O
I
I
I/O
I/O
O
I
I/O
I/O
O
I
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/OPort 3 analog (5 V input) and digital overcurrent input
Input, 3.3 V tolerant
5 V reference input for analog OC detector; Connect a 100 nF decoupling capacitorID input for detection of the default host or peripheral setting when port 1 is in the OTG modeInput, 3.3 V tolerant
Analog ground
Core power output (1.8 V); Internal 1.8 V for the digital core; Used for decoupling; Connect a 100 nF capacitorInput to internal regulators (3.0 V to 5.5 V); Connect a 100 nF decoupling capacitorOscillator groundRegulator output (3.3 V); For decoupling only; Connect a 100 nF capacitor and a 4.7 mF to 10 mF capacitorDigital supply; 1.65 V to 3.6 V; Connect a 100 nF decoupling capacitor12 MHz crystal connection input; Connect to ground if an external clock is used12 MHz crystal connection output12 MHz oscillator or clock input; Connect to VCC(I/O) when not in use 3.3 V tolerantDigital ground
RREF1 ground
Reference resistor connection; Cconnect a 12 kW¶1 % resistor between this pin and the RREF1 groundAnalog ground for port 1
Downstream data minus port 1
Analog ground
Downstream data plus port 1
Power switch port 1, active LOW
Output pad, push-pull open-drain, 8 mA output drive, 5 V tolerantRREF2 groundReference resistor connection; Connect a 12 kW¶1 % resistor between this pin and the RREF2 groundAnalog ground for port 2
Downstream data minus port 2
Analog ground
Downstream data plus port 2
Power switch port 2, active LOW
Output pad, push-pull open-drain, 8 mA output drive, 5 V tolerantRREF3 groundRreference resistor connection; Connect a 12 kW¶1 % resistor between this pin and the RREF3 groundAnalog ground for port 3
Downstream data minus port 3
Analog ground
Downstream data plus port 3
Power switch port 3, active LOW
Output pad, push-pull open-drain, 8 mA output drive, 5 V tolerantDigital ground
Data bit 0 input and output
Bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantData bit 1 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantData bit 2 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantDigital supply; 1.65 V to 3.6 V; Connect a 100 nF decoupling capacitorData bit 3 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantData bit 4 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantData bit 5 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantDigital ground
Data bit 6 input and output
Bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantData bit 7 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantData bit 8 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantDigital supply; 1.65 V to 3.6 V; Connect a 100 nF decoupling capacitorData bit 9 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantCore power output (1.8 V); Internal 1.8 V for the digital core; Used for decoupling; Connect a 100 nF capacitorData bit 10 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantData bit 11 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantCore ground
Data bit 12 input and output
Bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantDigital ground
Data bit 13 input and output
Bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantData bit 14 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantData bit 15 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantDigital supply; 1.65 V to 3.6 V; Connect a 100 nF decoupling capacitorData bit 16 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantData bit 17 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantData bit 18 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantDigital ground
Data bit 19 input and output
Bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantData bit 20 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantData bit 21 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantDigital supply; 1.65 V to 3.6 V; Connect a 100 nF decoupling capacitorData bit 22 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantData bit 23 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantData bit 24 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantDigital ground
Data bit 25 input and output
Bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantData bit 26 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantData bit 27 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
11 0
111
11 2
11 3
11 4
11 5
11 6
11 7
11 8
11 9
120
121
122
123
124
125
126
127
128VCC(I/O)
DATA28
DATA29
DATA30
GND
DATA31
TEST
A1
VCC(I/O)
A2
VREG(1V8)
A3
A4
GND
A5
GND
A6
A7
A8
VCC(I/O)
A9
A10
A11
A12
GND
A13
A14
A15
A16
VCC(I/O)
A17
CS_N
RD_N
WR_N
GND
VBAT_ON_N
DC_IRQ
HC_IRQ
DC_DREQ
HC_DREQ
VCC(I/O)
HC_DACK
DC_DACK
VREG(1V8)HC_SUSPEND/WAKEUP_N
DC_SUSPEND/WAKEUP_N
GND
RESET_N
GND
C_B
C_A
VCC(C_IN)OC1_N/VBUS
OC2_NI/O
I/O
I/O
I/O
I
I
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
I
I
O
I/O
I/O
I
I/O
I/O
I
I/O,I
I
Digital supply; 1.65 V to 3.6 V; Connect a 100 nF decoupling capacitorData bit 28 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantData bit 29 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantdata bit 30 input and outputBidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantDigital ground
Data bit 31 input and output
Bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerantConnect to ground
Address pin 1
Input, 3.3 V tolerant
Digital supply; 1.65 V to 3.6 V; Connect a 100 nF decoupling capacitorAddress pin 2
Input, 3.3 V tolerant
Core power output (1.8 V); Internal 1.8 V for the digital core; Used for 
decoupling; Connect a 100 nF capacitor and a 4.7 mF to 10 mF capacitor
Address pin 3
Input, 3.3 V tolerant
Address pin 4
Input, 3.3 V tolerant
Core ground
Address pin 5
Input, 3.3 V tolerant
Digital ground
Address pin 6
Input, 3.3 V tolerant
Address pin 7
Input, 3.3 V tolerant
Address pin 8
Input, 3.3 V tolerant
Digital supply; 1.65 V to 3.6 V; Connect a 100 nF decoupling capacitorAddress pin 9
Input, 3.3 V tolerant
Address pin 10
Input, 3.3 V tolerant
Address pin 11
Input, 3.3 V tolerant
Address pin 12
Input, 3.3 V tolerant
Digital ground
Address pin 13
Input, 3.3 V tolerant
Address pin 14
Input, 3.3 V tolerant
Address pin 15
Input, 3.3 V tolerant
Address pin 16
Input, 3.3 V tolerant
Digital voltage; 1.65 V to 3.6 V; Connect a 100 nF decoupling capacitorAddress pin 17
Input, 3.3 V tolerant
Chip select signal that indicates the area being accessed; Active LOWInput, 3.3 V tolerant
Read enable; Active LOW
Input, 3.3 V tolerant
Write enable; Active LOW
Input, 3.3 V tolerant
Digital ground
To indicate the presence of a minimum 3.3 V on pins 6 and 7 
(open-drain); Connect to VCC(I/O) through a 10 kW pull-up resistor
Output pad, push-pull open-drain, 8 mA output drive, 5 V tolerantPeripheral Controller interrupt signal
Output 4 mA drive, 3.3 V tolerant
Host Controller interrupt signal
Output 4 mA drive, 3.3 V tolerant
DMAC request for the Peripheral Controller output 4 mA drive;  3.3 V tolerantDMAC request for Host Controller
Output 4 mA drive, 3.3 V tolerant
Digital voltage; 1.65 V to 3.6 V; Connect a 100 nF decoupling capacitorHost Controller DMA request acknowledgment; When not in 
use, connect to VCC(I/O) through a 10 kW pull-up resistor
Input, 3.3 V tolerant
Peripheral Controller DMA request acknowledgment; When not 
in use, connect to VCC(I/O) through a 10 kW pull-up resistor
Input, 3.3 V tolerant
Core power output (1.8 V); Internal 1.8 V for the digital core; Used for decoupling; Connect a 100 nF capacitorHost Controller suspend and wake-up; Three-state suspend output 
(active LOW) and wake-up input circuits are connected together
Ô HIGH = output is three-state; ISP1761 is in suspend mode.Ô LOW = output is LOW; ISP1761 is not in suspend mode.Connect to VCC(I/O) throug h an external 10 kW pull-up resistor 
output pad, open-drain, 4 mA output drive, 3.3 V tolerant
Peripheral Controller suspend and wake-up; Three-state suspend 
output (active LOW) and wake-up input circuits are connected together.
Ô HIGH = output is three-state; ISP1761 is in suspend mode.Ô LOW = output is LOW; ISP1761 is not in suspend mode.
Connect to VCC(I/O) through an external 10 kW pull-up resistor
Output pad, open-drain, 4 mA output drive, 3.3 V tolerant
Core ground
External power-up reset; Active LOW
Input, 3.3 V tolerant
Analog ground
Charge pump capacitor input; Connect a 220 nF capacitor between this pin and pin 125
Charge pump capacitor input; Connect a 220 nF capacitor between this pin and pin 124
Charge pump input; Connect to 3.3 V
This pin has multiple functions:
ÔPort 1 OC1_N detection when port 1 is configured for host functionality and an 
external power switch is used; Connect to VCC(I/O) through a 10 kW resistor
ÔVBUS out when internal charge pump is used and port 1 is configured for 
the host functionality; Maximum 50 mA current capability; Only for port 1
ÔVBUS input detection when port 1 is defined for the peripheral functionality.Input, 3.3 V tolerant
Port 2 analog (5 V input) and digital overcurrent input;
  If not used, connect to VCC(I/O) through a 10 kW resistor
Input, 3.3 V tolerant
ISP1761BE (X9073A00) HI-SPEED USB OTG CONTROLLERDM: IC207 
						

							39 Tyros3
PIN
NO.I/O
FUNCTION NAMEPIN
NO.I/O
FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104LVDDXDACK
XDRAK
XDREQ
ATPGEN
Vss
ENCA0
ENCB0
ENCA1
ENCB1
HV
DDENCA2
ENCB2
ENCA3
ENCB3
Vss
ENCA4
ENCB4
ENCA5
ENCB5
HV
DDTSTEN
XIDCS0
XIDCS1
XIDDOE
Vss
HV
DDXIDWR
XIDRD
XIDMACK
IDMARQ
Vss
IDD0
IDD1
IDD2
IDD3
HV
DDIDD4
IDD5
IDD6
IDD7
Vss
IDD8
IDD9
IDD10
IDD11
HV
DDIDD12
IDD13
IDD14
IDD15
Vss
LV
DDSDRD0
SDRD1
SDRD2
SDRD3
Vss
SDRD4
SDRD5
SDRD6
SDRD7
LV
DDSDRD8
SDRD9
SDRD10
SDRD11
Vss
SDRD12
SDRD13
SDRD14
SDRD15
LV
DDSDRA0
SDRA1
SDRA2
SDRA3
Vss
LV
DDSDRA4
SDRA5
SDRA6
SDRA7
Vss
SDRA8
SDRA9
SDRA10
SDRA11
LV
DDSDRA12
SDRA13
XSDRWE
XSDRRAS
Vss
XSDRCAS
XSDRCS0
XSDRCS1
SDRDQM
LV
DDSDRCLK
XTCLR
HV
DDTESTRAM
VssI
I
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
IPower supply +3.3V
CPU DMA acknowledge
CPU DREQ request acknowledge
CPU DMA request
ATPG test input
Ground
Encoder0 A  input
Encoder0 B input
Encoder1 A  input
Encoder1 B input
Power supply +5V
Encoder2 A  input
Encoder2 B input
Encoder3 A  input
Encoder3 B input
Ground
Encoder4 A  input
Encoder4 B input
Encoder5 A  input
Encoder5 B input
Power supply +5V
Test mode change
IDE chip select
IDE bus buffer DIR signal
Ground
Power supply +5V
IDE write signal
IDE read signal
IDE DMA acknowledge
IDE DMA request
Ground
IDE data bus
Power supply +5V
IDE data bus
Ground
IDE data bus
Power supply +5V
IDE data bus
Ground
Power supply +3.3V
SDRAM data bus
Ground
SDRAM data bus
Power supply +3.3V
SDRAM data bus
Ground
SDRAM data bus
Power supply +3.3V
SDRAM address output
Ground
Power supply +3.3V
SDRAM address output
Ground
SDRAM address output
Power supply +3.3V
SDRAM address output
SDRAM write signal
SDRAM row address strobe
Ground
SDRAM column address strobe
SDRAM chip select
SDRAM data enable
Power supply +3.3V
SDRAM clock
Test counter clear
Power supply +5V
RAM test mode
Ground105
106
107
108
109
11 0
111
11 2
11 3
11 4
11 5
11 6
11 7
11 8
11 9
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208HV
DDLEDD0
LEDD1
LEDD2
LEDD3
Vss
LV
DDXTA22I
Vss
XTA22O
LV
DDHVDDLEDD4
LEDD5
LEDD6
LEDD7
Vss
VCOI
HV
DDPDOUT
Vss
XRESET
EXTWCI
SDIN
SDOUT
HV
DDXDSPCS0
XDSPCS2
XDSPCS1
Vss
AUDIOIN0
AUDIOIN1
AUDIOUT0
LV
DDAUDIOUT1
AUDIOUT2
AUDIOUT3
Vss
AUDIOUT4
AUDIOUT5
AUDIOUT6
LV
DDHVDDCK512
FS256
FS128
Vss
XFS64
ALRCK
XSSYNC
HV
DDVss
LVDDHVDDXDLCS
XLCDCS0
XLCDCS1
Vss
CD0
CD1
CD2
CD3
LV
DDCD4
CD5
CD6
CD7
Vss
CD8
CD9
CD10
CD11
LV
DDCD12
CD13
CD14
CD15
Vss
LV
DDCA1
CA2
CA3
CA4
Vss
CA5
CA6
CA7
CA12
LV
DDCA13
CA16
XCCS5
XCCS6
Vss
XCRD
XCWR
XCIRQ
XFTMIRQ1
LV
DDXFTMIRQ2
XFTMIRQ3
FSPLAY
SCANEN
VssO
O
O
O
I
O
O
O
O
O
I
O
I
I
I
O
O
O
O
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
IPower supply +5V
Port/Test output
Ground
Power supply +3.3V
XTAL input terminal
Ground
XTAL output terminal
Power supply +3.3V
Power supply +5V
Port/Test output
Ground
VCO clock input
Power supply +5V
PLL phase comparator output
Ground
Reset signal input
External synchronization WC input
Digital sound input
Digital sound output
Power supply +5V
DSP6 chip select
DSP chip select (reserve)
DSP7 chip select
Ground
Audio data input
Audio data output
Power supply +3.3V
Audio data output
Ground
Audio data output
Power supply +3.3V
Power supply +5V
FS512 clock
FS256 clock
FS128 clock
Ground
FS64 clock (reverse)
System WC (FS)
DSP synchronizing signal output
Power supply +5V
Ground
Power supply +3.3V
Power supply +5V
Data buffer enable
LCD driver chip select
Ground
CPU data bus
Power supply +3.3V
CPU data bus
Ground
CPU data bus
Power supply +3.3V
CPU data bus
Ground
Power supply +3.3V
CPU address input
Ground
CPU address input
Power supply +3.3V
CPU address input
CPU chip select
Ground
CPU read signal
CPU write signal
CPU interrupt request
Power supply +3.3V
CPU interrupt request
FS count signal
Scan enable input
Ground
S1L52502F24J200 (X2688A0R) GATE ARRAYDM: IC203 
						

							Tyros3
40
PIN
NO.I/O
FUNCTION
NAMEPIN
NO.I/O
FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40CLKI
CLKO
V
DDSCANENB
ATPGENB
VSSPLLTESTPLLRES
PLLVSSMVDDPLLVSSAVDDCHG0
LPVSSVSSMIRQ
MCS
MWR
MRD
MA
V
DDMD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
V
SSMD8
VDDMD9
MD10
MD11
MD12
MD13
MD14
MD15
V
SS
I
O
-
I/O
I/O
-
I
I
-
-
-
-
-
-
I/O
I
I
I
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-Clock
Power supply
Scan enable
Ground
Te s t
Reset
Ground
Power supply
Ground
Analog power supply
Ground
Interrupt request
Control port
Write
Read
Power supply
DRAM data bus
Ground
DRAM data bus
Power supply
DRAM data bus
Ground41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80VDDRESET
VSSOUT4
OUT3
INP2
INP1
INP0
TESTENBVSSOSCO
VDDOSCI
VSSSIRQ
SCS
SWR
SRD
SA
V
SSVDDSD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
V
SSSD8
VDDSD9
SD10
SD11
SD12
SD13
SD14
SD15
V
SS
-
I
-
O
O
I
I
I
I/O
-
-
-
I/O
I
I
I
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-Power supply
Reset
Ground
Output
Input
Test enable
Ground
Power supply
Ground
Interrupt request
Control port
Write
Read
Ground
Power supply
Serial data
Ground
Serial data
Power supply
Serial data
Ground
DM: IC503S1L50553F21Y000 (X4195A0R) MCI (Gate Array)
 1  GND1  -  Ground
  2  R-IN  I  Analog R signal input
  3  G-IN  I  Analog G signal input
  4  B-IN  I  Analog B signal input
 5  N.C.  -  Not used 
 6  fsc-IN  I  Subcarrier input
 7 
NTSC/PAL-IN I  NTSC/PAL selector
 8  N.C.  -  Not used
 9  N.C.  -  Not used
 10 
CSYNC-IN  I  Composite sync signal input
 11  N.C.  -  Not used
  12  Vcc1  -  Power supply +5 V 13  N.C.  -  Not used 
 14  N.C.  -  Not used 
 15 
CROMA-OUT O Chrominance signal output
 16  Y-OUT  O  Y-signal output
  17  Y-TRAP  -  Luminance signal band control
 18  N.C.  -  Not used 
  19  Vcc2  -  Power supply +5 V
 20 
VIDEO-OUT  O  Composite video signal output
  21  B-OUT  O  Analog B signal output
  22  G-OUT  O  Analog G signal output
  23  R-OUT  O  Analog R signal output
 24  GND2  -  Ground
PIN
NO.I/O FUNCTION NAMEPIN
NO.I/O FUNCTION NAME
MB3516APF-G-BND-EF(X2314A00)RGB ENCODERDM: IC406