Samsung Exynos 5 User Manual

Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-17  
1.4.7 High Speed Interfaces 
This section includes: 
 USB DRD (Dual Role Device) 3.0 Interface  
 USB Host 2.0 Interface 
 USB Device 2.0 Interface 
 USB HSIC 1.0 Interface 
 SATA 3.0 Interface 
 
1.4.7.1 USB DRD (Dual Role Device) 3.0 Interface 
 Both USB Device 3.0 and USB Device 2.0 compliant 
 Both USB HOST 3.0 and USB HOST 2.0 compliant 
 Supports both USB Device 3.0 interface and USB Device 2.0 interface 
 Supports both USB...

Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-18  
1.4.7.3 USB Device 2.0 Interface 
 USB Device 2.0 compliant 
 Supports low-speed (1.5 Mbps), full-speed (12 Mbps), and high-speed (480 Mbps) modes 
 Supports one USB device port. (muxed with USB2.0 Host) 
 One Control Endpoint 0 for control transfer 
 15 Device Mode programmable Endpoints 
 
1.4.7.4 USB HSIC 1.0 Interface 
 USB HSIC 1.0 compliant 
 Supports 480 Mbps 
 Supports two HSIC ports 
 On-chip USB PHY transceiver 
 HSIC...

Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-19  
1.4.8 External Peripheral 
This section includes: 
 eMMC and SD Interface 
 UART Interface 
 UART Interface in ISP 
 SPI Interface 
 SPI Interface in ISP 
 I2S Bus Interface 
 PCM Audio Interface 
 AC97 Audio Interface 
 S/PDIF Interface 
 I2C Bus Interface 
 HS-I2C 
 Configurable GPIOs  
 Global A/D Converter 
 
1.4.8.1 eMMC and SD Interface 
 Multimedia Card Protocol version 4.5 compatible (eMMC) 
 Secure Digital I/O...

Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-20  
1.4.8.3 UART Interface in ISP 
 One-port high-speed UART with DMA-based or interrupt-based operation 
 UART FIFO: 64 bytes one-port 
 Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit and receive 
 Programmable baud rate 
 Supports IrDA 1.0 SIR (115.2 Kbps) mode 
 Loop back mode for testing 
 Non-integer clock divide in Baud clock generation (BRM) 
 
1.4.8.4 SPI Interface 
 Three-channel Serial Peripheral Interface 
 Up...

Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-21  
1.4.8.7 PCM Audio Interface 
 16-bit mono audio interface 
 Master mode only 
 
1.4.8.8 AC97 Audio Interface 
 Independent channels for stereo PCM In, stereo PCM Out, and mono MIC In 
 16-bit stereo (2-channel) audio 
 Variable sampling rate AC97 Codec interface (48 KHz and below) 
 Supports AC97 Full Specification 
 
1.4.8.9 S/PDIF Interface 
 Linear PCM up to 24-bit per sample support 
 Non-linear PCM formats such as AC3, MPEG1,...

Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-22  
1.4.8.11 HS-I2C 
 Support four channel high speed I2C mode (up to 3.1 Mbps) 
 Supports operation based on DMA or interrupt 
 Transmits and receives data separately 
 Supports non-integer clock division 
 Operates in two modes: Master and slave 
 
1.4.8.12 Configurable GPIOs 
 Controls 205 External Interrupts  
 Controls 32 External Wake-up Interrupts  
 253 multi-functional input/output ports  
 Controls pin states in Sleep Mode,...

Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-23  
1.4.9 Modem Interfaces 
This section includes: 
 HSIC 
 MIPI HSI 
 C2C 
 
1.4.9.1 HSIC 
 USB HSIC 1.0 compliant 
 Supports two HSIC ports 
 Supports 480 Mbps with half duplex transfer 
 Supports maximum 10 Cm trace length 
 
1.4.9.2 MIPI HSI 
 Compliant to HSI specification version 1.0 
 Full-Duplex High Speed Serial Interface 
 Supports eight-logical channels for both transmit and receive operations  
 Maximum bandwidth of 200...

Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-24  
1.4.10 Low Power Co-Processor 
This section includes: 
 Samsung Reconfigurable Processor 
 Cortex-A5 
 
1.4.10.1 Samsung Reconfigurable Processor 
 Low power and ultra low power audio mode 
 
1.4.10.2 Cortex-A5 
 Low power co-processor unit 
 ARM Cortex-A5 core processor uses ARMv7-A architecture 
 16 KB instruction cache and 16 KB data cache 
 
  

Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-25  
1.4.11 System Peripheral 
This section includes: 
 Real Time Clock 
 PLL 
 Timer with Pulse Width Modulation 
 Multi-Core Timer 
 16-bit W atch Dog Timer 
 DMA 
 Generic Interrupt Controller  
 Power Management 
 
1.4.11.1 Real Time Clock 
 Full clock features: Second, minute, hour, date, day, week, month, and year 
 32.768 kHz operation 
 Alarm interrupt 
 Time-tick interrupt 
 
1.4.11.2 PLL 
 Seven on-chip PLLs: APLL, MPLL,...

Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-26  
1.4.11.3 Timer with Pulse Width Modulation 
 Four channel 32-bit timer with PW M 
 One channel 32-bit internal timer with DMA-based or interrupt-based operation 
 Programmable duty cycle, frequency, and polarity 
 Dead-zone generation 
 Supports external clock source 
 
1.4.11.4 Multi-Core Timer 
 Two private timers 
 A 32-bit counter that generates an interrupt when it reaches zero  
 Configurable single-shot or auto-reload modes...