Nintendo 8 Bit Manual

							 
 
31
5 - Input Devices 
 
5.1 Control Pad 
 
The 6502 used memory mapped I/O (input/output). This means that the same instructions 
and bus are used to communicate with I/O devices as with memory, that writing to a specific 
memory location writes to the appropriate device. In the NES, the I/O ports for input devices 
were $4016 and $4017 (see Appendix B). 
 
The original NES used a rectangular control pad as shown in figure 5-1. The pad featured 
four buttons, A, B, Start and Select as well as a four-directional cross used to control 
movement. Although many variations were released, often with additional features such as 
slow motion and turbo fire, the original design was by far the most commonly used. 
 
 
 
Figure 5-1. Original NES control pad [43]. 
 
The system reads multiple times from the I/O port to get all information about the controller. 
Each of the first eight reads indicates the status of one button on the standard controller in 
the order A, B, Select, Start, Up, Down, Left, Right. The first controller is attached to port 
$4016, the second to $4017. Using a four-player adapter it was possible to connect four 
controllers to the system, although this was rare. In this case controllers 1 and 3 were 
attached to $4016 and 2 and 4 to $4017. The next eight reads would get the status of the 
second controller on the port, otherwise they are ignored. 
 
Reads 17-20 retrieve the signatures which identify whether a device is connected and if so, 
what type of device [7]. If a joypad is connected to $4016 the returned value is 01b, if one is 
connected to $4017 the returned value is 10b. There are four more reads which are not 
required before the cycle starts again. 
 
The process of reading from an I/O device can be reset by use of a strobing method. When a 
reset is required, it is indicated by first writing a 1 to the port, followed by a 0. 
 
5.2 Zapper 
 
When the NES first launched in America, Nintendo included a light-gun known as the 
Zapper. Figure 5-2 shows the original version of the Zapper, although the colour was later 
changed to orange. By aiming using the sight, the gamer could produce quite accurate 
results. Several games featured Zapper support including Duck Hunt, Gumshoe and Wild 
Gunman [44]. 
  
						

							 
 
32
 
 
Figure 5-2. Original NES Zapper light-gun [45]. 
 
“The Zapper works by receiving the light from the screen. The contrast and 
brightness controls of the TV must be adjusted properly or the shots may not 
register. (The characters should be as bright as possible while the background 
areas should be as dark as possible.)” 
 
The above description of how the Zapper works is taken from the light-guns manual as 
quoted in [44]. Essentially, the Zapper works by measuring the intensity of the light at the 
point it is aimed at. When the system detects the trigger is pulled, it draws a white box 
around the sprites on the screen. The Zapper can then check the colour intensity and 
determine if it is pointed at a white area, which is a sprite, or a dark area, which belongs to 
the background. 
 
  
						

							 
 
33
Appendix A 
Arithmetic And Logic 
 
A.1 Numbering Systems 
 
The hexadecimal number system uses base 16 with digits 0-9 and A-F, where A represents 
10 and F represents 15. The hexadecimal system is used frequently throughout this 
document and any numbers written in this format will be indicated by use of the prefixes $ 
and 0x (used interchangeably). For example, $2F = (2 * 16) + 15 = 47. 
 
The binary number system uses base 2 with digits 0 and 1. This system is also frequently 
used and any numbers written in this format will be indicated by use of the suffix b. For 
example 101111b = 32 + 8 + 4 + 2 + 1 = 47. 
 
A.2 Binary Coded Decimal (BCD) 
 
Binary Coded Decimal represents each digit by a group of 4 bits. The technique is less 
efficient than traditional binary notation. As an example, 123 represented in binary is 
1111011b but the equivalent BCD representation is 000100100011b. 
 
A.3 Two’s Complement 
 
Two’s complement is a method for representing negative numbers in binary. The most 
significant bit is the sign, with 0 being positive, while 1 is negative. The range available in a 
single byte is therefore -128 to 127, rather than 0 to 255. 
 
A.4 Wraparound 
 
The maximum value of an unsigned byte is 255. Increasing the value causes it to wrap 
around to 0. Similarly, decrementing from 0 results in a value of 255. With a signed byte, the 
maximum positive value is 127, and incrementing beyond this will result in bit 7 being set and 
the value becoming -128. Around 0, the value changes smoothly between positive and 
negative numbers. Therefore with unsigned bytes, wraparound occurs between 255 and 0 
and with signed bytes, it occurs between 127 and -128. 
 
 
 
Figure A-1. Wraparound of both unsigned (left) and signed (right) 8-bit integers. 
  
						

							 
 
34
Appendix B 
NES I/O Registers 
 
The following information is based on [7]: 
 
Address Access Level Description 
$2000  Write  PPU Control Register 1: 
 
•  Bits 0-1 - Name table address, changes between the four 
name tables at $2000 (0), $2400 (1), $2800 (2) and $2C00 
(3). 
•  Bit 2 - Specifies amount to increment address by, either 1 if 
this is 0 or 32 if this is 1. 
•  Bit 3 - Identifies which pattern table sprites are stored in, 
either $0000 (0) or $1000 (1). 
•  Bit 4 - Identifies which pattern table the background is 
stored in, either $0000 (0) or $1000 (1). 
•  Bit 5 - Specifies the size of sprites in pixels, 8x8 if this is 0, 
otherwise 8x16. 
•  Bit 6 - Changes PPU between master and slave modes. 
This is not used by the NES. 
•  Bit 7 - Indicates whether a NMI should occur upon V-Blank. 
$2001  Write  PPU Control Register 2: 
 
•  Bit 0 - Indicates whether the system is in colour (0) or 
monochrome mode (1), 
•  Bit 1 - Specifies whether to clip the background, that is 
whether to hide the background in the left 8 pixels on 
screen (0) or to show them (1). 
•  Bit 2 - Specifies whether to clip the sprites, that is whether 
to hide sprites in the left 8 pixels on screen (0) or to show 
them (1). 
•  Bit 3 - If this is 0, the background should not be displayed. 
•  Bit 4 - If this is 0, sprites should not be displayed. 
•  Bits 5-7 - Indicates background colour in monochrome 
mode or colour intensity in colour mode. 
$2002  Read  PPU Status Register: 
 
•  Bit 4 - If set, indicates that writes to VRAM should be 
ignored. 
•  Bit 5 - Scanline sprite count, if set, indicates more than 8 
sprites on the current scanline. 
•  Bit 6 - Sprite 0 hit flag, set when a non-transparent pixel of 
sprite 0 overlaps a non-transparent background pixel. 
•  Bit 7 - Indicates whether V-Blank is occurring. 
$2003  Write  SPR-RAM Address Register: 
 
Holds the address in SPR-RAM to access on the next write to 
$2004. 
$2004  Write  SPR-RAM I/O Register: 
 
Writes a byte to SPR-RAM at the address indicated by $2003. 
$2005  Write  VRAM Address Register 1.  
						

							 
 
35
$2006  Write  VRAM Address Register 2. 
$2007  Read / Write  VRAM I/O Register: 
 
Reads or writes a byte from VRAM at the current address. 
$4000  Write  pAPU Pulse 1 Control Register. 
$4001  Write  pAPU Pulse 1 Ramp Control Register. 
$4002  Write  pAPU Pulse 1 Fine Tune (FT) Register. 
$4003  Write  pAPU Pulse 1 Coarse Tune (CT) Register. 
$4004  Write  pAPU Pulse 2 Control Register. 
$4005  Write  pAPU Pulse 2 Ramp Control Register. 
$4006  Write  pAPU Pulse 2 Fine Tune Register. 
$4007  Write  pAPU Pulse 2 Coarse Tune Register. 
$4008  Write  pAPU Triangle Control Register 1. 
$4009  Write  pAPU Triangle Control Register 2. 
$400A  Write  pAPU Triangle Frequency Register 1. 
$400B  Write  pAPU Triangle Frequency Register 2. 
$400C  Write  pAPU Noise Control Register 1. 
$400E  Write  pAPU Noise Frequency Register 1. 
$400F  Write  pAPU Noise Frequency Register 2. 
$4010  Write  pAPU Delta Modulation Control Register. 
$4011  Write  pAPU Delta Modulation D/A Register. 
$4012  Write  pAPU Delta Modulation Address Register. 
$4013  Write  pAPU Delta Modulation Data Length Register. 
$4014  Write  Sprite DMA Register: 
 
Writes cause a DMA transfer to occur from CPU memory at 
address $100 x n, where n is the value written, to SPR-RAM. 
$4015  Read / Write  pAPU Sound / Vertical Clock Signal Register. 
$4016  Read / Write  Joypad 1: 
 
•  Bit 0 - Reads data from joypad or causes joypad strobe 
when writing. 
•  Bit 3 - Indicates whether Zapper is pointing at a sprite. 
•  Bit 4 - Cleared when Zapper trigger is released. 
 
Only bit 0 is involved in writing. 
$4017  Read / Write  Joypad 2: 
 
When reading: 
 
•  Bit 0 - Reads data from joypad or causes joypad strobe 
when writing. 
•  Bit 3 - Indicates whether Zapper is pointing at a sprite. 
•  Bit 4 - Cleared when Zapper trigger is released. 
 
Only bit 0 is involved in writing.  
						

							 
 
36
Appendix C 
iNES Mapper Numbers 
 
The following mapper numbers are based on [9]: 
 
iNES Mapper Number  Mapper Name 
0 NROM, no mapper 
1 Nintendo MMC1 
2 UNROM switch 
3 CNROM switch 
4 Nintendo MMC3 
5 Nintendo MMC5 
6 FFE F4xxx 
7 AOROM switch 
8 FFE F3xxx 
9 Nintendo MMC2 
10 Nintendo MMC4 
11 ColorDreams chip 
12 FFE F6xxx 
15 100-in-1 switch 
16 Bandai chip 
17 FFE F8xxx 
18 Jaleco SS8806 chip 
19  Namcot 106 chip 
20 Nintendo DiskSystem 
21 Konami VRC4a 
22 Konami VRC2a 
23 Konami VRC2a 
24 Konami VRC6 
25 Konami VRC4b 
32 Irem G-101 chip 
33 Taito TC0190/TC0350 
34  32 KB ROM switch 
64 Tengen RAMBO-1 chip 
65 Irem H-3001 chip 
66 GNROM switch 
67 SunSoft3 chip 
68 SunSoft4 chip 
69  SunSoft5 FME-7 chip 
71 Camerica chip 
78 Irem 74HC161/32-based 
91 Pirate HK-SF3 chip 
 
  
						

							 
 
37
Appendix D 
Memory Mapper Functions 
 
The information in this section is based on [6] with additional information about MMC1 from 
[46]. 
 
D.1 UNROM Switch 
 
Address Data 
$8000-$FFFF  16 KB PRG-ROM bank number to load into $8000. 
 
On reset, the first PRG-ROM bank is loaded into $8000 and the last PRG-ROM bank is 
loaded into $C000. Switching is only allowed for the bank at $8000, the one at $C000 is 
permanently assigned to that location. Since this mapper has no support for VROM, games 
using it have 8 KB of VRAM at $0000 in PPU memory. 
 
D.2 CNROM Switch 
 
Address Data 
$8000-$FFFF  8 KB CHR-ROM bank number to load into PPU memory at $0000. 
 
With this mapper, PRG-ROM functions the same as with NROM (no mapper), so games with 
only one 16 KB bank of PRG-ROM will load it into both $8000 and $C000, those with two will 
load one into $8000 and the other into $C000. On reset, the first 8 KB VROM bank is loaded 
into PPU $0000. 
 
D.3 MMC1 
 
Address Data 
$8000-$9FFF Register 0: 
 
•  Bit 0 - Selects mirroring between horizontal (0) and vertical (1). 
•  Bit 1 - Set to 0 to cause single screen mirroring. 
•  Bit 2 - If 0, PRG-ROM swapped at $C000. If 1, PRG-ROM swapped at 
$8000. 
•  Bit 3 - If 0, swap 32 KB of PRG-ROM at $8000. If 1, swap 16 KB at the 
address specified by bit 2. 
•  Bit 4 - If the cartridge has VROM, 0 indicates swapping 8 KB of VROM 
at PPU $0000, 1 indicates swapping two 4 KB VROM pages at PPU 
$0000 and $1000. On 1024 KB cartridges this bit specifies whether to 
use 256 KB selection register 1. 
•  Bit 7 - Set to 1 to reset register. 
$A000-$BFFF Register 1: 
 
•  Bits 0-3 - VROM bank number to load into PPU $0000. Based on bit 4 
of register 0, this will either be 8 KB bank n, or 4 KB banks n and (n + 
1) where n is the value of bits 0-3. 
•  Bit 4 - 256 KB selection register 0. Stores the low bit of 256 KB PRG-
ROM selection in 1024 KB cartridges with bit 4 of register 0 set, 
otherwise 0 indicates swapping from first 256 KB of PRG-ROM, 1 
indicates swapping from third 256 KB of PRG-ROM. In 512 KB 
cartridges, 0 indicates swapping from first 256 KB of PRG-ROM, 1 
indicates swapping from second 256 KB of PRG-ROM.  
						

							 
 
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•  Bit 7 - Set to 1 to reset register. 
$C000-$DFFF Register 2: 
 
•  Bits 0-3 - VROM bank number to load into PPU $1000. If bit 4 of 
register 0 is set, this will be 4 KB banks n and (n + 1) where n is the 
value of bits 0-3, otherwise it is ignored. 
•  Bit 4 - 256 KB selection register 1. Stores the high bit of 256 KB PRG-
ROM selection in 1024 KB cartridges. 
•  Bit 7 - Set to 1 to reset register. 
$E000-$FFFF Register 3: 
 
•  Bits 0-3 - PRG-ROM bank number to load into memory. If bit 3 of 
register 0 is clear, swaps 32 KB at $8000, otherwise swaps a 16 KB 
bank at either $8000 or $C000 based on bit 2 of register 0. 
•  Bit 7 - Set to 1 to reset register. 
 
On reset, the first PRG-ROM bank is loaded into $8000 and the last PRG-ROM bank is 
loaded into $C000. Values are written to the registers in MMC1, one bit at a time until five 
bits have been written. By writing a value with bit 7 set, this buffering can be reset, causing 
the next write to be to bit 0 of the register. The buffering is also reset by writing to a different 
register. 256 KB swapping is not currently supported by the implementation of MMC1 in 
NES#. 
 
D.4 MMC3 
 
Address Data 
$8000 
•  Bits 0-2 - Command number: 
•  0 - Swap two 1 KB VROM banks at PPU $0000. 
•  1 - Swap two 1 KB VROM banks at PPU $0800. 
•  2 - Swap one 1 KB VROM bank at PPU $1000. 
•  3 - Swap one 1 KB VROM bank at PPU $1400. 
•  4 - Swap one 1 KB VROM bank at PPU $1800. 
•  5 - Swap one 1 KB VROM bank at PPU $1C00. 
•  6 - Swap PRG-ROM bank at either $8000 or $A000 based on bit 6. 
•  7 - Swap PRG-ROM bank at either $A000 or $C000 based on bit 
6. 
•  Bit 6 - If 0, enables swapping at $8000 and $A000, otherwise enables 
swapping at $A000 and $C000. 
•  Bit 7 - If 1, causes addresses for commands 0-5 to be the exclusive-or 
of the address stated and $1000. 
$8001  Executes the command specified by $8000, using this as the page 
number. 
$A000 
•  Bit 1 - Selects mirroring between horizontal (0) and vertical (1). 
$A001 
•  Bit 7 - Set to enable save RAM at $6000-$7FFF. 
$C000  IRQ Counter Register used to countdown to an IRQ. 
$C001  IRQ Latch Register used to store a temporary value to be copied to the 
IRQ Counter Register later. 
$E000  IRQ Control Register 0 used to disable IRQ generation and copy the IRQ 
Latch Register to the IRQ Counter Register. 
$E001  IRQ Control Register 1 used to enable IRQ generation. 
 
On cartridges with VROM, the first 8 KB bank is swapped into PPU $0000 on reset.  
						

							 
 
39
Appendix E 
6502 Addressing Modes 
 
E.1 Zero Page 
 
Zero page addressing uses a single operand which serves as a pointer to an address in zero 
page ($0000-$00FF) where the data to be operated on can be found. By using zero page 
addressing, only one byte is needed for the operand, so the instruction is shorter and, 
therefore, faster to execute than with addressing modes which take two operands. An 
example of a zero page instruction is AND $12. 
 
 
 
Figure E-1. Zero page addressing.  
 
E.2 Indexed Zero Page 
 
Indexed zero page addressing takes a single operand and adds the value of a register to it to 
give an address in zero page ($0000-$00FF) where the data can be found. There are two 
forms of indexed zero page addressing: 
 
•  Zero Page, X - Add contents of X register to operand. This is the most common form of 
indexed zero page. An example of this addressing mode is AND $12,X. 
•  Zero Page, Y - Add contents of Y register to operand. This mode can only be used with 
LDX (Load X Register) and STX (Store X Register). An example of this addressing mode 
is LDX $12,Y. 
 
Wraparound is used when performing the addition so the address of the data will always be 
in zero page. For example, if the operand is $FF and the X register contains $01 the address 
of the data will be $0000, not $0100. 
  
						

							 
 
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Figure E-2. Indexed zero page addressing. 
 
E.3 Absolute 
 
In absolute addressing, the address of the data to operate on is specified by the two 
operands supplied, least significant byte first. An example of an absolute instruction is AND 
$1234. 
 
 
 
Figure E-3. Absolute addressing.