Nintendo 8 Bit Manual

							 
 
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Figure 2-3. CPU memory map. 
 
2.3 Registers 
 
The 6502 has fewer registers than similar processors. There are three special purpose 
registers, the program counter, stack pointer and status register which each have a specific 
use. It also has three general purpose registers, the accumulator and the index registers, X 
and Y, which can be used to store data or control information temporarily. 
 
2.3.1 Program Counter (PC) 
 
The program counter is a 16-bit register which holds the address of the next instruction to be 
executed. As instructions are executed, the value of the program counter is updated, usually 
moving on to the next instruction in the sequence. The value can be affected by branch and 
jump instructions, procedure calls and interrupts. 
 
2.3.2 Stack Pointer (SP) 
  
						

							 
 
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The stack is located at memory locations $0100-$01FF. The stack pointer is an 8-bit register 
which serves as an offset from $0100. The stack works top-down, so when a byte is pushed 
on to the stack, the stack pointer is decremented and when a byte is pulled from the stack, 
the stack pointer is incremented. There is no detection of stack overflow and the stack 
pointer will just wrap around from $00 to $FF. 
 
2.3.3 Accumulator (A) 
 
The accumulator is an 8-bit register which stores the results of arithmetic and logic 
operations. The accumulator can also be set to a value retrieved from memory. 
 
2.3.4 Index Register X (X) 
 
The X register is an 8-bit register typically used as a counter or an offset for certain 
addressing modes. The X register can be set to a value retrieved from memory and can be 
used to get or set the value of the stack pointer. 
 
2.2.5 Index Register Y (Y) 
 
The Y register is an 8-bit register which is used in the same way as the X register, as a 
counter or to store an offset. Unlike the X register, the Y register cannot affect the stack 
pointer. 
 
2.3.6 Processor Status (P) 
 
The status register contains a number of single bit flags which are set or cleared when 
instructions are executed. 
 
•  Carry Flag (C) - The carry flag is set if the last instruction resulted in an overflow from bit 
7 or an underflow from bit 0. For example performing 255 + 1 would result in an answer 
of 0 with the carry bit set. This allows the system to perform calculations on numbers 
longer than 8-bits by performing the calculation on the first byte, storing the carry and 
then using that carry when performing the calculation on the second byte. The carry flag 
can be set by the SEC (Set Carry Flag) instruction and cleared by the CLC (Clear Carry 
Flag) instruction. 
•  Zero Flag (Z) - The zero flag is set if the result of the last instruction was zero. So for 
example 128 - 127 does not set the zero flag, whereas 128 - 128 does. 
•  Interrupt Disable (I) - The interrupt disable flag can be used to prevent the system 
responding to IRQs. It is set by the SEI (Set Interrupt Disable) instruction and IRQs will 
then be ignored until execution of a CLI (Clear Interrupt Disable) instruction. 
•  Decimal Mode (D) - The decimal mode flag is used to switch the 6502 into BCD mode. 
However the 2A03 does not support BCD mode so although the flag can be set, its value 
will be ignored. This flag can be set SED (Set Decimal Flag) instruction and cleared by 
CLD (Clear Decimal Flag). 
•  Break Command (B) - The break command flag is used to indicate that a BRK (Break) 
instruction has been executed, causing an IRQ. 
•  Overflow Flag (V) - The overflow flag is set if an invalid two’s complement result was 
obtained by the previous instruction. This means that a negative result has been obtained 
when a positive one was expected or vice versa. For example, adding two positive 
numbers should give a positive answer. However 64 + 64 gives the result -128 due to the 
sign bit. Therefore the overflow flag would be set. The overflow flag is determined by 
taking the exclusive-or of the carry from between bits 6 and 7 and between bit 7 and the 
carry flag [29]. An explanation of two’s complement can be found in Appendix A.  
						

							 
 
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•  Negative Flag (N) - Bit 7 of a byte represents the sign of that byte, with 0 being positive 
and 1 being negative. The negative flag (also known as the sign flag) is set if this sign bit 
is 1. 
 
The flags are arranged in the status register in the order shown in figure 2-3. Bit 5 of the 
status register is unused. 
 
 
 
Figure 2-4. Status register layout. 
 
2.4 Interrupts 
 
Interrupts prevent the standard sequential execution of code and cause the processor to 
attend to the interrupt. Interrupts are usually generated by hardware which requires attention, 
but can be triggered by software. The NES has three different types of interrupt, NMI, IRQ 
and reset. The addresses to jump to when an interrupt occurs are stored in a vector table in 
the program code at $FFFA-$FFFF. When an interrupt occurs the system performs the 
following actions [30]: 
 
1.  Recognize interrupt request has occurred. 
2.  Complete execution of the current instruction. 
3.  Push the program counter and status register on to the stack. 
4.  Set the interrupt disable flag to prevent further interrupts. 
5.  Load the address of the interrupt handling routine from the vector table into the program 
counter. 
6.  Execute the interrupt handling routine. 
7.  After executing a RTI (Return From Interrupt) instruction, pull the program counter and 
status register values from the stack. 
8.  Resume execution of the program. 
 
IRQs, or maskable interrupts, are generated by certain memory mappers. They are ignored 
by the processor if the interrupt disable flag is set. IRQs can be triggered by the software by 
use of the BRK (Break) instruction. When an IRQ occurs the system jumps to the address 
located at $FFFE and $FFFF. 
 
NMI (Non-Maskable Interrupt) is the type of interrupt generated by the PPU when V-Blank 
occurs at the end of each frame. NMIs are not affected by the interrupt disable bit in the 
status register, so execution is always interrupted when they occur [31]. However, triggering 
of a NMI can be prevented if bit 7 of PPU Control Register 1 ($2000) is clear. When a NMI 
occurs the system jumps to the address located at $FFFA and $FFFB. The handling of NMIs 
is shown in figure 2-4. 
 
Reset interrupts are triggered when the system first starts and when the user presses the 
reset button. When a reset occurs the system jumps to the address located at $FFFC and 
$FFFD. 
 
The system gives the highest priority to reset requests, followed by NMI and finally IRQ [7]. 
The NES has an interrupt latency of 7 cycles, which means it takes 7 CPU cycles to begin 
executing the interrupt handler. 
  
						

							 
 
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Figure 2-5. NMI (Non-Maskable Interrupt) handling. 
 
2.5 Addressing Modes 
 
The 6502 has several different addressing modes, providing different ways to access 
memory locations. There are also addressing modes which operate on the contents of 
registers, rather than memory. In total there are 13 different addressing modes on the 6502. 
Some instructions can use more than one different addressing mode. Details on the available 
addressing modes can be found in Appendix E. 
 
2.6 Instructions 
 
The 6502 has 56 different instructions although some come in multiple variations using 
different addressing modes, making a total of 151 valid opcodes (operation codes) out of a 
possible 256. A detailed explanation of the complete instruction set can be found in [2], [29] 
and [32]. Instructions are either one, two or three bytes long, depending on the addressing 
mode. The first byte is the opcode and the remaining bytes are the operands. Instructions fit 
into several functional groups [3]: 
 
•  Load / Store Operations - Load a register from memory or stores the contents of a 
register to memory. 
•  Register Transfer Operations - Copy contents of X or Y register to the accumulator or 
copy contents of accumulator to X or Y register. 
•  Stack Operations - Push or pull the stack or manipulate stack pointer using X register. 
•  Logical Operations - Perform logical operations on the accumulator and a value stored in 
memory. 
•  Arithmetic Operations - Perform arithmetic operations on registers and memory. 
•  Increments / Decrements - Increment or decrement the X or Y registers or a value stored 
in memory. 
•  Shifts - Shift the bits of either the accumulator or a memory location one bit to the left or 
right.  
						

							 
 
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•  Jumps / Calls - Break sequential execution sequence, resuming from a specified 
address. 
•  Branches - Break sequential execution sequence, resuming from a specified address, if a 
condition is met. The condition involves examining a specific bit in the status register. 
•  Status Register Operations - Set or clear a flag in the status register. 
•  System Functions - Perform rarely used functions. 
 
 
  
						

							 
 
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3 - Picture Processing Unit 
 
3.1 2C02 Overview 
 
Ricoh also supplied the 2C02 to serve as PPU. The PPU’s registers are mostly located in the 
I/O registers section of CPU memory at $2000-$2007 and $4014 as described in Appendix 
B. In addition, there are some special registers used for screen scrolling. 
 
3.2 PPU Memory Map  
 
The PPU has its own memory, known as VRAM (Video RAM). Like the CPU, the PPU can 
also address 64 KB of memory although it only has 16 KB of physical RAM. The PPU’s 
memory map is shown in figure 3-1. Again, the left hand map shows a simplified version 
which is elaborated on by the right hand map. Due to the difference between physical and 
logical address spaces, any address above $3FFF is wrapped around, making the logical 
memory locations $4000-$FFFF effectively a mirror of locations $0000-$3FFF. 
 
Reading from and writing to PPU memory can be done by using the I/O registers $2006 and 
$2007 in CPU memory. This is usually done during V-Blank at the end of a frame, as it 
affects addresses used while drawing the screen and can therefore corrupt what is 
displayed. However, this effect can be used to produce split screen effects. 
 
Since PPU memory uses 16-bit addresses but I/O registers are only 8-bit, two writes to 
$2006 are required to set the address required. Data can then be read from or written to 
$2007. After each write to $2007, the address is incremented by either 1 or 32 as dictated by 
bit 2 of $2000. The first read from $2007 is invalid and the data will actually be buffered and 
returned on the next read. This does not apply to colour palettes. 
 
The PPU also has a separate 256 byte area of memory, SPR-RAM (Sprite RAM), to store 
the sprite attributes. The sprites themselves can be found in the pattern tables.  
						

							 
 
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$0000
$2000
$3F00
$4000
$10000
Pattern Table 0 Pattern Table 1Mirrors
$3F00-$3F1F
Sprite Palette
Image Palette
Mirrors
$2000-$2EFF
Attribute Table 3
Name Table 3
Attribute Table 2
Name Table 2Mirrors
$0000-$3FFF
Attribute Table 1
Name Table 1
Attribute Table 0
Name Table 0
$0000
$1000
$2000
$23C0
$2400
$27C0
$2800
$2BC0
$2C00
$2FC0
$3000
$3F00
$3F10
$3F20
$4000
$10000
Name Tables
Palettes
Mirrors
$0000-$3FFF
Pattern Tables
 
Figure 3-1. PPU memory map. 
 
3.3 PPU Registers 
 
Communication between the CPU and other devices takes place via memory mapped I/O 
registers. The registers used by the PPU are located in main memory at $2000-$2007 with 
an additional register used for Direct Memory Access at $4014. Remember that locations 
$2000-$2007 are mirrored every 8 bytes in the region $2008-$3FFF. A summary of all I/O 
registers can be found in Appendix B. 
 
The actions of the PPU can be controlled by the CPU by writing to $2000 and $2001, known 
as PPU Control Register 1 and PPU Control Register 2 respectively. Both registers should  
						

							 
 
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only be written to. Bit 7 of £2000 can be used to disable NMIs. Remember that this type of 
interrupt is generated whenever a V-Blank occurs and is unaffected by the interrupt disable 
flag of the status register. Clearing this bit will prevent an NMI from occurring on V-Blank. 
Since the NES supports both 8x8 and 8x16 sprites, setting bit 5 of $2000 will switch to 8x16 
sprites. The next address in PPU memory to read or write from will be incremented after 
each I/O occurs. The value to increment by is adjusted by setting the value of bit 2 of $2000. 
If this is clear, the address is incremented by 1 (horizontal), otherwise the increment is 32 
(vertical). Using $2001, the background can be hidden by clearing bit 3 and, similarly, the 
sprites can be hidden by clearing bit 4. 
 
The PPU Status Register is located at $2002 and is read only. The register is used by the 
PPU to report its status to the CPU. The programs will frequently cause the CPU to read 
from this location in order to ascertain the PPU’s status. Bit 7 is set by the PPU to indicate 
that V-Blank is occurring. Bit 6 and bit 7 relate to sprites and are described later. Bit 4 
indicates whether the PPU is willing to accept writes to VRAM, if it clear then writes are 
ignored. When a read from $2002 occurs, bit 7 is reset to 0 as are $2005 and $2006. 
 
3.3.1 Direct Memory Access 
 
When transferring a large amount of data between devices it is inefficient to transfer this 
through the processor. To transfer data from CPU memory to sprite memory, for example, 
takes the following steps: 
 
1.  Load required SPR-RAM address into CPU. 
2.  Write required SPR-RAM address to $2003. 
3.  Load byte into CPU. 
4.  Write byte to $2004. 
 
When filling the contents of sprite memory, this technique would have to be repeated 256 
times. Direct Memory Access (DMA) is a technique which allows more efficient copying of 
data from CPU memory to sprite memory. Using DMA, the whole of sprite memory can be 
filled by using a single instruction, a write to $4014. The starting address in CPU memory is 
specified by the operand for the write multiplied by $100. The 256 bytes starting at this 
address are copied directly into sprite memory without the further involvement of the CPU. 
 
When the DMA is occurring, the memory bus is in use, preventing the CPU from accessing 
memory and, therefore, preventing it from accessing any more instructions. This is referred 
to as cycle stealing and the CPU has to wait until the DMA transfer is complete. On the NES, 
the DMA takes the equivalent of 512 cycles (about 4.5 scanlines worth) after which the CPU 
can resume. This is considerably less than would be required to copy manually through the 
CPU. 
 
3.4 Colour Palette 
 
The NES has a colour palette containing 52 colours although there is actually room for 64. 
However, not all of these can be displayed at a given time. The NES uses two palettes, each 
with 16 entries, the image palette ($3F00-$3F0F) and the sprite palette ($3F10-$3F1F). The 
image palette shows the colours currently available for background tiles. The sprite palette 
shows the colours currently available for sprites. These palettes do not store the actual 
colour values but rather the index of the colour in the system palette. Since only 64 unique 
values are needed, bits 6 and 7 can be ignored. 
 
The palette entry at $3F00 is the background colour and is used for transparency. Mirroring 
is used so that every four bytes in the palettes is a copy of $3F00. Therefore $3F04, $3F08, 
$3F0C, $3F10, $3F14, $3F18 and $3F1C are just copies of $3F00 and the total number of  
						

							 
 
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colours in each palette is 13, not 16 [5]. The total number of colours onscreen at any time is 
therefore 25 out of 52. Both palettes are also mirrored to $3F20-$3FFF. The colour palette is 
shown in Appendix F. 
 
3.5 Pattern Tables 
 
The NES has two pattern tables at $0000 and $1000. The pattern tables store the 8x8 pixel 
tiles which can be drawn on the screen. Many games store the pattern tables in CHR-ROM 
on the cartridge, however, games without CHR-ROM will use RAM for the pattern tables and 
fill them during execution. The pattern tables store the least significant two bits of the 4-bit 
number needed to identify the image or sprite palette entry used by that pixel such that 00b 
is palette entry 0, 01b is 1, 10b is 2 and 11b is 3. 
 
 
 
Figure 3-2. Pattern tables. Adapted from [7]. 
 
Figure 3-2 shows how the pattern tables work. The character ‘A’ is the final result, shown at 
the bottom. The character is constructed pixel by pixel by taking one bit from the top left and 
one from the top right to make a 2-bit colour. The other two bits of the colour are taken from 
the attribute tables. The colours shown are not genuine NES colour palette values. 
 
3.6 Name Tables / Attribute Tables 
 
Name tables are essentially a matrix of tile numbers, pointing to the tiles stored in the pattern 
tables. The name tables are 32x30 tiles and since each tile is 8x8 pixels, the entire name 
table is 256x240 pixels. 
 
Each name table has an associated attribute table. Attribute tables hold the upper two bits of 
the colours for the tiles. Each byte in the attribute table represents a 4x4 group of tiles, so an 
attribute table is an 8x8 table of these groups. Each 4x4 group is further divided into four 2x2 
squares as shown in figure 3-3 [9]. The 8x8 tiles are numbered $0-$F. The layout of the byte  
						

							 
 
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is 33221100 where every two bits specifies the most significant two colour bits for the 
specified square. 
 
Square 0
$0 $1
$2 $3Square 1
$4 $5
$6 $7
Square 2
$8 $9
$A $BSquare 3
$C $D
$E $F
 
 
Figure 3-3. 4x4 tile group layout. Adapted from [20]. 
 
The NES only has 2 KB to store name tables and attribute tables, allowing it to store two of 
each. However it can address up to four of each. Mirroring is used to allow it to do this. There 
are four types of mirroring which are described below, using abbreviations for logical name 
tables (those that can be addressed), L1 at $2000, L2 at $2400, L3 at $2800 and L4 at 
$2C00: 
 
•  Horizontal mirroring maps L1 and L2 to the first physical name table and L3 and L4 to the 
second as shown in figure 3-4. 
 
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Figure 3-4. Horizontal mirroring. 
 
•  Vertical mirroring maps L1 and L3 to the first physical name table and L2 and L4 to the 
second as shown in figure 3-5. 
 
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Figure 3-5. Vertical mirroring.