Motorola Radio Mcs2000 Vol 1 68p81083c20 A Manual

							 
Controller Section Theory of Operation 7-9  
that is approximately equal to the voltage present at the inverting input 
during the maximum current voltage drop through R5612.
PA control voltage limit consists of a portion of the control voltage fed back to 
the power control loop. PA_CNTL_LIM is produced by a voltage divider 
network on the PA board. When PA_CNTL_LIM goes above the reference 
voltage of 4.65 V plus one diode voltage drop (i.e. 0.7 V) then protection 
begins. At this point the control voltage PA_CNTL is clamped. This protects 
the PA from being driven too hard by PA_CNTL which could cause excessively 
high output power 
Interfacing 
(Refer to ÒClock Distribution Block DiagramÓ on page 7-10, and Interface 
schematic page 10-24 for general reference) 
Microprocessor 
Clock Synthesizer 
(Refer to ASFIC schematic page 10-23 for reference) 
The clock source for the microprocessor system is generated by the ASFIC 
(U0200). Upon power-up the reference oscillator U5800 (Pendulum) provides 
a 16.8 MHz reference. Based on this reference the synthesizer (U5801) 
generates a 2.1 MHz waveform that is routed from the RF section (via C0403) 
to the ASFIC (on U0200-E1) and the option connectors (J0401-3 and J0408-3). 
At the option connectors the 2.1 MHz may be used as a reference for any 
option boards that are attached. For the main board controller the ASFIC uses 
2.1 MHz as a reference input clock signal for its internal synthesizer. The 
ASFIC, in addition to audio circuitry, has a programmable synthesizer which 
can generate a synthesized signal ranging from 1200 Hz to 32.769 MHz in 
1200 Hz steps.
When power is Þrst applied, the ASFIC will generate its default 3.6864 MHz 
CMOS square wave  
m  
P CLK (on U0200-D1) and this is routed to the 
microprocessor (U0103-36/U0003-E3) and SLIC (U0104-A3). After the 
microprocessor starts operation, it reprograms the ASFIC clock synthesizer to 
a higher  
m 
P CLK frequency (usually 7.3728 or 14.7456 MHz) and continues 
operation.
The ASFIC synthesizer loop uses C0208, C0209 and R0204 to set the switching 
time and jitter of the clock output. If the synthesizer cannot generate the 
required clock frequency it will switch back to its default 3.6864 MHz output.
Because the ASFIC synthesizer and the  
m  
P system will not operate without the 
2.1 MHz reference clock it (and the voltage regulators) should be checked Þrst 
in debugging the system. 
Serial Peripheral 
Interface (SPI) 
(Refer to Controller schematic page 10-19 for reference) 
The  
m 
P communicates to many of the ICs through its SPI port. This port 
consists of SPI TX DATA (U0103-66/U0003-B2), SPI RX DATA (U0103-65/
U0003-B1), CLK (U0103-67/U0003-A2) and chip select lines going to the 
various ICs, connected on the SPI PORT (BUS). This BUS is a synchronous bus, 
in that the timing clock signal CLK is sent while SPI data (SPI TX DATA or SPI 
RX DATA) is sent. Therefore, whenever there is activity on either SPI TX DATA 
or SPI RX DATA there should be a uniform signal on CLK. The SPI TX DATA is 
used to send serial from a  
m  
P to a device, and SPI RX DATA is used to send data 
from a device to a  
m 
P. 
						

							 
7-10 Controller Section Theory of Operation 
  
Figure 7-1   Clock Distribution Block Diagram 
On the controller there are 2 ICs on the SPI BUS, ASFIC (U0200-F2) and D/A 
(U0551-6). In the UHF and VHF RF sections there are 3 ICs on the SPI BUS, ZIF 
(U3201-21), Pendulum (Reference Oscillator U5800-23) and FRAC/N (U5801-
4). For the 800 and 900 MHz radios the 3 ICs on the SPI BUS are: ZIF (U6201), 
Pendulum (Reference Oscillator U6704) and FRAC/N (U6702). The SPI TX 
DATA and CLK lines going to the RF section are Þltered by R0403 and R0404 
to minimize noise.
There are 2 chip select lines going to each of the 2 Option boards (J0401-21 
and J0401-23  
/ 
and J0408-21 and J0408-23).
When the  
m 
P needs to program any of these ICs it brings the chip select line 
for that IC to a logic 0 and then sends the proper data and clock signals. The 
amount of data sent to the various ICs are different, for example the ASFIC can 
receive up to 21 bytes (168 bits) while the ZIF can receive up to 5 bytes (40 
bits). After the data has been sent the chip select line is returned to a logic 1.
The Option board interfaces are different in that the  
m  
P can also read data back 
from devices connected. Two additional interrupt lines are provided to each of 
the 2 option boards ASN INT (J0401-22 and J0408-22) and JABBA INT(J0401-
20 J0408-20) are provided to allow an option to signal the  
m  
P that there is data 
to transfer.
PENDULUM
QUARTZ
CRYSTAL
16.8 MHZFRACTIONAL DIVISION SYNTHESIZER
ELECTRONIC CLOCK GENERATION
2.1 MHz
ZERO I.F.
SPI-CLOCKSPI-CLOCK
AUDIO SIGNALLING FILTER IC
ELECTRONIC CLOCK GENERATION,
PROGRAMMABLE RANGE:
1200 Hz to 32.769 MHz (1200 Hz STEPS)
68HC11K4 uP
D/A MC68HC11F1 MICRO
CONTROLLER
ELECTRONIC GENERATION 
OF E AND SPI CLOCKS
F REF OUT
E-CLOCK
SPI-CLOCK
TRANSCEIVER
CONTROLLER
SLIC IVa OR 
SLIC V(not placed in
this application) uP-CLOCK 
						

							 
Controller Section Theory of Operation 7-11 
The timing and operation of this interface is speciÞc to the option connected, 
but generally follows the pattern 1) an option board device generates the 
interrupt, 2) main board asserts a chip for that option board device, 3) the 
main board  
m 
P generates the CLK, and 4) when data transfer is complete the 
main board terminates the chip select and CLK activity. Typical Data rate for 
the SPI BUS is 1 Megabit/sec. 
SB9600 Serial 
Interface 
(Refer to schematics on page 10-27 and 10-19 for reference and to SB9600 BUSY 
SimpliÞed Schematic on page 9-27) 
The SB9600 serial interface allows the radio to communicate with external 
radio options (like a control head) and Radio Service Software (RSS). This 
interface connects to both the Control Head connector (J0405) and the 
Accessory connector (J0403) and comprises BUS+ (J0405-15/J0403-6), BUS- 
(J0405-4/J0403-18), BUSY (J0405-14/J0403-5) and RESET (J0405-3/J0403-17). 
All of these lines are bidirectional, meaning that either the radio or an option 
can drive the line.
When the radio needs to send a message (for example to update the Control 
Head display) it Þrst checks BUSY IN (U0103-76/U0003-A4) to make sure the 
interface is not currently being used. If this input is a logic 1 the interface is 
available and the  
m 
P will change BUSY OUT (U0104-G4/U0003-29) to a logic 
0. This drives the BUSY line to a logic 1 through buffer transistor Q0406 
informing the radio and all connected devices that a data transmission is 
starting.
The radioÕs  
m 
P then starts sending serial data on SCI TX (U0103-64/U0003- 83). 
This data is buffered by Q0402 and drives the differential bus signals (BUS+/
BUS-) through Q0401 and Q0400. The BUS+ line normally sits at +5 volts 
because of pull-up resistor R0407. The BUS- line normally sits at 0 Volts 
because of pull-down resistor R0412.
While the radio is sending serial data on SCI TX it receives an ÒechoÓ of the 
same data on the SCI RX (U0103-63/U0003-82) line. The BUS-, BUS+ lines go 
to U0401 which acts as a comparator. When the BUS+ voltage is greater than 
the BUS- voltage the output (at U0401-7) is a logic 1. If it is less, the output is 
a logic 0. This is routed through U0105 to  
m 
P (U0103). Note that the SCI 
SELECT input to U0105-11 is at a logic 1 to allow the routing to the controller 
on BUS SCI (U0105- 13).
A total of 5 bytes of data are sent for each standard message. After the data is 
sent the BUSY line is released to its default state (a logic 0). Other devices are 
now free to use the interface to send data.
The same method of operation occurs when an option sends data to the radio 
on this interface. The data is received through U0401 and U0105 (or R0020/
R0021) to the SCI RX input of the  
m 
P.  
The sender receives back an ÒechoÓ of each byte and compares this to what 
was sent. If the echo does not agree then the transmission is repeated at a later 
time.
If excessive transmission errors occur, the  
m 
P will reset the interface by setting 
the RESET OUT (U0104-B7/U0003-43) line to a logic 0. This drives the RESET 
line to a logic 1 through buffer transistor Q0408 resetting all SCI devices 
connected. 
						

							 
7-12 Controller Section Theory of Operation 
An option can reset the radio by driving the LH RESET line to a logic 1. This 
gets buffered by Q0409 and Q0425 and goes to the reset input of SLIC (U0104-
A8). This then causes the reset input of the  
m 
P (U0103-50) RESET to go to a 
logic 0 resulting in the  
m 
P restarting operation. 
General Purpose 
Input/Output 
(Refer to IO Buffers schematic page 10-28 for reference) 
Five general purpose I/O lines (GP I/O 2 through GP I/O 6) are provided to 
interface to external options. Each of these lines is conÞgured under software 
control to be either an input or an Òopen collectorÓ output. To make an I/O 
line an input the corresponding output line is set to a logic 0; for example to 
make GP I/O 6 (J0403-7) an input pin, OUT 6 (U0104-K8/U0003 
-  
24) is set to a 
logic 0. This turns off Q0423 and allows an external device to either turn on 
or off Q0424 which is sensed by U0104-H2/U0003-36 IN6/RTSB.
The GP I/O 2 line is different to the other 4 GP I/O lines. The output transistor 
(Q0425) can drive an external relay (HLN4435 or similar) for use with the 
vehicle horn or lights. This can also drive a non relay device, but the device 
must be designed to take a SW B+ input.
Selected GP I/O lines have secondary functions. If the line is used for the 
secondary function then it can not be used as an I/O line. The following 
secondary functions are supported (not all radio models support the RS-232 
function, refer to the description for your radio).
The 470 pF and 10 nF capacitors serve to Þlter out any AC noise which may 
ride on the GPIO lines. 
Microprocesso
r Operation 
(Refer to schematic 
page 10-19 for 
reference) 
For this radio, the  
m 
P, U0103, is conÞgured to operate in one of two modes, 
expanded and bootstrap. In expanded mode the  
m 
P uses external memory 
devices to operate, whereas in bootstrap operation the  
m 
P uses only its internal 
memory. In normal operation of the radio the  
m 
P is operating in expanded 
mode as described below. See ÒBootstrap Microprocessor OperationÓ on 
page 7-16 for bootstrap information. 
Table 7-2    Secondary I/O Functions 
I/O line Standard VRM500 VRM100 Alternate Flashport 
GP I/O 2 Horn/Lights Horn/Lights Horn/Lights External 
Alarm Outn/a
GP I/O 3 PTT Data PTT Data PTT n/a Bootstrap Vpp 
GP I/O 4 Not Used Not used Data Mode 
Request 
(Modem)RS-232 
TX DataBootstrap Data
GP I/O 5 Car Radio 
MuteNot used Transmit 
Enable 
(Modem)RS-232
CTSn/a
GP I/O 6 Hub-Monitor Not used Channel 
Grant 
(Modem)RS-232
RTSn/a 
						

							 
Controller Section Theory of Operation 7-13 
Normal 
(=Expanded) 
Microprocessor 
Operation 
In expanded mode on this radio, the  
m 
P has access to 3 external memory 
devices; U0100 (EEPROM), U0101 (SRAM) U0102 (FLASH EEPROM). In 
addition the  
m 
P has access to U0104 (SLIC). Also, within the  
m 
P there are 1 
Kbytes of internal RAM and 512 
  
bytes of internal EEPROM, as well as logic to 
select external memory devices.
The external EEPROM (U0100) as well as the  
m 
PÕs own internal EEPROM space 
contain the information in the radio which is customer speciÞc, referred to as 
the codeplug. This information consists of items such as: 1)what band the 
radio operates in, 2)what frequencies are assigned to what channel, and 3) 
tuning information. In general, tuning information and other more 
frequently accessed items are stored in the internal EEPROM (space within the 
68HC11F1), while the remaining data is stored in the external EEPROM. (See 
the particular device subsection for more details.)
The external SRAM (U0101) as well as the  
m 
PÕs own internal RAM space are 
used for temporary calculations required by the software during execution. All 
of the data stored in both of these locations is lost when the radio powers off 
(See the particular device subsection for more details).
The FLASH EEPROM (U0102) contains the actual Radio Operating Software. 
This software is common to all radios within a given model type. For example 
Securenet radios may have a different version of software in the FLASH ROM 
than a non-secure radio (See the particular device subsection for more details).
The  
m 
P provides an address bus of 16 address lines (A0-A15), and a data bus of 
8 data lines (D0-D7). There are also 5 control lines; CSPROG (U0103-53), 
CSGEN (U0103-54), CSI01 (U0103-55), E CLK (U0103-34), and RWBIN 
(U0103-35). CSPROG and CSI01 are used to chip select the SLIC, CSGEN is 
used to chip select the SRAM. E CLK and RWBIN are used to generate the 
proper timed control signals to the memory devices. E CLK is generated by the 
microprocessor based on  
m 
P CLK and is always 1/4 the frequency of  
m 
P CLK, 
e.g. if  
m 
P CLK is 7.3728 MHz, then E CLK will be 1.8432 MHz.
When the  
m 
P is functioning normally, the address and data lines should be 
toggling at CMOS logic levels. SpeciÞcally, the logic high levels should be 
between 4.8 and 5.0  V, and the logic low levels should be between 0 and 0.2  V. 
No other intermediate levels should be observed, and the rise and fall times 
should be 
						

							 
7-14 Controller Section Theory of Operation 
running, this signal is an open-drain CMOS output which goes low whenever 
the  
m 
P begins a new instruction (an instruction typically requires 2-4 external 
bus cycles, or memory fetches). However, since it is an open-drain output, the 
waveform rise assumes an exponential shape similar to an RC circuit.
There are 8 analog to digital converter ports (A/D) on U0103. They are labelled 
within the device block as PE0-PE7. These lines sense the voltage level ranging 
from 0 to 5 V of the input line and convert that level to a number ranging 
from 0 to 255 which can be read by the software to take appropriate action. 
For example U0103-23 is the battery voltage detect line. R0417 and R0416 
form a resistor divider on SWB+. With 68K and 22K and a voltage range of 11  V 
to 17 V, that A/D port would see 2.68 V to 4.15 V which would then be 
converted to ~136 to 211 respectively.
U0103-30 is the high reference voltage for the A/D ports on the  
m 
P. Resistor 
R0112 and capacitor C0104 Þlter the +5 V reference. If this voltage is lower 
than +5 V the A/D readings will be incorrect. Likewise U0103-29 is the low 
reference for the A/D ports. This line is normally tied to ground. If this line is 
not connected to ground, the A/D readings will be incorrect.
Capacitor C0105 serves to Þlter out any AC noise which may ride on +5V at 
U0103. 
Support Logic IC 
(SLIC) 
The SLIC (U0104) provides 3 primary functions, I/O port expansion, memory 
address expansion, and some signalling decoding.
There are 32 I/O lines within the SLIC which are under  
m 
P control. They are 
grouped in 4 blocks of 8 and labelled as SLIC ports H, J, K, and L. Ports J, K, 
and L each have a DDR memory register and a ÒvalueÓ register. Port H only has 
a ÒvalueÓ register. These ports are accessed by the mP by placing the correct 
address for the I/O registers on the address bus and either reading or writing 
the data on the data bus. Changing bits in the DDR registers conÞgures speciÞc 
port bits to be either input sensors or output drivers. The ÒvalueÓ registers 
either report the state of the sensed input or provide the logic level to be 
driven on a line conÞgured as an output.
Since the 68HC11F1 only has 16 address lines (A0-A15), it can only directly 
address 64 Kbytes(=2^16) of external memory. The radio architecture is 
designed to accommodate over 2 Mbytes of memory. The SLIC contains logic 
which allows addressing of the memory which would otherwise be 
unavailable to the mP on its own. The SLIC monitors address lines A0, A1, A2, 
A3, A4, A14, and A15. Depending on what combinations appear on those 
lines, the SLIC may or may not assist the mP with addressing. When the mP is 
addressing a device on its own then address lines A0-A15 are used and valid. 
If instead the SLIC is assisting with the addressing then address lines A0-A13 
from the mP are valid, but the upper order address lines A14 OUT, A15 OUT, 
A16, A17, A18, and if necessary A19 are provided from the SLIC. There is no 
conßict with A14 and A14 OUT or with A15 and A15 OUT. Notice for example 
that SRAM U0101 uses A14 meaning that line is always provided from the mP 
directly. Notice also that EEPROM U0100 and FLASH ROM U0102 use A14 
OUT, meaning that their address lines come from the SLIC. On the SLIC itself, 
line A14 going to A14IN and A15 going to A15IN are address input lines TO 
the SLIC. Whereas A14 OUT and A15 OUT are address output lines FROM the 
SLIC.
The SLIC also generates chip select signals UV CS for U0102 and EE CS for 
U0101, as well as memory timing signals MEMRWB and OE. 
						

							Controller Section Theory of Operation 7-15 The circuitry in the SLIC is reset when either the RESET IN (U0104-A8) is a 
logic 1, or RESET* (U0104-E4) is a logic 0, or PWR RST is a logic 0. These lines 
must be in the opposite logic state for the SLIC to function normally.
The SLIC supports hardware signalling decoding for certain signalling 
standards such as MPT 1327 and Trunking (OSW). There are different versions 
of SLIC each having a different decoder. Currently there are no SLIC devices 
which have more than 1 decoder.
The incoming data received by the radio and Þltered by the ASFIC exits the 
ASFIC at U0200-G4 RX DATA, and enters the SLIC at U0104-B6. Based on the 
data the SLIC updates internal status registers which the mP can read using the 
address and data bus, and act upon it.
Notice that RX data also goes to U0103-77/U0003-C5. This implies that the 
radio can be conÞgured to perform software decoding if desired, even if the 
radio has a SLIC with a hardware decoder in it.
Capacitor C0108 serves to Þlter out any AC noise which may ride on +5V at 
U0104.
FLASH Electrically 
Erasable 
Programmable 
Memory (FLASH 
EEPROM)The FLASH EEPROM (U0106) contains the radioÕs operating software. This 
software is common to all radios within a given model type. For example 
Securenet radios may have a different version of software in the FLASH ROM 
than a non-secure radio. This is, as opposed to the codeplug information 
stored in EEPROM (U0100) which could be different from one user to another 
in the same company.
In normal operating mode, this memory is only read, not written to. In 
bootstrap mode the Vpp pin (U0106-11) is brought to 12  V to allow the device 
to be written to. The memory access signals (UV CS, OE and MEMRWB) are 
generated by the SLIC. To upgrade/reprogram the FLASH software, the mP must 
be set in bootstrap operating mode, and the FLASH device pin (U0106-11) Vpp 
must be between 11.4 and 12.6 V.
Taking diode CR0105 into account, the voltage at J0403-21 to enable FLASH 
programming may range between 12.1 and 13.1  V. Resistor divider pair R0104 
and R0105 set up 4.1 V on U0106-11 which reduces the chance of logic 
transitions on I/O3 used as a GPIO from affecting the FLASH Vpp port. The 
FLASH device may be reprogrammed 1,000 times without issue. It is not 
recommended to reprogram the FLASH device at a temperature below 0°C.
(See ÒBootstrap Microprocessor OperationÓ on page  7-16 for further details on 
reprogramming of the FLASH EEPROM)
Capacitor C0102 serves to Þlter out any AC noise which may ride on +5V at 
U0102, and C0107 Þlters out any AC noise on Vpp.
Electrically 
Erasable 
Programmable 
Memory (EEPROM)The EEPROM (U0100) contains the radioÕs operating parameters such as 
operating frequency and signalling features, commonly know as the codeplug. 
It is also used to store radio operating state parameters such as current mode 
and volume. U0100 is a 32 Kbyte device. This memory can be written to in 
excess of 100,000 times and will retain the data when power is removed from 
the radio. The memory access signals (EE CS, OE and MEMRWB) are generated 
by the SLIC. 
						

							7-16 Controller Section Theory of OperationAdditional EEPROM is contained in the mP (U0103). This EEPROM is used to 
store radio tuning and alignment data. Like the external EEPROM this 
memory can be programmed multiple times and will retain the data when 
power is removed from the radio. 
Note: the external EEPROM plus the 512 bytes of internal EEPROM in the 
68HC11F1 comprise the complete codeplug.
Static Random 
Access Memory 
(SRAM)The SRAM (U0101) contains temporary radio calculations or parameters that 
can change very frequently, and which are generated and stored by the 
software during its normal operation. The information is lost when the radio 
is turned off. The device allows an unlimited number of write cycles. SRAM 
accesses are indicated by the CSGEN signal U101-20 (which comes from 
U0103-54) going low. U0101 is commonly referred to as the external RAM as 
opposed to the internal RAM which is the 1 K (1024) bytes of RAM which is 
part of the mP. Both RAM spaces serve the purpose. However, the internal RAM 
is used for the calculated values which are accessed most often.
Resistors R0100, R0101, and R0102 allow the board to be conÞgured to accept 
either an 8 K or 32 K byte EEPROM. For a 32 K device, R0100 is placed, and 
R0102 and R0101 are NOT placed. For an 8 K device R0100 is NOT placed, and 
R0102 and R0101 are placed.
Capacitor C0100 serves to Þlter out any ac noise which may ride on +5 V at 
U0101
Bootstrap 
Microprocessor 
Operation The bootstrap mode of operation is only used to load new software into the 
FLASH EEPROM (U0106 or U0102). The MODA (U0103-33) and MODB 
(U0103-32) inputs must be a logic 0 when the microprocessor comes out of 
reset. The microprocessor will wait to receive data on its SCI RX (U0103-63) 
line and as data is received, it will be echoed on the SCI TX (U0103-64) line. 
For example, when the Smart RIB (SRIB) is used to load new software into the 
FLASH EEPROM, the signals to the microprocessor are automatically 
controlled by the SRIB to enter this mode. First the SRIB brings the SCI RX 
DATA (J0403-19) above 12 volts. This turns on dual transistor Q0103 to bring 
the MODA and MODB lines and the SCI SELECT line to a logic 0. The SRIB 
then releases the LH RESET (J0403-17) line and begins transferring the data to 
the radio. Data from the SRIB goes to GP I/O 4 (J0403-20) and data to the SRIB 
comes from the BUS+ and BUS- lines (J0403-6 and J0403-18). After an initial 
data transfer, the SRIB will bring the Vpp line (J0403-21) to 12.5 volts and start 
loading the data to be stored in the FLASH. The microprocessor will verify that 
each of the FLASH EEPROM memory locations are programmed correctly. 
						

							Controller Section Theory of Operation 7-17
Audio and 
Signalling 
Circuits(Refer to ASFIC schematic page 10-23 for reference)
Audio Signalling 
Filter IC (ASFIC)The ASFIC has 4 functions;
1. RX/TX audio shaping, i.e. Þltering, ampliÞcation, attenuation
2. RX/TX signalling, PL/DPL/HST/MDC/MPT
3. Squelch detection
4. Microprocessor clock signal generation (see Microprocessor Clock 
Synthesizer Description Block).
The ASFIC is programmable through the SPI BUS (U0200-E3/F1/F2), normally 
receiving 21 bytes. This programming sets up various paths within the ASFIC 
to route audio and/or signalling signals through the appropriate Þltering, gain 
and attenuator blocks. The ASFIC also has 6 General Control Bits GCB0-5 
which are CMOS level outputs. In this radio all, except GCB2 used for AUX TX 
IN2 (see Aux TX), are used to control the Hear Clear IC. (See Hear Clear 
Description Block for details).
Audio Ground
(Refer to schematic 
page 10-25 for 
reference)VAG is the dc bias used as an audio ground for the op-amps that are external 
to the Audio Signalling Filter IC (ASFIC). U0201 forms this bias by dividing 
9.3 V with R0206 and R0207 and buffering the 4.65 V result with a voltage 
follower. VAG emerges at pin 1 of U0201. C0235 is a bypass capacitor for VAG. 
The ASFIC generates its own 2.5 V bias for its internal circuitry. C0210 is the 
bypass for the ASFICÕs audio ground dc bias. Note that while there are ASFIC 
VAG, BOARD VAG (U0201), and Hear Clear VAG, each of these are separate. 
They do not connect together.
Transmit Audio 
Circuits
(Refer to schematic 
page 10-23 for 
reference)(Refer to Figure 7-2 for reference for the following sections)
The radio supports 2 distinct microphone paths known as internal and 
external mic. The microphones used for the radio require a DC biasing voltage 
provided by R0222 and R0223 for internal, and R0231 and R0230 for external. 
These two microphone audio input paths enter the ASFIC at U0200-A7 
(external mic) and U0200-B8 (internal mic). Following the internal mic path; 
the microphone is plugged into the radio control head and is connected to the 
controller board via J0405-9.
From here the signal is routed to R0224. R0222 and R0223 provide the 
9.3 VDC bias and R0224 provides input protection for the CMOS ampliÞer 
input. R0223 and C0219 provide a 560 ohm AC path to ground that sets the 
input impedance for the microphone and determines the gain based on the 
emitter resistor in the microphoneÕs ampliÞer circuit.
Filter capacitor C0224 provides lowpass Þltering to eliminate frequency 
components above 3 kHz, and C0218 serves as a DC blocking capacitor. C0427 
bypasses RF interference which may couple onto the line to ground. The audio 
signal at U0200-B8 should be approximately 80 mV to achieve 60% of 
maximum system deviation.
The ASFIC has an internal AGC that can control the gain in the mic audio 
path. The AGC can be disabled/enabled by the mP. Another feature that can be  
						

							7-18 Controller Section Theory of Operationenabled or disabled in the ASFIC is the VOX. This circuit, along with C0205, 
provides a DC voltage that can allow the mP to detect microphone audio. The 
ASFIC can also be programmed to route the microphone audio to the speaker 
for public address operation.
External Mic PathThe external microphone signal enters the radio on accessory connector J0403 
pin 23. It is then routed to the ASFIC through resistor R0229 and capacitors 
C0223 and C0221, with DC bias provided by R0231/R0230
PTT Sensing and 
TX Audio 
ProcessingMic PTT is sensed via SB9600. An external PTT can be generated by 
programming one of the digital I/O lines on the accessory connector for PTT 
and grounding that pin. When microphone PTT is sensed, the mP will always 
conÞgure the ASFIC for the ÒinternalÓ mic audio path, and external PTT will 
result in the external mic audio path being selected.
.
Figure 7-2    Transmit Audio Paths
Inside the ASFIC, the mic audio is Þltered to eliminate components outside the 
300-3000 Hz voice band, and pre-emphasized if pre-emphasis is enabled. The 
HEARCLEAR - I
IC
U0250
ASFIC
U0200
COMP BUF IN
COMP OUT HPF
 MIC INTX IN
MIC AMP OUT
EXT MIC IN
AUX TX IN
PRE EMP OUTLIM INVCO ATNAUDIO MODTO
RF
SECTION
(VCO)
C7A6
D3
E8 C8H8
J408
INTERNAL OPTION
CONNECTOR
J401
INTERNAL OPTION
CONNECTOR
J403
ACCESSORY
CONNECTOR
J405
CONTROL HEAD
CONNECTOR
MIC
EXT MIC
AUX TX
D7F3
AUX TX
AUX TX
14
1424
A7 13
B8 923
FILTERS AND
PREEMPHASIS
SPLATTER
FILTER
LS SUMMER
HS SUMMER
LIMITER
ATTENUATOR