Motorola Gtx2000 Lcs2000 68p02945c70 O Manual

							7-6 Theory of Operation
Synthesizer Detailed
Functional DescriptionThe complete synthesizer subsystem consists of a reference oscillator (U5700), a
Fractional-N Synthesizer IC (U5702), two on-board voltage controlled oscillators,
a buffer stage (U5701), and two line-up ampliÞers (Q5707, Q5705).
Reference oscillator U5700 contains a temperature compensated crystal with an
oscillation frequency of 16.8 MHz. The output of the oscillator (pin 10 of U5700)
is then applied to pin 14 (XTAL1) of U5702 via C5733 and R5715.
There are two VCOs which are varactor tuned. The oscillator frequency is
controlled by the voltage applied via L5702 and L5701. This control voltage
ranges from about 2.5 to 10.5 V DC. A small control voltage produces a lower
frequency and a large control voltage produces a high frequency respectively.
The RX/TX VCO (806 - 825 MHz frequency range) provides the Þrst LO
injection frequency which is 45.1 MHz below the carrier frequency and the TX
injection in the conventional mode. The RX/TX VCO is selected by pulling pin 1
(AUX 3) low on U5702.
The TA (Talk-Around) VCO (851 - 870 MHz frequency range) provides the
transmit frequency in talk-around mode. The TA VCO is selected by pulling pin
1 high on U5702.
The buffer stage (U5701) and the feedback ampliÞer (Q5703) provide the
necessary gain and isolation for the synthesizer loop.
Fractional-N Synthesizer IC U5702 consists of:
¥Prescaler
¥Programmable loop divider
¥Control divider logic
¥Phase detector
¥Charge pump
¥A/D Converter for low frequency digital modulation
¥Balance attenuator to balance the high and low frequency analog modulation
¥13-V positive voltage multiplier,
¥Serial interface for control,
¥Super Þlter for the regulated 9.3 V
 C5712 is used as a super Þlter capacitor. The output voltage of the super Þlter (pin
18) drops from 9.3 V to about 8.5 V. This Þltered 8.5 VDC supplies the voltage
for the VCOs, the VCO switching units (U5704 & U5705), feedback ampliÞer
(Q5703), and synthesizer charge pump resistor network (R5707- R5709).
The synthesizer supply voltage is provided by the 5 V regulator (U5703). The
2.1 MHz reference signal (pin 11 of U5702) is generated by dividing down the
signal of reference oscillator U5700 after it is applied to pin 14 of U5702.
In order to generate a high voltage that supplies the charge pump output stage at
pin VCP (pin 32 of U5702), 13 V is generated at pin 3 of CR5700 by the positive
voltage multiplier circuitry (CR5700). This voltage multiplier is basically a diode
capacitor network driven by two 1.05 MHz, 180-degree out-of-phase signals (pin
9 and 10 of U5702). 
						

							Theory of Operation 7-7 The serial interface (SPI_DATA) is connected to the microprocessor via the data
line (pin 5 of U5702), clock line (pin 6 of U5702), and chip enable line (pin 5 of
U5702). Proper enabling of these lines should allow the microprocessor to load
the synthesizer IC.
The output of the VCO is fed into the buffer input port (pin 1) of U5701. The
output of the buffer, pin 5 of U5701, is applied to the input of the feedback
ampliÞer (Q5703) through an attenuator network (R5735, R5733, R5732). To
close the synthesizer loop, the output of Q5703 is connected to the PREIN port
(pin 20) of synthesizer U5702. The buffer output (pin 5 of U5701) also provides
signal for the receiver LO injection and transmit injection string circuit. The
charge pump current is present at pin 31 of U5702.
The loop Þlter (which consists of R5716, R5717, R5734, C5750, C5744, C5745,
C5736, C5746, C5747, C5794, C5795, C5796, C5797, C5798, C5799) will then
transform this current into a voltage that will, in turn, be applied to Vcontrol of the
VCOs and alter the output frequency.
In order to modulate the PLL, the two-point modulation method is utilized. The
audio signal is applied to both the A/D converter (low frequency path) as well as
the balance attenuator (high frequency path) via pin 8 on U5702.
The A/D converter will convert the low-frequency, analog modulating signal into
a digital code that will in turn be applied to the loop divider. This will cause the
carrier to deviate. The balance attenuator is used to adjust the VCO deviation
sensitivity to high frequency modulating signals. The output of the balance
attenuator is present at the MODOUT port (pin 28 of U5702).
The transmit injection string consists of two ampliÞer stages (Q5707 & Q5705)
whose main purpose is to maintain a constant output to drive the RFPA and
provide isolation. The Q5705 stage is actively biased through Q5701, and Q5707
has passive bias. The TX injection string is on, only during the transmit mode (K
9.1V line is at 9.1 V).
There are two VCOs, one for the 806-825 band that is used as LO INJ. during
receive and TX INJ. at conventional mode. The second VCO is used as TX INJ.
in the talk-around mode.
The VCOs get their control voltage through L5702 and L5701. Q5704 and Q5706
are the oscillation transistors. C5793, C5792 and C5785, C5784 are the oscillator
feedback capacitors. U5707 and U5706 are micro strip resonators. CR5702 and
CR5701 are the varactors. C5790 and C5782 determine the KV. C5703 and C5704
determine the VCO operation frequency.
C5791 and C5783 are the coupling capacitors between the tank and the oscillation
transistor.
The two VCOs are coupled to the buffer (Q5702) through C5789 and C5786. The
stage output signal is fed to U5701 input (pin 1) through C5770 & R5736. 
						

							7-8 Theory of Operation
Controller Detailed
Functional Description
GeneralThe radio controller consists of four main subsections:
¥Digital Control
¥Audio Processing
¥Power Control
¥Voltage Regulation
The digital section consists of a microprocessor, memory ICs, glue logic circuitry,
signal MUX ICs, On/Off circuit, and general purpose Input/Output circuitry.
The controller is based on the Motorola 68HC11K1 microprocessor (U0101), 8-
Kbyte SRAM (U0103), 128 Kbyte-OTP memory (U0102), and 4 Kbyte EEPROM
(U0104).
Note:From this point on, the 68HC11K1 microprocessor will be
referred to as K1mP ormP.
References to a Control Head will be to type P+ (Display
radio).
Voltage RegulatorsVoltage regulation for the controller is provided by 3 separate devices; U0631
(LP2951CM) +5V, U0601 (LM2941T) +9.3V, and UNSW 5V (R0621 and
VR0621). An additional regulator is located in the RF section.
5-V voltage regulation for the digital circuitry is provided by U0631. Input and
output capacitors (C0631/0632 and C0633-0635) are used to reduce high-
frequency noise and provide proper operation during short battery transients. This
regulator provides a reset output (pin 5) that drops to 0 V while the regulator
output goes out of regulation. This is used to reset the controller in order to prevent
improper operation. Diode D0631 prevents discharge of C0632 by negative spikes
on the 9V3 voltage.
Regulator U0601 is used to generate the 9.3 V required by some audio circuits, the
RF circuitry and power control circuitry. Input and output capacitors (C0601-0603
and C0604/0605) are used to reduce high-frequency noise. R0602/R0603 set the
regulator output voltage. If the voltage at pin 1 is greater than 1.3 volts the
regulator output decreases and if the voltage is less than 1.3 V, the regulator output
increases. This regulator output is electronically disabled by a 0 V signal on pin 2.
Q0601 and associated circuitry (R0601/0604/0605) are used to disable the
regulator when the radio is turned off.
UNSW 5V is only used by a few circuits which draw low current and require 5 V
while the radio is off.
UNSW 5V CL is used to save the internal RAM data. C0622 allows the battery
voltage to be disconnected for a couple of minutes without losing RAM
parameters. Diode D0621 prevents radio circuitry from discharging this capacitor.
The SW +B voltage is monitored by themP through voltage divider R0641/R0642.
Diode VR0641 limits the divided voltage to 5.1 V in order to protect themP. 
						

							Theory of Operation 7-9 Diode D5601 located on the PA section acts as protection against transients and
wrong polarity of the supply voltage.
Electronic On/OffThe radio has circuitry which allows radio software and/or external triggers to turn
the radio on or off without direct user action.
Some examples of where this is useful are: 1) automatic turn on when emergency
switch is engaged; 2) automatic turn on when ignition is sensed and off when
ignition is off.
Q0611 is used to provide SW B+ to the various radio circuits. Q0611 acts as an
electronic on/off switch controlled by Q0612 (the switch is on while Q0612 is on).
When the radio is turned on, the voltage at the base of Q0612 is high (about 0.6
V). Q0612 switches on (saturation) and pulls down the voltage at Q0611-base.
This turns on Q0611 and supplies SWB+ to the radio. The on resistance of Q0611
is very low (less than 1 W), so the voltage level at SWB+ is quite the same as A+.
The electronic on/off circuitry can be enabled by the microprocessor (through
ASFIC, line B+ CONTROL), the emergency switch (line EMERGENCY
CONTROL), the mechanical On/Off button on the control head (line ON OFF
CONTROL), or the ignition sense circuitry (line IGNITION CONTROL). If one
of the 4 paths cause a low at the collector of Q0612, the electronic ON process is
engaged.
EmergencyThe emergency switch, when pressed, grounds the base of Q0441 and pulls the
line EMERGENCY CONTROL to low. EMER IGN SENSE is pulled high by
R0441. When the emergency switch is released, the base of Q0441 is pulled high
by R0442. This causes the collector of transistor Q0441 to drop down (0.2 V),
thereby setting the EMER IGN SENSE line to low.
While EMERGENCY CONTROL is low, Q0611 is turned on, SW B+ is enabled,
the microprocessor starts execution, reads the voltage level of EMER IGN SENSE
line, and sets the B+ CONTROL output of the ASFIC to a logic high. This high
level keeps Q0611 switched on through Q0612. This operation allows powering
on the radio by a momentary press of the emergency switch. When the
microprocessor has Þnished processing the emergency press, it sets the B+
CONTROL line to a logic 0. This cuts off Q0611 and the radio turns off. Notice
that the microprocessor is alerted to the emergency condition via line EMER IGN
SENSE. If the radio was already on when emergency was triggered, then B+
CONTROL would have already been at a high level.
Mechanical On/OffThis refers to the typical on/off button which is located on the control head and
turns the radio on and off. While the on/off button is turned on, line ON OFF
CONTROL goes high during the short pulse generated by the ON_OFF Òone-
shotÓ circuitry in the control head. This switches the radio on. The microprocessor
is alerted through line ANALOG 3 which is pulled to low by Q0925 (Control
Head P+) while the on/off button is turned on. If the software detects a low state,
it asserts B+ CONTROL via ASFIC-GCB2, which keeps Q0612 and Q0611on,
and in turn the radio is switched on.
While the on/off button is turned off, the software detects the line ANALOG 3
changing to low and switches the radio off by setting B+ CONTROL to low.
IgnitionIgnition sense is used to prevent the radio from draining the vehicleÕs battery while
the engine is not running. 
						

							7-10 Theory of OperationWhen the IGNITION input goes above 6 V, Q0450, Q0612 and Q0611 turn on,
supplying SW B+ to the radio and enabling U0601 and U0631 to supply the
regulated voltage (+5 V and 9.3 V) to all the circuitry. ThemP starts to run the
software, reads the line EMER IGN SENSE, determines from the level
(Emergency has a different level) that the IGNITION input is active and sets the
B+ CONTROL (via the ASFIC-GCB2) to high and latches SW B+ to on.
While the IGNITION line drops below 6 V, Q0450 switches off and R0441 pulls
line EMER IGN SENSE high. The software is alerted by line EMER IGN SENSE
to switch off the radio by setting B+ CONTROL line to low. Whenever the
IGNITION line goes above 6 V, the above process will be repeatedÑdepending
if the radio was previously on or off.
HookThe HOOK line is used to inform themP when the Microphone«s hang-up switch
is engaged. Depending on the radio model, themP turns the audio PA on or off.
The signal is routed from J0101-3 and J0400-14 through transistor Q0101 to the
K1mP U0101-PH1 (pin 23). The voltage range of HOOK in normal operating
mode is 0-5 V.
Microprocessor Clock
SynthesizerThe clock source for the controllerÕs microprocessor system is generated by the
ASFIC (U0201). Upon power-up the synthesizer (U5701) generates a 2.1 MHz
waveform that is routed from the RF section (via C0202) to the ASFIC (on U0201
XTAL_IN). For the main board controller, the ASFIC uses 2.1 MHz as a reference
input clock signal for its internal synthesizer. The ASFIC, in addition to audio
circuitry, has a programmable synthesizer which can generate a synthesized signal
ranging from 1200 Hz to 32.769 MHz with steps of 1200 Hz.
While the radio is turned on, the ASFIC generates a default 3.6864 MHz CMOS
square wavemP CLK (on U0201-UPCLK) which is routed to themP (U0101-
EXTAL). After themP starts operation, it reprograms the ASFIC synthesizer clock
to a highermP CLK frequency (usually 7.3728 or 14.7456 MHz) and continues
operation.
The ASFIC synthesizer clock is controlled by the software, and may slightly be
changed while harmonics of this clock source interfere with the speciÞc radio
receive frequency.
The ASFIC synthesizer loop components (C0228, C0229 and R0222) set the
switching time and jitter of the clock output. If the synthesizer cannot generate the
required clock frequency it will switch back to its default 3.6864 MHz frequency.
Serial Peripheral Interface
(SPI)ThemP communicates with the other programmable ICs through its SPI port. This
port consists of SPI TRANSMIT DATA (MOSI) (K1mP: U0101-1), SPI
RECEIVE DATA (MISO) (K1mP: U0101-80), SPI CLK (K1mP: U0101-2) and
chip select lines going to the various programmable ICs. This BUS is a
synchronous bus (the timing clock signal CLK is sent with SPI TRANSMIT
DATA or SPI RECEIVE DATA).
In the controller section, there are three ICs on the SPI BUS: ASFIC (U0201-E3),
EEPROM (U0104) and D/A (U0731-6). In the RF sections, there are 2 ICs on the
SPI BUS: Pendulum (Reference Oscillator U5702-24) and Synthesizer (U5701-
7). The SPI TRANSMIT DATA and CLK lines going to the RF section are Þltered
with L0131/L0132 to minimize noise. The chip select lines for the ICs are
decoded by the address decoder U0105. 
						

							Theory of Operation 7-11 SPI BUS is also used for the control head. U0106 buffers the SPI TRANSMIT
DATA and CLK lines to the control head. U0106 serves also to switch off the CLK
signal for the LCD display while it is not selected via LCD CE signal.
When themP needs to program any of these ICs, it drops down the chip select line
of the speciÞc IC to a logic 0 and then sends the proper data and clock signals. The
data sent to the various ICs are different. For example the ASFIC receives 21 bytes
(168 bits) while the DAC needs 3 bytes (24 bits). After the data has been sent the
chip select line is returned to a logic 1.
SBEP Serial InterfaceThe SBEP serial interface line allows the radio to communicate with the Dealer
Programming Software (DPS). This interface connects to the Microphone
connector (J0902) via Control Head connector (J0101) and comprises BUS+
(J0101-15). The line is bi-directional, meaning that either the radio or the DPS can
drive the line.
The connection from the Control Head is made through the BUS+ line, via L421
(SCI_RSS line) and diode CR151 to the K1mP-TxD and K1mP-RxD ports.
Microprocessor (Open
Controller)For this radio, the K1mP is conÞgured to operate in the expanded or bootstrap
modes. In expanded mode the K1mP uses external memory ICs, whereas in
bootstrap mode it uses only its internal memory. In normal radio operation, the
K1mP is operating in the expanded mode.
In the radio expanded mode, the K1mP (U0101) has access to three external
memory ICs: U0102 (OTP memory), U0103 (SRAM), U0104 (EEPROM). Also,
within the K1mP there are 768 bytes of internal RAM and 640 bytes of internal
EEPROM, as well as glue logic circuitry to select external memory ICs.
The external EEPROM (U0104) as well as the K1mPÕs own internal EEPROM
contain the radio information which is customer speciÞc, referred to as the
codeplug. This information consists of items such as: 1) frequency operating band,
2) channel frequencies, and 3) general tuning information. General tuning
information and other more frequently accessed items are stored in the internal
EEPROM (within the 68HC11K1), while the remaining data is stored in the
external EEPROM. (See the particular IC subsection for more details.)
The external SRAM (U0103) as well as the K1mPÕs own internal RAM are used
for temporary calculations required by the software during normal radio
operation. All of the data stored in both of these locations is lost when the radio is
powered off. (See the particular IC subsection for more details.)
The OTP memroy contains the actual Radio Operating Software. This software is
common to all radios for the same model type. For example Securenet radios may
have a different version of software in the OTP memory than a non-secure radio.
(See the particular IC subsection for more details.)
The K1mP has an address bus of 16 address lines (A0-A15), a data bus of 8 data
lines (D0-D7). and three control lines; CSPROG (U0101-29) to select U0102-30
(OTP memory), CSGP2 (U0101-28) to select U0103-20 (SRAM) and PG7_R_W
for read and write. All other chips (ASFIC/PENDULLUM/DAC/FRACN/LCD/
LED/EEPROM) are selected by 3 lines of the K1mP using chip select decoder
U0105. While the K1mP is functioning normally, the address and data lines should
be within CMOS logic levels.
The low-order address lines (A0-A7) and the data lines (D0-D7) should change. 
						

							7-12 Theory of OperationOn the K1mP the lines XIRQ (U0101-30), MODA LIR (U0101-77), MODB
VSTPY (U0101-76) and RESET (U0101-75) should be logic high during all
normal K1mP operation. Whenever a data or an address line becomes unloaded or
shorted to an adjacent line, a common symptom is that short negative pulses occur
on the RESET line, with a period of 20 msec. When two lines are short-circuited,
mid logic level (around 2.5 V) may be observed, while these lines are opposite
driven by two different ICs.
The MODA LIR (U0101-77) and MODB VSTPY (U0101-76) inputs to the K1mP
must be at a logic 1 level for proper operation. After the K1mP starts execution, it
will periodically pulse these lines to determine the desired operating mode. While
the Central Processing Unit (CPU) is running a new instruction, MODA LIR (as
an open-drain CMOS output) drops low.
However, since it is an open-drain output, the signal waveform rise has an
exponential shape, like an RC circuit.
ThemP has eight analog-to-digital converter ports (A/D): PE0 to PE7. These lines
may measure voltage levels in the range of 0 to 5 V and convert that level to a
number ranging from 0 to 255 which can be read by the software to take
appropriate action.
For example, U0101-46 is the battery voltage detect line. R0641 and R0642 form
a resistor divider on SWB+. With 30K and 10K and a voltage range of 11 V to 17
V, that A/D port would see 2.74 V to 4.24 V which would then be converted to
digital values of ~140 to 217 respectively.
U0101-51 is the high reference voltage for the A/D ports on the K1mP. Resistor
R0106 and capacitor C0106 Þlter the +5 V reference. If this voltage is lower than
+5 V the A/D readings will be incorrect. Likewise U0101-50 is the low reference
for the A/D ports. This line is normally tied to ground. If this line is not connected
to ground, the A/D readings will be incorrect.
Capacitors C0104, C0105 serve to Þlter out any AC noise which may ride on +5V
at U0101.
Input IRQ (U101-61) generates an interrupt, if either HOOK (J0101-3) is higher
than 6V (SBEP communication) or a low at the option interrupt pin (J0103-8)
turns Q0124 off and Q0125 on. The K1mP determines the interrupt source by
reading the collector of Q0104 via U0101-6 and the collector Q0124 via U0101-7.
One-Time Programmable
(OTP) MemoryThe 128-KByte OTP memory (U0102) contains the radioÕs operating software.
This memory is read-only. The memory access signals (CE, OE and WE) are
generated by themP.
The OTP memory is factory-programmed once only.
Capacitor C0131 serves to Þlter out any AC noise which may ride on +5V at
U0101, and C0132 Þlters out any AC noise on Vpp.
Electrically Erasable
Programmable Memory
(EEPROM)EEPROM (U0104) contains the radioÕs operating parameters such as operating
frequency and signalling features, commonly known as the codeplug. It is also
used to store radio operating state parameters such as current mode and volume.
U0104 is a 4 Kbyte device. This memory can be written to in excess of 100,000
times and will retain the data when power is removed from the radio. The memory 
						

							Theory of Operation 7-13 access signals (SI, SO and SCK) are generated by the K1mP and chip select (CS)
is generated by address decoder U0105.
Additional EEPROM is contained in the K1mP (U0101). This EEPROM is used
to store radio tuning and alignment data. Like the external EEPROM this memory
can be programmed multiple times and will retain the data when power is removed
from the radio.
Note:The external EEPROM plus the 640 bytes of internal EEP-
ROM in the 68HC11K1 comprise the complete codeplug.
Static Random Access
Memory (SRAM)The SRAM (U0103) contains temporary radio calculations or parameters that can
change very frequently, and which are generated and stored by the software during
its normal operation. The information is lost when the radio is turned off. The
device allows an unlimited number of write cycles. SRAM accesses are indicated
by the CS signal U103-20 (which comes from U101-CSGP2) going low. U0103
is commonly referred to as the external RAM as opposed to the internal RAM
which is the 768 bytes of RAM which is part of the 68HC11K1. Both RAM spaces
serve the purpose. However, the internal RAM is used for the calculated values
which are accessed most often. Capacitor C0133 serves to Þlter out any AC noise
which may ride on +5V at U0103.
Control Head Model P+Control Head Model P+ is available for user interface. The Control Head contains
the internal speaker, the microphone connector, several buttons to operate the
radio and several indicator LEDs to inform the user about the radio status.
Additionally Control Head P+ uses a 3 digit LCD display for the channel number.
When turned on, the On/Off switch  switches the voltage regulators on by pulling
ON OFF CONTROL to high and connects the base of Q0925(P), Q0825(K) to
FLT A+. This transistor pulls the line ANALOG 3 to low to inform themP that the
On/Off button is pressed. If the radio is switched off, themP will switch it on and
vice versa. All other buttons work the same way. If a button is pressed, it will
connect one of the 3 lines ANALOG 1,2,3 to a resistive voltage divider connected
to +5V. The voltages of the lines are A/D converted inside themP and specify the
pressed button.
All the back light and indicator LEDs are driven by current sources and controlled
by themP via SERIAL PERIPHERAL INTERFACE (SPI) interface. The LED
status is stored in shift register U0941(P). Line LED CE enables the serial write
process via Q0941(P), while line LED CLCK BUF shifts the data of line SPI
DATA BUF into the shift register.
In addition Control Head P contains the LCD display H0931, the display driver
U0932 and a transistor (U0931) to switch the display driver on and off in
emergency condition. Q0931 is controlled by themP via shift register U0941, The
display data of line SPI DATA BUF is shifted into the display driver by clock
signal LCD CLCK BUF. 
						

							7-14 Theory of Operation
Controller Audio &
Signaling Circuits
General
Audio Signalling Filter IC
(ASFIC)The ASFIC (U0201) used in the controller has four functions;
¥RX/TX audio shaping, i.e. Þltering, ampliÞcation, attenuation
¥RX/TX signalling, PL/DPL/HST/MDC/MPT
¥Squelch detection
¥Microprocessor clock signal generation (see Microprocessor Clock
Synthesizer Description Block).
The ASFIC is programmable through the SPI BUS (U0201-E3/F1/F2), normally
receiving 21 bytes. This programming sets up various paths within the ASFIC to
route audio and/or signalling signals through the appropriate Þltering, gain and
attenuator blocks. The ASFIC also has 6 General Control Bits GCB0-5 which are
CMOS level outputs and used for AUDIO PA ENABLE (GCB0) to switch the
audio PA on and off, EXTERNAL ALARM (GCB1) and B+ CONTROL (GCB2)
to switch the voltage regulators (and the radio) on and off. GCB3 controls output
GPI/O (accessory connector J0400-12), HIGH LOW BAND (GCB4) can be used
to switch between band splits and GCB5 is available on the option board
connector J0102-5.
Audio GroundVAG is the dc bias used as an audio ground for the op-amps that are external to
the Audio Signalling Filter IC (ASFIC). U0251 forms this bias by dividing 9.3V
with resistors R0251, R0252, and buffering the 4.65V result with a voltage
follower. VAG emerges at pin 1 of U0251. C0235 is a bypass capacitor for VAG.
The ASFIC generates its own 2.5V bias for its internal circuitry. C0221 is the
bypass for the ASFICÕs audio ground dc bias.
Note:While there are ASFIC VAG, and BOARD VAG (U0201-1),
each of these are separated. They are not connected together.
Transmit Audio CircuitsRefer to the following sections.
Mic Input PathThe radio supports two distinct microphone paths known as internal and external
mic and an auxiliary path (FLAT TX AUDIO). The microphones used for the
radio require a DC biasing voltage provided by a resistive network.
These two microphone audio input paths enter the ASFIC at U0201-A7 (external
mic) and U0201-B8 (internal mic). Following the internal mic path; the
microphone is plugged into the radio control head and is connected to the
controller board via J101-16.
From here the signal is routed to R0206. R0204 and R0205 provide the 9.3VDC
bias and R0206 provides input protection for the CMOS ampliÞer input. R0205
and C0209 provide a 1kohm AC path to ground that sets the input impedance for
the microphone and determines the gain based on the emitter resistor in the
microphoneÕs ampliÞer circuit. 
						

							Theory of Operation 7-15 Figure 7-3 Transmit Audio Paths
Filter capacitor C0210 provides low-pass Þltering to eliminate frequency
components above 3 kHz, and C0211 serves as a DC blocking capacitor. The
audio signal at U0201-B8 should be approximately 80mV for 3kHz of deviation
with 25 kHz channel spacing.
The FLAT TX AUDIO signal from accessory connector J0400-5 is buffered by
op-amp U0202-1 and fed to the ASFIC U0201-D7 through C0205.
External Mic PathThe external microphone signal enters the radio on accessory connector J0400 pin
2 and connects to the standard microphone input through R0413. The signal is
routed to the ASFIC (U0201-A7) through resistor R0414 and capacitors C0413
and C0414, with DC bias provided by R0415 / R0416.
PTT Sensing and TX Audio
ProcessingMic PTT is sensed by themP. An external PTT can be generated by grounding pin
3 on the radio accessory connector. When microphone PTT is sensed, themP will
always conÞgure the ASFIC for the ÒinternalÓ mic audio path, and external PTT
will result in the external mic audio path being selected for models with separated
MIC and EXT MIC signals.
Inside the ASFIC, the mic audio is Þltered to eliminate components outside the
300-3000Hz voice band, pre-emphasized if pre-emphasis is enabled. The
capacitor between ASFIC pre-emphasis out U0201-C8 and ASFIC limiter in
U0201-E8 AC couples the signal between ASFIC blocks and prevents the DC bias
at the ASFIC output U0201-H8 from shifting when the ASFIC transmit circuits
are powered up. The signal is then limited to prevent the transmitter from over
deviating. The limited mic audio is then routed through a summer which, is used
to add in signalling data, and then to a splatter Þlter to eliminate high frequency
spectral components that could be generated by the limiter. The audio is then
MIC
IN
TO RF
C7 A6
E8 C8H8
J0400
ACCESSORY
J0101
CONTROL HEAD
MIC
EXT MIC
FLAT TXD7
5A7
B8 16
2
FILTERS &
LS SUMMER
SPLATTER
HS SUMMER
LIMITER
ATTENUATORVCO TX IN
MIC AMP OUT
MIC IN
EXT
AUX TX IN
PRE EMP OUTLIM INASFIC U0201
MOD IN PREEMPHASIS CONNECTOR
CONNECTORFILTER
ATN
SECTION
(SYNTHESIZER) AUDIOMIC IN