Motorola Cp200 Detailed 6880309n62 C Manual

							Chapter 3 Controller Theory of Operation
3.1 Controller
The controller provides the following functions:
• interface with controls and indicators
• serial bus control of major radio circuit blocks
• encoding and/or decoding of selective signaling formats such as PL, DPL, MDC1200 and Quik-
Call II
• interface to CPS programming via the microphone connector
• storage of customer-specific information such as channel frequencies, scan lists, and signaling 
codes
• storage of factory tuning parameters such as transmitter power and deviation, receiver squelch 
sensitivity, and audio level adjustments
• power-up, power-down and reset routines
Figure 7-3 (VHF) shows the interconnection between the controller and the various other radio 
blocks. Figure 7-9 show the connections between the following circuit areas which comprise the 
controller block:
• microprocessor circuitry
• audio circuitry
• DC regulation circuitry (refer to Chapter 2, DC Regulations and Distribution.)
• rotary and pushbutton controls and switches
• option board interface
The majority of the circuitry described below is contained in the (VHF) Microprocessor Circuitry 
schematic diagrams (Figure 7-10). Portions are also found in the Audio and DC Regulation 
schematics (Figures 7-11 and 7-12).
3.1.1 Microprocessor Circuitry
The microprocessor circuitry includes microprocessor (U401) and associated EEPROM, S-RAM (not 
used in PR400 models), and Flash ROM memories. The following memory ICs are used:
Table 3-1.  Radio Memory Requirements
Reference No. Description Type Size
U402Serial EEPROMAT2512816K x 8
U403 Static RAM (not used)
U404Flash ROMAT49LV001N_70 V128K x 8 
						

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3-2Controller Theory of Operation: Controller
3.1.1.1  Memory Usage
Radio operation is controlled by software that is stored in external Flash ROM memory (U404).  
Radio parameters and customer specific information is stored in external EEPROM (U402). The 
operating status of the radio is maintained in RAM located within the microprocessor. When the radio 
is turned off, the operating status of the radio is written to EEPROM before operating voltage is 
removed from the microprocessor. See section “3.1.1.7 Microprocessor Power-Up, Power-Down and 
Reset Routine” on page 3-3 for a discussion of the power-down routine.
Parallel communication with U403 and U404 is via:
• address lines A(0)-A(16), from U401 port F ADDR0-ADDR13 and port G XA14-XA16 
• data lines D(0)-D(7), from U401 port C DATA0-DATA7 
• chip-select for U403, from PH6 (U401 pin 41)
• chip-enable for U404, from PH7 (U401 pin 38)
• output enable for U404, from PA7 (U401 pin 86)
• write-enable for both U403 and U404, from PG7_R/W (U401 pin 4)
Serial communication with U402 is via:
• the SPI bus (see section “3.1.1.3 Serial Bus Control of Circuit Blocks” on page 3-2)
• chip-select for U402, from PD6 (U401 pin 3)
3.1.1.2  Control and Indicator Interface
Ports PI3 and PI4 are outputs which control the top-mounted LED indicator. When PI3 is high, the 
indicator is red. When PI4 is high, the indicator is green. When both are high, the indicator is amber. 
When both are low, the indicator is off.
Pressing the side-mounted PTT button (S441) provides a low to port PJ0 (U401 pin 71), which 
indicates PTT is asserted. Side-mounted option buttons 1 and 2 (S442 and S443) are connected to 
Ports PJ6 (pin 77) and PJ7 (pin 78), respectively.
3.1.1.3  Serial Bus Control of Circuit Blocks
The microprocessor communicates with other circuit blocks via a SPI (serial peripheral interface) bus 
using ports PD2 (data into uP), PD3 (data out of uP) and PD4 (clock). The signal names and 
microprocessor ports are defined in Table 3-2.
These signals are routed to:
• the audio filter IC (U451) to control internal functions such as gain change between 25 kHz and 
12.5 kHz channels, transmit or receive mode, volume adjustment, etc.
• the synthesizer IC U201 to load receive and transmit channel frequencies
• option board connector J460-1 for internal option configuration and control
• serial EEPROM U402 (both SPI_DATA_IN and SPI_DATA_OUT are used). Table 3-2.  SPI Bus Signal Definitions
Signal Name Microprocessor Port Microprocessor Pin
SPI-DATA_INPD2-MISOU401 Pin 99
SPI_DATA_OUT PD3-MOSI U401 pin 100
SPI_CLKPD4-SCKU401 pin 1 
						

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Controller Theory of Operation: Controller3-3
In order for each circuit block to respond only to the data intended for it, each peripheral has its own 
chip select (or chip enable) line. The device will only respond to data when its enable line is pulled 
low by one of the microprocessor ports, as follows:
• port PD5 (U401 pin 2) for the audio filter IC
• port PH0 (U401 pin 47) for the synthesizer IC
• port PD6 (U401 pin 3) for the serial EEPROM.
3.1.1.4  Interface to RSS Programming
The radio can be programmed, or the programmed information can be read, using a computer with 
CPS (Customer Programming Software) connected to the radio via a RIB (radio interface box) or 
with the RIB-less cable. Connection to the radio is made via the microphone connector (part of 
accessory connector J471). The SCI line connects the programming contact (J471 pin 6) to ports 
PD0_RXD (data into uP, pin 97) and PD1_TXD (data out of uP, pin 98). Transistor Q410 isolates the 
input and output functions by allowing PD1 to pull the line low, but does not affect incoming data from 
being read by port PD0. This isolation allows high-speed 2-wire programming via TP401 and TP402 
for factory programming and tuning.
3.1.1.5  Storage of Customer-Specific Information
Information that has been programmed using CPS, such as channel frequencies or selective 
signaling codes, are stored in the external EEPROM, where it is retained permanently (unless 
reprogrammed) without needing DC power applied to the microprocessor.
3.1.1.6  Sensing of Externally-Connected Accessories
Port PJ1 is used to detect the presence of externally connected accessories. Port PJ1 (U401 pin 72) 
is normally low, unless accessories (lapel speaker microphone, lightweight headset, etc.) are used 
with the radio. This port is used to detect an accessory PTT or auto sensing of a VOX accessory. 
If VOX is programmed into the radio channel codeplug information, and PJ1 is high during power-up, 
the radio will activate VOX operation. If a low is present at port PJ1 during power-up, the radio will 
use this port as an external PTT indicator.
3.1.1.7  Microprocessor Power-Up, Power-Down and Reset Routine
On power-up, the microprocessor is held in reset until the digital 3.3 V regulator (U320 pin 5) 
provides a stable supply voltage. Once the digital supply reaches steady state and releases the reset 
line (U320 pin 7), the microprocessor begins to start up. The ASFIC_CMP (U451) has already 
started running and is providing the startup clock to the microprocessor. After reset release by all 
circuits, the software within the microprocessor begins executing port assignments, RAM checking, 
and initialization. A fixed delay of 100 ms is added to allow the audio circuitry to settle. Next, an alert 
beep is generated and the steady state software begins to execute (buttons are read, radio circuits 
are controlled).
When the radio is turned off, SWB+ is removed and port PE0 (U401 pin 67) goes low, initiating a 
power-down routine. Port PH3 (pin 44) remains high, keeping the voltage regulators on via Q493 
and Q494, until the operating state of the radio has been stored in EEPROM. PH3 then goes low, 
and all regulated voltages are removed. 
						

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3-4Controller Theory of Operation: Controller
The microprocessor reset line (pin 94) can be controlled directly by the digital 3.3 V regulator (U320 
pin 7), the microphone jack (part of accessory connector J471) via Q472 and Q471, and the 
microprocessor itself. U320 pulls the reset line low if the digital 3.3 V source loses regulation. This 
prevents possible MOS latch-up or overwriting of registers in the microprocessor because the reset 
line is higher in voltage than the microprocessor VDD ports (U401 pins 12, 39, 59, 88). The 
microprocessor can drive the reset line low if it detects a fault condition such as an expired watchdog 
timer, software attempting to execute an infinite loop, unplanned hardware inputs, static discharge, 
etc. Finally, the Q471 can pull the reset line low during use of the programming cable and CPS by 
the application of a sufficiently negative voltage to the microphone connector tip contact (J471 pin 4), 
however this reset method is not utilized.
3.1.1.8  Boot Mode Control
When power-up reset occurs, the microprocessor will boot into either normal or flash mode 
depending on the logic level of ports MODA (U401 pin 58) and MODB (pin 57). The Flash Adapter is 
a programming accessory which provides negative 9 volts dc via a 1K resistor to microphone 
connector J471 pin 4. This turns on Q471 and Q472 via D471 and VR472, pulling MODA and MODB 
low and allowing booting in the flash mode by cycling power to reset the radio. Software upgrades 
can then performed by loading the new software code into Flash ROM U404.
3.1.1.9  Microprocessor 7.3975 MHz Clock
The 7.3975 MHz clock signal (uP_CLK) is provided from the ASFIC_CMP (U451 pin 28).  Upon 
startup the 16.8MHz crystal provides the signal to the ASFIC_CMP, which sends out the uP_CLK at 
3.8MHz until a steady-state condition is reached and the clock is increased to 7.3975MHz for the 
microprocessor.
3.1.1.10 Battery Gauge
Various battery types are available having different capacities. The different battery types contain 
internal resistors connected from the BATT_CHARGE contact to ground (which is routed to the 
microprocessor as BATT_DETECT). A voltage divider is formed with R255 producing a different DC 
voltage for each battery type, which is read by microprocessor port PE2 (pin 65). This allows the 
software to recognize the battery chemistry being used and adjust the battery gauge for best 
accuracy.
3.1.2 Audio Circuitry
3.1.2.1  Transmit and Receive Low-Level Audio Circuitry
The majority of RX and TX audio processing is performed by U451, the Audio Filter IC 
(ASFIC_CMP), which provides the following functions:
• Tone PL/Digital PL encode and decode filtering
• Tone PL/Digital PL rejection filter in RX audio path
• TX pre-emphasis amplifier
• TX audio modulation limiter
• Post-limiter (splatter) filter
• TX deviation adjust (digitally-controlled attenuators)
• Programmable microphone gain attenuator
• RX audio volume control (digitally controlled attenuator)
• Carrier squelch adjustment (digitally controlled attenuator)
• Microprocessor output port expansion 
						

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Controller Theory of Operation: Controller3-5
• 2.5 volt dc reference source
• Microprocessor clock generation (from the 16.8 MHz reference oscillator input)
The parameters of U451 that are programmable are selected by the microprocessor via the CLOCK 
(U451 pin 21), DATA (U451 pin 22) and chip enable (U451 pin 20) lines.
RX audio buffer U510 amplifies the audio level from the DEMOD output of the IFIC before being 
applied to the audio filter IC input (DISC, U451 pin 2). The buffer is DC coupled to avoid corruption of 
low-frequency data waveforms such as DPL. Because such waveforms are polarity sensitive, this 
buffer is configured as a single-stage inverting amplifier (U510-1 only) for VHF models where high-
side first injection is used, or is configured as a two-stage non-inverting amplifier (U510-1 and -2) for 
UHF models using low-side first injection. The gain of the buffer is 1.5 times or 3.5 dB.
U480 and associated components are not used. Stage U480-1 is bypassed by jumper R487.
Volume adjustment is performed by a digital attenuator within U451. The volume control (10KO, part 
of S444) is connected to D_3.3 V and ground via R506 and R507. When the volume control is 
rotated, it varies the dc voltage applied to microprocessor A/D input port PE1 (U401 pin 66) between 
approximately 0 volts dc at minimum volume to 3.3 volts dc at maximum volume. Depending on this 
voltage, the appropriate setting of the digital volume attenuator is selected. This technique is less 
susceptible to noise than a conventional analog volume control.
3.1.2.2  Audio Power Amplifier
The audio power amplifier IC U490 amplifies receiver audio from U451 pin 41 to a level sufficient to 
drive a loudspeaker. U490 is a bridge amplifier delivering 3.46 volts rms between pins 5 and 8 
without distortion, which is sufficient to develop 500 milliwatts of audio power into the internal 24 ohm 
speaker or an external 24 ohm load. The audio power amplifier is muted whenever speaker audio is 
not required to reduce current drain. The audio amp is muted when U451 pin 14 is low. When U451 
pin 14 is high, U490 pin 1 is pulled low by Q490, enabling the audio amplifier. 
Because the power amplifier is a bridge-type, neither speaker terminal is grounded. Care should be 
taken that any test equipment used to measure the speaker audio voltage does not ground either 
speaker output terminal, otherwise damage to the audio power amplifier IC may result. When a 24-
ohm load resistor is used it should be connected between the tip and the sleeve of accessory jack 
J471 (3.5mm port), never to ground. External SPKR plug insertion mechanically disconnects the 
internal speaker. Voltage measurements using test equipment that is not isolated from ground may 
be made from one side of the speaker or load resistor (either the tip or the sleeve of J471) to chassis 
ground, in which case the voltage indicated will be one half of the voltage applied to the speaker or 
load resistor. The Motorola RLN4460 Portable Test Set and AAPMKN4004 Programming Test Cable 
provide the proper interface between the radios ungrounded audio output and ground-referenced 
test equipment.
3.1.2.3  Internal Microphone Audio Voice Path
Microphone audio from internal microphone is routed from J470-1 via C475, L471, and C470 to the 
ASFIC_CMP mic audio input (MICINT, U451 pin 46). During transmit, Q470 is turned on by a low at 
U451 pin 35, providing dc bias for the internal MIC via R478.  External MIC plug insertion 
mechanically disconnects the internal microphone. External MIC audio is coupled through L471 and 
C470 to the mic audio input.  An input level of 10 mV at J471 pin 4 produces 200 mV at the output of 
U451 pin 40, which corresponds to 60% deviation.  
						

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3-6Controller Theory of Operation: Controller
3.1.2.4  PTT Circuits
The internal side-mounted PTT switch (S441) is sensed directly by microprocessor port PJ0 (U401 
pin 71).  External mic PTT is sensed by measuring the current drawn through the accessory 
connector (J471-4) by the mic cartridge (which is in series with the accessory PTT switch). This 
current is drawn through the base (pin 5) and emitter (pin 4) of a transistor in Q470, causing its 
collector (pin 3) to supply a logic-high to microprocessor port PJ1 (pin 72).
3.1.2.5  VOX Operation
VOX audio accessories do not have a PTT switch. Instead, the mic cartridge is wired directly from 
J471-4 to ground. If the radio has been programmed for VOX operation and the VOX accessory is 
plugged in prior to turning the radio on, the current drawn by the cartridge will turn on Q470 (pins 3-
4-5) and a logic high will be seen at port PJ1 at turn-on. The microprocessor then assumes VOX 
operation, with PTT controlled by the presence of audio at the mic cartridge. A dc voltage 
proportional to the audio level at the input of the ASFIC_CMP (U451 pin 46) is fed to an A/D input of 
microprocessor U401 (pin 62). During VOX operation, PTT is activated when the dc level exceeds a 
preset threshold.
3.1.2.6  Battery Charging Through Microphone Jack
A wall-type charging power supply may be connected to the 2.5 mm microphone jack (part of 
accessory connector J451). The voltage present at the tip contact (pin 4) is applied to the center 
charging contact of the battery via diode D470. Another diode, internal to the battery, applies this 
voltage to the (+) battery terminal. Only the recommended charger and battery type should be 
charged in this manner. 
Different battery types contain internal resistors connected from the BATT_CHARGE contact to 
ground, which is routed to the microprocessor as BATT_DETECT. A voltage divider is formed with 
R255 producing a DC voltage which is read by microprocessor port PE2 (pin 65). This allows the 
software to recognize the battery chemistry being used and adjust the battery gauge for best 
accuracy. The value of R255 is chosen so that the voltage at the BATT_CHARGE node (cathode of 
D470) is never low enough to turn on the EXT_MIC_PTT sense transistor (part of Q470).
3.1.2.7  Programming and Flashing Through Microphone Jack
The ring contact on the 2.5 mm microphone jack is used for reading, programming or re-flashing the 
radio using CPS. This contact (J471 pin 6) is routed to ports PD0_RXD (data into uP, pin 97) and 
PD1_TXD (data out of uP, pin 98). Transistor Q410 isolates the input and output functions by 
allowing PD1 to pull the line low, but does not affect incoming data from being read by port PD0.
To re-flash the radio (overwrite the software in the Flash ROM with new software), the radio must 
power up in the boot mode. This is accomplished by using a flash adapter accessory, which provides 
SCI communication with the programming ring contact (J471 pin 6) and also allows a negative 
voltage (negative 9 volts dc via a 1K resistor) to be applied to the tip contact (J471 pin 4). This 
voltage is sufficient to turn on the base-emitter junction (pins 1 and 2) of Q472 via L471, D471, 
VR472 and R471. Pin 6 of Q472 goes high, turning on Q471 (pins 3 and 4) and pulling the 
BOOT_ENA line (ports MODA and MODB of the microprocessor) low. Cycling power generates a 
reset which causes the radio to boot in the flash mode. 
						

							Chapter 4 136-162 MHz VHF Theory Of Operation
4.1 Introduction
This chapter provides a detailed theory of operation for the radio components. Schematic diagrams 
for the circuits described in the following paragraphs are located in Chapter 7 of this manual.
4.2 VHF Receiver
The VHF receiver covers the range of 136-162 MHz and provides switchable IF bandwidth for use 
with 12.5 kHz or 20/25 kHz channel spacing systems. The receiver is divided into two major blocks as 
shown in Figure 4-1.
•Front End
• Back End
Figure 4-1.  VHF Receiver Block Diagram
4.2.1 Receiver Front-End
Incoming RF signals from the antenna are first routed through the harmonic filter and antenna switch, 
part of the transmitter circuitry, before being applied to the receiver front end. The receiver front end 
consists of a preselector filter, RF amplifier, an interstage filter, and a double-balanced first mixer.
The preselector filter is a fixed-tuned 4-pole design using discrete elements (L1-L4 and C1-C9) in a 
series/shunt resonator configuration. It has a 3 dB bandwidth of 43 MHz, an insertion loss of 2 dB and 
image attenuation of 37 dB at 226 MHz, with increasing attenuation at higher frequencies. Diode CR1 
protects the RF amplifier by limiting excessive RF levels.
The output of the filter is matched to the base of RF amplifier Q21, which provides 18 dB of gain and 
a noise figure of 2 dB. Operating voltage is obtained from the 5R source, which is turned off during 
transmit to reduce dissipation in Q21. Current mirror Q22 maintains the operating current of Q21 
DemodulatorCrystal
Filter  1st Mixer RF
AmpIF
Amp Preselector
FilterInterstage
 Filter
Recovered Audio
RSSI
RX from
Antenna Switch
Inj Filter
First LO
from Synthesizer
Ceramic
ResonatorCer FltrSwitching4E
6E6GBW_SEL 
						

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4-2136-162 MHz VHF Theory Of Operation: VHF Receiver
constant at 6.2 mA regardless of device and temperature variations, for optimum dynamic range and 
noise figure.
The output of the RF amplifier is applied to the interstage filter, a fixed-tuned 3-pole series-coupled 
resonator design having a 3 dB bandwidth of 54 MHz and insertion loss of 1.8 dB. This filter has an 
image rejection of 40 dB at 226 MHz, with increasing attenuation at higher frequencies.
The output of the interstage filter is connected to the passive double-balanced mixer consisting of 
components T41, T42, and CR41. This mixer has a conversion loss of 7 dB. High-side injection from 
the frequency synthesizer is filtered by L40-L41 and C40-C44 to remove second harmonic energy 
that may degrade half-IF spurious rejection performance. The injection filter has a 3 dB bandwidth of 
52 MHz and an insertion loss of 1.5 dB. The filtered injection signal is applied to T42 at a level of +6 
dBm.
The mixer output is applied to a diplexer network (L51-L52, C51, R51) which matches the 44.85 MHz 
IF signal to crystal filter FL51, and terminates the mixer into 50Ω at all other frequencies
4.2.2 Receiver Back-End
The receiver back end is a dual conversion design. High IF selectivity is provided by FL51, a 4-pole 
fundamental mode 44.85 MHz crystal filter with a minimum 3 dB bandwidth of + 6.7 kHz, a maximum 
20 dB bandwidth of ±12.5 kHz, and a maximum insertion loss of 3.5 dB. The output is matched to IF 
amplifier stage Q51 by L53 and C93. Q51 provides 16 dB of gain and a noise figure of 1.8 dB. The dc 
operating current is 1 mA. The output of Q51 is applied to the input of the receiver IFIC U51. Diode 
CR51 limits the maximum RF level applied to the IFIC.
The IFIC is a low-voltage monolithic FM IF system incorporating a mixer/oscillator, two limiting IF 
amplifiers, quadrature detector, logarithmic received signal strength indicator (RSSI), voltage 
regulator and audio and RSSI op amps. The second LO frequency, 44.395 MHz, is determined by 
Y51. The second mixer converts the 44.85 MHz high IF frequency to 455 kHz.
Additional IF selectivity is provided by two ceramic filters, FL52 (between the second mixer and IF 
amp) and FL53 or FL54 (between the IF amp and the limiter input). The wider filter FL53 is used for 
20/25 kHz channel spacing, and the narrower filter FL54 is used for 12.5 kHz channels. When the 
BW_SEL line is high, the two upper diodes in packages D51 and D52 are forward biased, selecting 
FL53 for 20/25 kHz channels. When the BW_SEL line is low, the two lower diodes in packages D51 
and D52 are forward biased, selecting FL54 for 12.5 kHz channels.
Ceramic resonator Y70 provides phase vs. frequency characteristic required by the quadrature 
detector, with 90 degree phase shift occurring at 455 kHz. Buffer Q70 provides a lower driving 
impedance from the limiter to the resonator, improving the IF waveform and lowering the distortion of 
the recovered audio signal. The recovered audio level at the DEMOD output is 120 mV rms (25 kHz 
channel, 3 kHz deviation) or 60 mV rms (12.5 kHz channel, 1.5 kHz deviation). An additional RSSI 
output provides a DC voltage level that is proportional to RF signal level. This voltage is measured by 
an A/D converter contained in the microprocessor (PE4_AN4, U401 pin 63).FL52 FL53 FL54
Number of Elements:466
Insertion Loss: 4 dB 4 dB 4 dB
6 dB Bandwidth:15 kHz15 kHz9 kHz
50 dB Bandwidth: 30 kHz 30 kHz 22 kHz
Stopband Rejection:27 dB47 dB47 dB 
						

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136-162 MHz VHF Theory Of Operation: VHF Transmitter 4-3
4.3 VHF Transmitter
The VHF transmitter covers the range of 136-162 MHz. Depending on model, the output power of the 
transmitter is either switchable on a per-channel basis between high power (5 watts) and low power 
(1 watt), or is factory preset to 2 watts. The transmitter is divided into four major blocks as shown in 
Figure 4-2.
• Power Amplifier
• Harmonic Filter
• Antenna Matching Network
• Power Control
Figure 4-2.  VHF Transmitter Block Diagram
4.3.1 Transmit Power Amplifier
The transmitter power amplifier has three stages of amplification. The first stage, Q100, operates in 
Class AB from the 5T source. It provides 13 dB of gain and an output of 20 mW. The current drain is 
typically 25mA. Components C105-C107 and L103 match the output of Q100 to the 50Ω input of the 
module U110.
U110 is a two stage Silicon MOS FET power amplifier module. Drain voltage is obtained from UNSW 
B+ after being routed through current-sense resistor R150 in the power control circuit. The output 
power of the module is controlled by varying the DC gate bias on U110 pin 2 (VGG).
4.3.2 Antenna Switch
The antenna switch consists of two pin diodes, D120 and D121. In the receive mode, both diodes are 
off. Signals applied at the antenna or at jack J140 are routed, via the harmonic filter, through network 
C122-C124 and L121, to the receiver input. In the transmit mode, Q170 is on and TXB+ is present, 
forward-biasing both diodes into conduction. The diode current is 50 mA, set by R120-R122. The 
transmitter RF from U110 is routed through D120, and via the harmonic filter to the antenna jack. 
D121 conducts, shunting RF power and preventing it from reaching the receiver. L121 is selected to 
appear as a 1/4 wave at VHF, so that the low impedance of D121 appears as a high impedance at the 
junction of D120 and the harmonic filter input. This provides a high series impedance and low shunt 
impedance divider between the power amplifier output and receiver input.
4.3.3 Harmonic Filter
The harmonic filter consists of components C130-C136 and L130-L132. The harmonic filter is a 
seven-pole elliptical low-pass configuration, optimized for low insertion loss, with a 3 dB frequency of 
approximately 180 MHz and typically less than 0.8 dB insertion loss in the passband.
Power Control
Harmonic Filter
Antenna
Matching
NetworkPower Amplifier Module U110Q100TX_INJ
(From VCO)5TVDD
VGG TX_ENA
PWR_SET
USWB+
RX_IN
(To Receiver)
Antenna
SwitchJ140 Antenna
Jack
Antenna 
						

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4.3.4 Antenna Matching Network
The harmonic filter presents a 50 Ω impedance to antenna jack J140. A matching network, made up 
of C140-C141 and L140, is used to match the antenna impedance to the harmonic filter. This 
optimizes the performance of the transmitter and receiver into the impedance presented by the 
antenna, significantly improving the antennas efficiency.
4.3.5 Power Control
The power control circuit is a dc-coupled amplifier whose output is the dc gate bias voltage (VGG) 
applied to the two stages of the RF power amplifier U110.
The output power of the transmitter is adjusted by varying the setting of the power-set DAC contained 
in the ASFICcmp IC (DACG, U451 pin 6). This PWR_SET voltage is applied to U150 pin 3.
Stage U150-2 compares the voltage drop across current sense resistor R150 to the voltage drop 
across resistor R151 caused by current flow through Q150, and adjusts its output (pin 7) to maintain 
equal voltages at pins 5 and 6. Thus the current flow through Q150, and hence its emitter voltage, is 
proportional to the current drawn by stage U110, which is in turn proportional to the transmitter output 
power. The emitter voltage of Q150 is applied to U150 pin 2, where it is compared to the power set 
voltage PWR_SET at pin 3. 
The output of U150 pin 1 is divided by R110 and R111 and applied as a gate voltage to the power 
amplifier U110. By varying this gate voltage as needed to keep the voltages at U150 pins 2 and 3 
equal, power is maintained at the desired setting. Excessive final current, for example due to antenna 
mismatch, causes a lowering of the voltage at U150 pin 6, an increased voltage at pin 2, and a 
lowering of the voltage at pin 1 and of the gate voltage VGG. This prevents damage to the final stage 
due to excessive current.
4.4 VHF Frequency Generation Circuitry
The frequency generation system, shown in Figure 4-3, is composed of two circuit blocks, the 
Fractional-N synthesizer IC U201, the VCO/Buffer IC U251, and associated circuitry. Figure 4-4 
shows the peripheral interconnect and support circuitry used in the synthesizer block, and Figure 4-5 
details the internal circuitry of the VCOBIC and its interconnections to the surrounding components. 
Refer to the schematic to identify reference designators.
The Fractional-N synthesizer is powered by regulated 5 V and 3 V provided by U310 and U330 
respectively. 5 V is applied to U201 pins 13 and 30, and 3 V is applied to pins 5, 20, 34 and 36. The 
synthesizer in turn generates a super-filtered 4.5 V supply (VSF, from pin 28) to power U251. In 
addition to the VCO, the synthesizer also interfaces with the logic and ASFICcmp circuits. 
Programming for the synthesizer is accomplished through the microprocessor SPI_DATA_OUT, 
SPI_CLK, and SYNTH_CS (chip select) lines (U409 pins 100, 1 and 47 respectively). A logic high 
(3 V) from U201 pin 4 indicates to the microprocessor that the synthesizer is locked.