JBL Ms 8 Service Manual

							
Connection Diagram
201023056-Lead TSOT
NS Package Number MK06A
Ordering Information
Order Number Package Type NSC Package Drawing Package Marking Supplied As
LM2734XMK
TSOT-6MK06A SFDB
1000 Units on Tape and Reel
LM2734YMK SFEB1000 Units on Tape and Reel
LM2734XMKX SFDB3000 Units on Tape and Reel
LM2734YMKX SFEB3000 Units on Tape and Reel
* Contact the local sales office for the lead-free package.
Pin Description
Pin Name Function
1 BOOSTBoost voltage that drives the internal NMOS control switch. A
bootstrap capacitor is connected between the BOOST and SW
pins.
2 GNDSignal and Power ground pin. Place the bottom resistor of the
feedback network as close as possible to this pin for accurate
regulation.
3 FBFeedback pin. Connect FB to the external resistor divider to set
output voltage.
4 ENEnable control input. Logic high enables operation. Do not allow
this pin to float or be greater than V
IN+ 0.3V.
5V
INInput supply voltage. Connect a bypass capacitor to this pin.
6 SWOutput switch. Connects to the inductor, catch diode, and
bootstrap capacitor.
LM2734
www.national.com 2
 
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70  
						

							
ASAHI KASEI 
 [AK4359] 
MS0289-E-00   2004/02 
  - 1 - 
 
       
 
 
 
 
GENERAL DESCRIPTION The AK4359 is eight channels 24bit DAC corresponding to digital audio system. Using AKMs advanced 
m ulti bit architecture for its m odulator the AK4359 delivers a w ide dynam ic range w hile preserv ing 
linearity for improved THD+N perform ance. The AK4359 has single end SCF outputs, increasing 
performance for systems with excessive clock jitter. The AK4359 accepts 192kHz PCM data, ideal for a 
wide range of applications including DVD-Audio. 
FEATURES 
 Sampling Rate Ranging from 8kHz to 192kHz  24Bit 8 times Digital Filter with Slow roll-off option  THD+N:   -94dB  DR, S/N:  106dB  High Tolerance to Clock Jitter  Single Ended Output Buffer with 2nd order Analog LPF  Digital De-emphasis for 32, 44.1 & 48kHz sampling  Zero Detect function  Channel Independent Digital Attenuator (Linear 256 steps)  3-wire Serial and I2
C Bus 
P I/F for mode setting  I/F format: MSB justified, LSB justified (16bit, 20bit, 24bit), I 2
S, TDM  Mast er clock:   256fs, 384f s, 512fs or 768fs or 1152f s (N orm al Speed Mode) 
128fs, 192fs, 256fs or 384fs (Double Speed Mode) 
128fs or 192fs (Quad Speed Mode) 
 Power Supply: 4.5 to 5.5V   30pin VSOP Package 
 
 
 
 
 
 
 
 
 
 
 
 
 
 SCF DAC
DATTDZF 
LOUT1 
SCF DAC
DATTROUT1 
SCF DAC
DATTLOUT2 
SCF DAC
DATTROUT2 
SCF DAC
DATTLOUT3 
SCF DAC
DATTROUT3  Audio
I/F Control
Register AK4359 MCLK 
LRCK 
BICK 
3-wire 
or I2C SDTI1 
SDTI2 
SDTI3 
PCM SCF DAC
DATTLOUT4 
SCF DAC
DATTROUT4  SDTI4 LPF
LPF 
LPF 
LPF 
LPF 
LPF 
LPF 
LPF 
 192kHz 24-Bit 8ch DAC
AK4359

 
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71  
						

							
ASAHI KASEI 
 [AK4359] 
MS0289-E-00   2004/02 
  - 2 - 
 Ordering Guide 
 
    AK4359VF    -40 

 +85C      30pin VSOP 
    AKD4359     Evaluation Board for AK4359 
 
 
  Pin Layout  
 
   

 6  5 
4 
3  2  1 
MCLK  BICK
LRCK
SDTI1 RSTB 
SMUTE/CSN/CAD0 
7 
DIF0/CDTI/SDA 8  DZF1 
DZF2 
AVDD 
AVSS 
VCOM 
LOUT1 
ROUT1 
P/S AK4359
Top 
View  
10  9 
SDTI2  SDTI3
SDTI4 11 
DIF1 12  LOUT2 
ROUT2 
LOUT3 
ROUT3 
25 26
27 28 29 30
24
23
21 22
20
19
ACKS/CCLK/SCL 
DEM0 13  DVDD 14  LOUT4 
ROUT4 
18
17
DVSS 15  DEM1/I2C 
16
 
 
 
 
 

 
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72  
						

							
ASAHI KASEI 
 [AK4359] 
MS0289-E-00   2004/02 
  - 4 - 
PIN/FUNCTION 
 
No. Pin Name  I/O  Function  1  MCLK 
I  Master Clock Input Pin 
   An external TTL clock should be input on this pin.  2  BICK 
I  Audio Serial Data Clock Pin 3  SDTI1 
I  DAC1 Audio Serial Data Input Pin 4  LRCK 
I  L/R Clock Pin 5  RSTB 
I  Reset Mode Pin 
   When at “L”, the AK4359 is in the reset mode. The AK4359 should always be reset upon power-up.  SMUTE 
I  Soft Mute Pin in parallel mode 
“H”: Enable, “L”: Disable  CSN 
I  Chip Select Pin in serial 3-wire mode 6 
CAD0  I  Chip Address Pin in serial I2C mode  ACKS 
I  Auto Setting Mode Pin in parallel mode 
   “L”: Manual Setting Mode,    “H”: Auto Setting Mode  CCLK 
I  Control Data Clock Pin in serial 3-wire mode  7 
SCL    Control Data Clock Pin in serial I2C mode  DIF0 
I  Audio Data Interface Format Pin  in parallel mode  CDTI 
I  Control Data Input Pin in serial 3-wire mode   8 
SDA  I/O  Control Data Pin in serial I2C mode  9  SDTI2 
I  DAC2 Audio Serial Data Input Pin  10  SDTI3 
I  DAC3 Audio Serial Data Input Pin  11  SDTI4 
I  DAC4 Audio Serial Data Input Pin  12  DIF1 
I  Audio Data Interface Format Pin 13  DEM0 
I  De-emphasis Filter Enable Pin 14 DVDD   
Digital Power  Supply Pin, +4.5
+5.5V 
15  DVSS 
  Digital Ground Pin I2C 
I  Control Mode Select Pin in serial mode 
“L”: 3-wire Serial, “H”: I 2
C Bus  16 
DEM1  I  De-emphasis Filter Enable Pin in parallel mode 17  ROUT4 
O  DAC4 Rch Analog Output Pin 18  LOUT4 
O  DAC4 Rch Analog Output Pin 19  ROUT3 
O  DAC3 Rch Analog Output Pin 20  LOUT3 
O  DAC3 Rch Analog Output Pin 21  ROUT2 
O  DAC2 Rch Analog Output Pin 22  LOUT2 
O  DAC2 Rch Analog Output Pin 23 P/S 
I 
Parallel/Serial Select Pin                                            (Internal pull-up pin) 
   “L”: Serial control mode, “H”: Par allel control mode   24  ROUT1 
O  DAC1 Rch Analog Output Pin 25  LOUT1 
O  DAC1 Lch Analog Output Pin 26  VCOM 
O  Common Voltage Pin, AVDD/2 
      Normally connected to AVSS with a 0.1

F ceramic capacitor in parallel with 
a 10
F electrolytic cap. 
 27  AVSS 
-  Analog Ground Pin 28 AVDD  - 
Analog Power Supply Pin, +4.5
+5.5V 
29  DZF2 
O  Data Zero Input Detect Pin 30  DZF1 
O  Data Zero Input Detect Pin Note: All input pins except pull-up pin should not be left floating. 
 
 

 
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73  
						

							
Philips SemiconductorsProduct speciÞcation
Dual 4-channel analog multiplexer,
demultiplexer 74HC4052; 74HCT4052
FEATURES
 Wide analog input voltage range from 5 V to +5 V
 Low ON-resistance:
Ð80 (typical) at V
CC
V
EE = 4.5 V
Ð70 (typical) at V
CC
V
EE = 6.0 V
Ð60 (typical) at V
CC
V
EE = 9.0 V
 Logic level translation: to enable 5 V logic to
communicate with ±5 V analog signals
 Typical Òbreak before makeÓ built in
 Complies with JEDEC standard no. 7A
 ESD protection:
Ð HBM EIA/JESD22-A114-B exceeds 2 000 V
Ð MM EIA/JESD22-A115-A exceeds 200 V.
 Specified from 40 °C to +85 °C and 40 °C to +125 °C.
APPLICATIONS
 Analog multiplexing and demultiplexing
 Digital multiplexing and demultiplexing
 Signal gating. DESCRIPTION
The 74HC4052 and 74HCT4052 are high-speed Si-gate
CMOS devices and are pin compatible with the
HEF4052B. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC4052 and 74HCT4052 are dual 4-channel
analog multiplexers or demultiplexers with common select
logic. Each multiplexer has four independent
inputs/outputs (pins nY0 to nY3) and a common
input/output (pin nZ). The common channel select logics
include two digital select inputs (pins S0 and S1) and an
active LOW enable input (pin
E). When pinE = LOW, one
of the four switches is selected (low-impedance ON-state)
with pins S0 and S1. When pin
E = HIGH, all switches are
in the high-impedance OFF-state, independent of pins S0
and S1.
V CC  and GND are the supply voltage pins for the digital
control inputs (pins S0, S1, and
E). The V CC to GND
ranges are 2.0 V to 10.0 V for 74HC4052 and
4.5 V to 5.5 V for 74HCT4052. The analog inputs/outputs
(pins nY0 to nY3 and nZ) can swing between V CC as a
positive limit and V EE as a negative limit. V
CC
V
EE  may
not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, V EEis
connected to GND (typically ground).
FUNCTION TABLE
Note
1. H = HIGH voltage level L = LOW voltage level
X = donÕt care. INPUT
(1)
CHANNEL BETWEEN
ES1S0
L L L nY0 and nZ
L L H nY1 and nZ
L H L nY2 and nZ
L H H nY3 and nZ
H X X none
 
 MS-8                      
 
 
 
74  
						

							
Philips SemiconductorsProduct speciÞcation
Dual 4-channel analog multiplexer,
demultiplexer 74HC4052; 74HCT4052
PINNING PIN SYMBOL DESCRIPTION1 2Y0 independent input or output
2 2Y2 independent input or output
3 2Z common input or output
4 2Y3 independent input or output
5 2Y1 independent input or output
6
E enable input (active LOW)
7V EE negative supply voltage
8 GND ground (0 V)
9 S1 select logic input
10 S0 select logic input
11 1Y3 independent input or output
12 1Y0 independent input or output
13 1Z common input or output
14 1Y1 independent input or output
15 1Y2 independent input or output
16 V CC positive supply voltage
handbook, halfpage
4052
MNB039
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2Y0
2Y2
2Z
2Y3
2Y1
E
V EE
GND S1 S0 1Y3 1Y0
1Z 1Y1 1Y2
V
CC
Fig.1 Pin configuration DIP16, SO16 and
(T)SSOP16.
Fig.2  Pin configuration DHVQFN16.
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
001aac117
4052
V CC (1)
V EE S0
E 1Y3
2Y1 1Y0 2Y3 1Z 2Z 1Y1
2Y2 1Y2
GND
S1 2Y0
V
CC
Transparent top view
710
611
512
413
314
215
89
116
terminal 1
index area
 
 MS-8                      
 
 
 
75  
						

							
Philips SemiconductorsProduct speciÞcation
Dual 4-channel analog multiplexer,
demultiplexer 74HC4052; 74HCT4052
handbook, halfpage
MNB040 
4 2
5 1
11 15
14
12
13
3
6 9 1Z
S0
S1
E 2Z2Y3 2Y2 2Y1 2Y0
1Y3
1Y2 1Y1 1Y0
10
Fig.3  Logic symbol.
handbook, halfpage
MNB041
11 15 14 12 4
2
5
9
1
10 0
6G4
MDX0
3
4 
×
1
3 2 1
0
13 3
Fig.4  IEC logic symbol.
handbook, full pagewidth
MNB042
1 - OF - 4
DECODERLOGIC
LEVEL
CONVERSION
7
8
VEE
GND V
CC
12 13
16
3
14
15
11
10
9
6
S0
S1
E
1
5
2
1Y0 1Z
2Z 1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
4
Fig.5  Functional diagram.
 
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1
LTC1694
SMBus/I2C Accelerator*
nImproves SMBus Rise Time Transition
nEnsures Data Integrity with Multiple Devices
on  the SMBus
nImproves Low State Noise Margin
nAuto Detect Low Power Standby Mode
nWide Supply Voltage Range: 2.7V to 6V
nLow Profile (1mm) SOT-23 (ThinSOTTM) PackageThe LT C
¨1694 is a dual SMBus active pull-up designed to
enhance data transmission speed and reliability under all
specified SMBus loading conditions. The LTC1694 is also
compatible with the Philips I
2CTM Bus.
The LTC1694 allows multiple device connections or a
longer, more capacitive interconnect, without compro-
mising slew rates or bus performance, by using two
bilevel hysteretic current source pull-ups.
During positive bus transitions, the LTC1694 current
sources provide 2.2mA to quickly slew the SMBus line.
During negative transitions or steady DC levels, the cur-
rent sources decrease to 275m A to improve negative slew
rate and improve low state noise margins. An auto detect
standby mode reduces supply current if both SCL and
SDA are high.
The LTC1694 is available in a 5-pin SOT-23 package,
requiring virtually the same space as two surface mount
resistors.
nNotebook and Palmtop Computers
nPortable Instruments
nBattery Chargers
nIndustrial Control Application
nTV/Video Products
nACPI SMBus Interface
LTC1694
V
CC
GND
VCC5V
C1
0.1µF
SMBus1
SMBus2
SCL
SDA
DEVICE 1
CLK
IN
CLK
OUT
SMBus
DATA
IN
DATA OUT
DEVICE N
1694 TA01
CLK IN
CLK
OUTDATA IN
DATA OUT
, LTC and LT are registered trademarks of Linear Technology Corporation.ThinSOT is a trademark of Linear Technology Corporation.
I2C is a trademark of Philips Electronics N.V.
*U.S. Patent No. 6,650,174
VCC = 5V 1m s/DIV
CLD = 200pF
fSMBus = 100kHz1694 TA02
Comparison of SMBus Waveforms for the LTC1694 vs Resistor Pull-Up
LTC1694
R
PULL-UP= 15.8k
FEATURESDESCRIPTIO
U
APPLICATIO  S
U
TYPICAL APPLICATIO
U
1V/DIV
 
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77  
						

							
2
LTC1694
1694fa
ORDER PARTNUMBER
LTC1694CS5
LTC1694IS5
(Note 1)
Supply Voltage (VCC) ................................................. 7V
SMBus1, SMBus2 Inputs ............ Ð 0.3V to (V
CC + 0.3V)
Operating Ambient Temperature Range
LTC1694C ............................................... 0 °C to 70 °C
LTC1694I ............................................ Ð 40° C to 85°C
Junction Temperature ........................................... 125 °C
Storage Temperature Range ................. Ð 65° C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300 °C
VCC  1
GND  2 NC  3 5  SMBus1
4  SMBus2
TOP VIEW
S5 PACKAGE
5-LEAD PLASTIC TSOT-23
TJMAX = 125 °C,  qJA = 256 °C/ WLTEE
LTA8
S5 PART MARKING
The l denotes specifications that apply over the full operating temperature r\
ange, otherwise specifications are at TA = 25 °C.
V
CC = 2.7V to 6V unless otherwise noted.
SYMBOL PARAMETER CONDITIONSMIN TYP MAX UNITS
VCCSupply Voltage Range 2.76V
ICCSupply Current SMBus1 = SMBus2 = Openl20 60 100mA
IPULL-UPPull-Up Current SMBus1 = SMBus2 = 0Vl125 275 350mA
Boosted Pull-Up Current Positive Transition on SMBus ( Figure 1)l1.0 2.2mA
Slew Rate = 0.5V/ ms, SMBus > V
THRES
VTHRESInput Threshold Voltage Slew Rate = 0.5V/ms (Figure 1)l0.4 0.65 0.9 V
SRTHRESSlew Rate Detector Threshold SMBus > VTHRESl0.2 0.5 V/ms
trSMBus Rise Time Bus Capacitance = 200pF (Note 2)l0.32 1.0ms
Standard Mode I2C Bus Rise Time Bus Capacitance = 400pF (Note 3)l0.30 1.0ms
fMAXSMBus Maximum Operating Frequency (Note 4)l100 kHz
Note 1:  Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:  The rise time of an SMBus line is calculated from (V
IL(MAX)  Ð
0.15V) to (V
IH(MIN) + 0.15V) or 0.65V to 2.25V. This parameter is
guaranteed by design and not tested. With a minimum pull-up current of
125 mA, a minimum boosted pull-up current of 1mA and a maximum input
threshold voltage of 0.9V:
Rise Time = [(0.9V Ð 0.65V)/125 mA + (2.25V Ð 0.9V)/1mA] ¥ 200pF
                 = 0.67 ms Note 3:
 The rise time of an I
2C bus line is calculated from VIL(MAX) to
V
IH(MIN) or 1.5V to 3V (with VCC = 5V). This parameter is guaranteed by
design and not tested. With a minimum boosted pull-up current of 1mA:
Rise Time = (3V Ð 1.5V) ¥ 400pF/1mA = 0.6 ms
Note 4:  This parameter is guaranteed by design and not tested.
ABSOLUTE    AXI   U    RATI  GS
W
WW
U
PACKAGE/ORDER I  FOR   ATIO
UU W
ELECTRICAL CHARACTERISTICS
Consult LTC Marketing for parts specified with wider operating temperatu\
re ranges.
 
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78  
						

							
3
LTC1694
1694fa
TEMPERATURE (¡C)
–50
PULL-UP CURRENT (µA)
350
325
300
275
250
225
200
175
150
125
100
050
75
1694 G01
–25 25
100125
VCC = 6V
VCC = 5V
VCC = 2.7V
TEMPERATURE (¡C)
–50
BOOSTED PULL-UP CURRENT (mA)
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
050
75
1694 G02
–25 25
100125
VCC = 6V
VCC = 5V
VCC = 2.7V
Boosted Pull-Up Current vs
SMBus Voltage
TEMPERATURE (¡C)
–50
INPUT THRESHOLD VOLTAGE (V)
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
050
75
1694 G04
–25 25
100125
VCC = 6V
VCC = 2.7V
VCC = 5V
TEMPERATURE (¡C)
–50
SLEW RATE DETECTOR THRESHOLD (V/µs)
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0 050
75
1694 G05
–25 25
100125
VCC = 6V
VCC = 2.7VVCC = 5V
Slew Rate Detector Threshold
Standby Mode Supply Current
TEMPERATURE (¡C)
–50
SUPPLY CURRENT (µA)
100
1694 G06
050
100
90
80
70
60
50
40
30
20 – 25 25 75 125
VCC = 6V
VCC = 2.7VVCC = 5V
Pull-Up Current at SMBus = 0V Boosted Pull-Up Current
SMBus VOLTAGE (V)
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0 35
LT1694 G03
12467
BOOSTED PULL-UP CURRENT (mA)
VCC = 6V
VCC = 5V
VCC = 2.7V
Input Threshold Voltage
TYPICAL PERFOR   A  CE CHARACTERISTICS  
UW
VCC (Pin 1):
 Power Supply Input. VCC can range from 2.7V
to 6V and requires a 0.1 mF bypass capacitor to GND.
GND (Pin 2):  Ground.
NC (Pin 3):  No Connection. SMBus2 (Pin 4):
 Active Pull-Up for SMBus.
SMBus1 (Pin 5):  Active Pull-Up for SMBus.
UUU
PI   FU  CTIO  S
 
 MS-8                       
 
 
79