JBL Ms 8 Service Manual

							
Philips Semiconductors Product speciÞcation
Octal buffer/line driver with 30W series termination
resistors; 5 V input/output tolerant; 3-state 74LVC2244A
FEATURES
·
5 V tolerant inputs/outputs for interfacing with 5 V logic
· Wide supply voltage range of 1.2 to 3.6 V
· CMOS low power consumption
· Direct interface with TTL levels
· Integrated 30 W termination resistors. DESCRIPTION
The 74LVC2244A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. In
3-state operation, outputs can handle 5 V. These features
allow the use of these devices as translators in a mixed
3.3/5 V environment.
The 74LVC2244A is an octal non-inverting buffer/line
driver with 3-state outputs. The 3-state outputs are
controlled by the output enable inputs 1
OE and 2OE. A
HIGH on n
OE causes the outputs to assume a
high-impedance OFF-state. Schmitt-trigger action at all
inputs makes the circuit highly tolerant for slower input rise
and fall times. The 74LVC2244A is designed with 30 W
series termination resistors in both HIGH and LOW output
stages to reduce line noise.
QUICK REFERENCE DATA
Ground = 0 V; T
amb=25 °C; tr=tf£ 2.5 ns.
Note
1. C
PDis used to determine the dynamic power dissipation (PDin mW).
P
D=CPD´ VCC 2´
fi+ S(CL´ VCC 2´
fo) where:
f
i= input frequency in MHz;
f
o= output frequency in MHz;
C
L= output load capacitance in pF;
V
CC= supply voltage in Volts;
S (C
L´ VCC 2´
fo) = sum of the outputs.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
t
PHL/tPLHpropagation delay 1Anto 1Yn; 2Anto 2YnCL= 50 pF; VCC= 3.3 V 4.0 ns
C
Iinput capacitance 5.0 pF
C
PDpower dissipation capacitance per buffer VI= GND to VCC; note 1 25 pF
 
 MS-8                       
 
 
90  
						

							
Philips SemiconductorsProduct speciÞcation
Octal buffer/line driver with 30W series termination
resistors; 5 V input/output tolerant; 3-state 74LVC2244A
Fig.1  Pin configuration.
handbook, halfpage1OE
1A 0
2Y 0
1A 1
2Y 1
1A 2
2Y 2
1A 3
2Y 3
GND V
CC
2OE
1Y 0
2A 0
2A 1
1Y 2
1Y
1
2A 2
1Y 3
2A 31
2
3
4 5
6
7
8
9
10 11
12 20
19
18
17
16
15
14
13
2244
MNA357
handbook, halfpage
1A 3
1A
2
1A
1
1A
0
2
4
6
8
1
1Y 0
1Y1 18
16
14
12
1Y
2
1Y3
1OE
MNA360
2A3
2A
2
2A
1
2A
0
17
15
13
11
19
2Y 0
2Y1 3
5
7
9
2Y
2
2Y3
2OE
Fig.2  Functional diagram.Fig.3  IEC logic symbol.
handbook, halfpage
12 14
2
4
6
8 18
16
1
EN
MNA359
9 7
17
15
13
11 3
5
19
EN
 
 MS-8                       
 
 
91  
						

							
 
 MS-8                      
 
 
 
92  
						

							
ABC D
DCBA
ED0ED1ED2ED3ED4ED5ED6ED7ED8ED9ED10ED11ED12ED13ED14ED15
EA2EA3EA4EA5EA6EA7EA8EA9EA10EA11EA12EA13EA14EA15EA16EA17EA18EA19EA20EA21
BE0#BE1#CLKOSDRAS#SDWE#SDCAS#
JTAG_TRSTJTAG_EMU0JTAG_EMU1JTAG_TDIJTAG_TDOJTAG_TCKJTAG_TMSDSP_RXD
I2S_OUT0I2S_OUT1I2S_OUT2I2S_OUT3
I2S_IN0I2S_IN1I2S_IN2I2S_IN3DSP_TXD
GP14GP8GP0
CE0#CE1#BE2#BE3#
ED16ED17ED18ED19ED20ED21ED22ED23ED24ED25ED26ED27ED28ED29ED30ED31
1TP1 TEST POINT
R2344.7k
R18710k
1 TP18
TEST POINT
1234
5678
RN3
33 x 4
1TP17
TEST POINT
1234
5678
RN5
33 x 41234
5678
RN8
33 x 4
1 TP19
TEST POINT
R276
3.3k
R251
5.1k
R201
10k
1 TP20
TEST POINT
R278 1k
R275
1k
R198
10k
1234
5678
RN1
33 x 4
1234
5678
RN4
33 x 4
1 TP22
TEST POINT
1234
5678
RN9 33 x 4
R30
4.7k
R202
4.7k
EMIF (External Memory Interface)
EA2
Y6EA3
V7EA4
W7EA5
V8EA6
W8EA7
Y8EA8
V9EA9
Y9EA10
V10EA11
W13EA12
V14EA13
W14EA14
Y14EA15
W15EA16
Y15EA17
V16EA18
Y16EA19
W17EA20
Y18EA21
U18BE0#
V20BE1#
U19BE2#
Y4BE3#
V5CE0#
V17CE1#
W18CE2#
W6CE3#
V6ECLKOUT
Y10ARE#/SDCAS#/SSADS#
V11AOE#/SDRAS#/SSOE#
W10AWE#/SDWE#/SSWE#
V12
ED0/GP1[0] K18ED1/GP1[1]K19ED2/GP1[2]L18ED3/GP1[3]
L19ED4/GP1[4]M19ED5/GP1[5]M20ED6/GP1[6]N18ED7/GP1[7]
N19ED8/GP1[8]N20ED9/GP1[9]P18ED10/GP1[10]
P20ED11/GP1[11]R19ED12/GP1[12]R20ED13/GP1[13]T18ED14/GP1[14]
T20ED15/GP1[15]T19
ED16V4ED17W4ED18
Y3ED19V2ED20V1ED21U2ED22
U1ED23U3ED24T1ED25
T2ED26R3ED27R2ED28P1ED29
P2ED30P3ED31N3ARDY
Y5HOLD# J17HOLDA# J18BUSREQ
J19
U21A
TMS320DA610B-GDP
1TP2 TEST POINT
1234
5678
RN7
33 x 4
R204
1k
R279 33
1TP21
TEST POINT
R230
10k
R277
4.7k
IO
DR0/AXR0[0]/AXR1[15]
J1DX0/AXR0[1]/AXR1[14]
H2TOUT0/AXR0[2]/AXR1[13]
G1TINP0/AXR0[3]/AXR1[12]
G2TOUT1/AXR0[4]/AXR1[11]
F1DX1/AXR0[5]/AXR1[10]
L2CLKR1/AXRO[6]/AXR1[9]
M1FSR1/AXR0[7]/AXR1[8]
M3HD1/AXR0[8]/AXR1[7]
D20HDS1#/AXR0[9]/AXR1[6]
E19HDS2#/AXR0[10]/AXR1[5]
F18HD0/AXR0[11]/AXR1[4]
E20HCNTL0/AXR0[12]/AXR1[3]
G18HCS#/AXR0[13]/AXR1[2]
F20HCNTL1/AXR0[14]/AXR1[1]
G19HR/W#/AXR0[15]/AXR1[0]
G20RESET#
A13ECLKIN
Y11CLKMODE0
C4CLKOUT3
D10CLKIN
A3TDI
A7TDO
A8TCK
A6TMS
B7TRST#
B6EMU0
D9EMU1
B9
HD4/GP0[0] C19HINT#/GP0[1] J20CLKOUT2/GP0[2] Y12
HD7/GP0[3]
A18
GP0[4](EXT_INT4)/AMUTEIN1 C2GP0[5](EXT_INT5)/AMUTEIN0C1
GP0[6](EXT_INT6)D2GP0[7](EXT_INT7)
E3
HD8/GP0[8]B17HD9/GP0[9]C16HD10/GP0[10]
B16HD11/GP0[11]A16HD12/GP0[12]C15HD13/GP0[13]A15HD14/GP0[14]
C14HD15/GP0[15]B14FSR0/AFSR0J3CLKR0/ACLKR0 H3CLKS0/AHCLKR0
K3TINP1/AHCLKX0F2CLKX0/ACLKX0G3FSX0/AFSX0
H1
NMIC13
HD3/AMUTE1 C20CLKS1/SCL1
E1DR1/SDA1M2
SCL0N1SDA0
N2
EMU2
D3EMU3
B10EMU4
C11EMU5
B12FSX1
L1OSCVDD
A12OSCVSS
B11OSCIN
D12OSCOUT
C12CLKX1/AMUTE0
L3HRDY#/ACLKR1
H19HAS#/ACLKX1
E18HD6/AHCLKR1
C17HD5/AHCLKX1
B18HD2/AFSX1
D18HHWIL/AFSR1
H20
U21B
TMS320DA610B-GDP
1234
5678
RN6
33 x 4
R2524.7k
1234
5678
RN2
33 x 4
3P3V
3P3V
3P3V
3P3V
DGND
DGND
DGND3P3V
I2S_IN[3:0]DSP_RXD
ED[31:0]EA[21:2]
I2C_SCL2I2C_SDA2
BE0#BE1#SDWE#SDRAS#SDCAS#CLK0
ARDY
DSPRESET#JTAG_TDIJTAG_TDOJTAG_TCKJTAG_TMSJTAG_TRSTJTAG_EMU0JTAG_EMU1
I2S_OUT[3:0]
SYSCLK
DSP_MCLKM_BCLKM_LRCLK
CE0#CE1#BE2#BE3#
DSP_TXD
DSP_GP1
  
NOTE: Pull-ups on GP0  andGP8  are  required  forbooting
  
Pl ac e  r e si st or n e t wor k  c lo se t o T M S32 0 DS PI2S Mapping
I2S_0 = CH4 & CH8
I2S_1 = CH3 & CH7
I2S_2 = CH2 & CH6
I2S_3 = CH1 & CH5
9
84
4
684
4
4
4
4
4
4
6
8
8,9
8,9 6,18
6,18
5
5
5
5
5
5
5
5
5
5
5
5
5
Place resistor
networks close to
 TMS320 DSP
DW GNO:
PART NO:
PART NAME:
PRODUCT MODE:
SCALE:       1:1
UNIT:          MM
SIZE:          
REV:          DRAWN BY: 
CHECKED BY:
APPROVED BY:
DATA:
DATA:
DATA:
DESCRIPTON DATA
APPROVED
DESCRIPTON
REV REV
Place
Place
DATA
EVR DSP&Memory
MS-8 MAIN AMP T4ChengHao 2009.09.08
Sheet 2 of 18
B
 
 MS-8                      
 
 
 
93  
						

							
ABC D
DCBA
C346
0.1uFC273
0.1uF
C216
0.1uFC351
0.1uF
C230
0.1uF
C189
0.1uF
C234
0.1uF
C215
0.1uF
C277
0.1uF
C342
0.1uFC253
0.1uF
C345
0.1uF
C193
0.1uFC350
0.1uF
C301
0.1uF
C365
0.1uF
C280
0.1uF
C347
0.1uF
C343
0.1uFC254
0.1uF
C238
0.1uFC355
0.1uF
C356
0.1uF
C320
0.1uF
C344
0.1uF
Power
PLLHV
C5DVDD
Y17DVDD
Y7DVDD
W12DVDD
W9DVDD
W3DVDD
V19DVDD
V15DVDD
V13DVDD
U16DVDD
U12DVDD
U7DVDD
U5DVDD
T3DVDD
R18DVDD
R1DVDD
M18DVDD
J2DVDD
H18DVDD
F3DVDD
D19DVDD
D16DVDD
D1DVDD
C10DVDD
B13DVDD
B8DVDD
B3DVDD
A17CVDD
W19CVDD
W2CVDD
V18CVDD
V3CVDD
U15CVDD
U14CVDD
L20CVDD
U11CVDD
U10CVDD
U6CVDD
R17CVDD
R4CVDD
L17CVDD
L4CVDD
K17CVDD
K4CVDD
K1CVDD
F17CVDD
F4CVDD
D15CVDD
D14CVDD
D11CVDD
D6CVDD
D5CVDD
C18CVDD
C7CVDD
C3CVDD
B19CVDD
B2CVDD
A10CVDD
A9CVDD
A4RSV
D7RSV
B5RSV
B4RSV
A5
GND A1GNDA2GNDA11GND
A14GNDA19GNDA20GNDB1GND
B15GNDB20GNDC6GND
C8GNDC9GNDD4GNDD8GND
D13GNDD17GNDE2GNDE4GND
E17GNDF19GNDG4GND
G17GNDH4GNDH17GNDJ4GND
J9GNDJ10GNDJ11GNDJ12GND
K2GNDK9GNDK10GNDK11GND
K12GNDK20GNDL9GND
L10GNDL11GNDL12GNDM4GND
M9GNDM10GNDM11GNDM12GND
M17GNDN4GNDN17GNDP4GND
P17GNDP19GNDT4GND
T17GNDU4GNDU8GNDU9GND
U13GNDU17GNDU20GNDW1GND
W5GNDW11GNDW16GND
W20GNDY1GNDY2GNDY13GND
Y19GNDY20
U21C
TMS320DA610B-GDP
C255
0.1uF
C353
0.1uF
C303
0.1uF
C352
0.1uF
C276
0.1uF
C341
0.1uFC252
0.1uF
C340
0.1uF
C339
0.1uF
C354
0.1uF
C218
0.1uF
C318
0.1uF
C348
0.1uF
C217
0.1uF
C127
0.1uF
C274
0.1uF
C236
0.1uF
C314
0.1uFC249
0.1uF
C219
0.1uF
C349
0.1uF
C188
0.1uFC275
0.1uF
C239
0.1uF
C338
0.1uF
C126
0.1uF
3P3V
1P2V
3P3V
DGND
1P2V
DGNDDGND
3P3V
1P2V
3P3V
Bypass Caps: Place close to U21
 
These capacitors  should be placed acrossthe plane split between 1P2V and 3P3V.
DW GNO:
PART NO:
PART NAME:
PRODUCT MODE:
SCALE:       1:1
UNIT:          MM
SIZE:          
REV:           DRAWN BY: 
CHECKED BY:
APPROVED BY:
DATA:
DATA:
DATA:
DESCRIPTON DATA
APPROVED
DESCRIPTON
REV REV
Place
Place
DATA
EVR DSP Power
MS-8 MAIN AMP T4ChengHao 2009.09.08
Sheet 3 of 18
B
C256
4.7UFC324
4.7UFC322
4.7UFC235
4.7UFC211
4.7UF
C200
0.1uF
 
 MS-8                      
 
 
 
94  
						

							
1
2
3
4
56
ABC D
6
5
4
3
2
1
D
CBA
TDO_BUFFTCK_RET
JTAG_TRSTJTAG_TMSTDO_BUFFTCK_RETJTAG_TCKJTAG_TDIJTAG_EMU0JTAG_EMU1JTAG_TDOC328
0.1uF (DNP)
C199
0.1uF
C330
0.1uF (DNP)
C327
0.1uF (DNP)
C329
0.1uF (DNP)
OE1
11A4
81A1
21A3
62A3
152A1
112A4
172A2
131A2
4
OE2 191Y4121Y1181Y3
142Y352Y192Y432Y2
71Y216
VCC 20GND
10
U22
74LVC2244A
123 J10
B3P-BC-2 (DNP)
EN
1C1+
2V+
3C1-
4
C2+ 5C2-6
V-
7
Rin 8
Rout
9
INVALID 10
Din
11ForceOn
12
Dout 13
Gnd
14VCC 15
ForceOff
16 U27
MAX3221 (DNP)
VCC
5GND
4GND
8KEY
6GND
10GND
12
#TRST 2TMS
1
TCK_RET 9
TCK11TDI3TDO
7EMU0 13EMU114
J9
TSW-107-07-L-D-006 (DNP)
3P3VDGND
DGND3P3V
DGND
3P3V
3P3VDGND
DGND
AGND3P3V
JTAG_TRST
DSP_TXDDSP_RXD
JTAG_TMSJTAG_TCKJTAG_TDIJTAG_EMU0JTAG_EMU1JTAG_TDO
JTAG Debug/Programming Circuit for DA610
3-Pin header for RS232 Comm (DNP for Production)
R274
4.7K
R273
4.7K
R290
4.7K
R280
4.7K
R287
4.7K
R291
4.7K
R285
100(DNP)R286
100(DNP)
2
2
2
2
2
2
2
2
2
DW GNO:
PART NO:
PART NAME:
PRODUCT MODE:
SCALE:       1:1
UNIT:          MM
SIZE:          
REV:           DRAWN BY: 
CHECKED BY:
APPROVED BY:
DATA:
DATA:
DATA:
DESCRIPTON DATA
APPROVED
DESCRIPTON
REV REV
Place
Place
DATA
EVR
Debug Connectors
MS-8 MAIN AMP
T4 ChengHao
2009.09.08
Sheet 4 of 18
B
 
 MS-8                      
 
 
 
95  
						

							
1
2
3
4
56
ABC D
6
5
4
3
2
1
D
CBA
ED0ED1ED2ED3ED4ED5ED6ED7ED8ED9ED10ED11ED12ED13ED14ED15
ED0ED1ED2ED3ED4ED5ED6ED7ED8ED9ED10ED11ED12ED13ED14ED15
EA2EA3EA4EA5EA6EA7EA8EA9EA10EA11EA12EA13EA14BE0#BE1#SDWE#SDCAS#SDRAS#CE0#CLKO
EA2EA3EA4EA5EA6EA7EA8EA9EA10EA11EA12EA13EA14EA15EA16EA17EA18EA19EA20EA21CE1#SDRAS#SDWE#
ED16ED17ED18ED19ED20ED21ED22ED23ED24ED25ED26ED27ED28ED29ED30ED31
BE2#BE3#
C315
0.1uF
C149
0.1uF
C316
0.1uF
C317
0.1uF
C321
0.1uF
C319
0.1uF
DQ0
29DQ1
31DQ2
33DQ3
35DQ4
38DQ5
40DQ6
42DQ7
44DQ8
30DQ9
32DQ10
34DQ11
36DQ12
39DQ13
41DQ14
43DQ15/A-1
45
CE 26OE 28WE 11RY/BY
15A025A124A2
23A322A421A520A6
19A718A88A97A10
6A115A124A133A14
2A151A1648A17
17A1816A199
NC1
10VCCW
13WP
14GND
27GND
46VCC
37
RP 12BYTE 47
U8
S29AL016M
DQ0
2DQ1
4DQ2
5DQ3
7DQ4
8DQ5
10DQ6
11DQ7
13
BA0 22BA123A1024A0
25A126A227
DQ24
45DQ25
47DQ26
48DQ27
50DQ28
51DQ29
53DQ30
54DQ31
56
CLK 68
DQ10
77
A3
60A461A562A663A7
64A865A966
DQ8
74DQ9
76DQ11
79DQ12
80DQ13
82DQ14
83DQ15
85DQ16
31DQ17
33DQ18
34DQ19
36DQ20
37DQ21
39DQ22
40DQ23
42
GND
44GND
58GND
72GND
86
VSSQ 12VSSQ6VSSQ32VSSQ
38VSSQ46VSSQ52VSSQ78VSSQ
84VDD1VDD
15VDD29VDD43VDDQ 3VDDQ
9VDDQ35VDDQ41VDDQ49VDDQ
55VDDQ75VDDQ81CAS
18CKE 67RAS19WE
17CS20DQM0 16DQM1
71DQM228DQM359
NC
30NC
57NC
21NC
14NC
69NC
73NC
70 U7
MT48LC2M32B2/TSOP
C150
0.1uF
3P3V
3P3V
3P3V
DGND
DGND
3P3V
DGND3P3V
ED[31:0]EA[21:2]
BE0#BE1#SDWE#SDCAS#SDRAS#CLK0CE0#
CE1#RESET#ARDY
BE2#BE3#
8 Mbyte SDRAM in 256 Mbyte address space 
(8000 0000 - 8FFF FFFF) 2 Mbyte Flash in 256 Mbyte address space 
(9000 0000 - 9FFF FFFF)
Upon the release of internal reset, the 1K-Byte
ROM code located in the beginning of CE1 Flash
is copied to address 0 by the EDMA using the
default ROM timings, while the CPU is internally
stalled.
2
2
2
2
2
2
2
2
2
2
2
2
2
6,7
R158
10K
R170 1K
DW GNO:
PART NO:
PART NAME:
PRODUCT MODE:
SCALE:       1:1
UNIT:          MM
SIZE:          
REV:           DRAWN BY: 
CHECKED BY:
APPROVED BY:
DATA:
DATA:
DATA:
DESCRIPTON DATA
APPROVED
DESCRIPTON
REV REV
Place
Place
DATA
EVR SDRAM,Flash
MS-8 MAIN AMP T4ChengHao 2009.09.08
Sheet 5 of 18
B
 
 MS-8                      
 
 
 
96  
						

							
1
2
3
4
56
ABC D
6
5
4
3
2
1
D
CBA
POW_EN#DSPRESET
DSPLY_PWR_EN#PWRAMPMUTE
LED_EN
LED_EN
5V_IPOD_EN#
DSPLY_PWR_EN#
DSPRESET
POW_EN#
PWRAMPMUTE
5V_IPOD_EN#
VTEMP
VTEMP
R232 680
3
4
U10B
74HCU04
32
1
Q3
MUN5214T1
P0.1
1P0.0
2GND
3D+
4D-
5VDD
6REGIN
7VBUS
8/RST/C2CK
9P3.0/C2D
10P2.7
11P2.6
12P2.5
13P2.4
14P2.3
15P2.2
16
P2.1 17P2.018P1.719P1.6
20P1.521P1.422P1.323P1.2
24P1.125P1.026P0.727P0.6
28P0.529P0.430P0.3
31P0.232
U23
C8051F347
5
6
U10C
74HCU04
1
TP11 TEST POINT
C391
0.1uF
C304
0.1uF
t
RT11
NCP18XH103J03RB
10
11 U10E
74HCU04
8
9
U10D
74HCU04
123
J4
1
2
147U10A
74HCU04
12
13
U10F
74HCU04
C382
0.1uF
R81
7.68k 1%
C323
0.1uF
123 J12
R80
2.32k 1%
12LED1
BLUE LED
DGND
DGND
DGND
5V_ONDGND3P3V_ON
5V_ONDGND
3P3V_ONDGND
DGND
DGND
DGND
3P3V_ONDGND
DGND
USB_D-USB_D+VBUSI2C_SDAI2C_SCL
DAC_MUTEMUX0DAC_RESET#ADC_PDN#MUX1
RESET#
REM_IN_TTL
LOWVOLT#
AUD_SENSEI2C_SCL2I2C_SDA2
MICDETECT#
DSP_GP1
DSPLY_PWR_ENDSPRESET#
POW_EN
MUTE#
    
C2 I nter face  fo rDe bug  andPr ogra mmin g o fMi croc ontr oll er
    
VT EM P c an be  a ma xi mum  o f2. 4V
The microcontroller internally regulates
the 5V supply down to 3.3V.  The 3.3V
output is available as a supply for
other devices.
DW GNO:
PART NO:
PART NAME:
PRODUCT MODE:
SCALE:       1:1
UNIT:          MM
SIZE:          
REV:           DRAWN BY: 
CHECKED BY:
APPROVED BY:
DATA:
DATA:
DATA:
DESCRIPTON DATA
APPROVED
DESCRIPTON
REV REV
Place
Place
DATA
EVR
Microcontroller
MS-8 MAIN AMP T4ChengHao 2009.09.08
Sheet 6 of 18
B
5,7 17,18
17,18
17
17
17
10
7 2 14
2,18
7
2,18
8
8
8
9
9
7
18
2
7,18 The UART TXD and RXD
are fixed as P0.4 and
P0.5  respectively.
R282 63.4KR297
10K
C401
0.1uFDGND
DGND
VCAR
 
 MS-8                      
 
 
 
97  
						

							
ABC D
DCBA
REM_IN_ACT
TERMGNDREM_INBATT
REM_IN_ACT5V_ON
REM_OUT
MR#
REM_OUT
REM_IN_TTL
RESET#
R203
4.99k 1%
R322
1k
R292
100k
REG1(V8P5/600mA)
1REG3(V5/1400mA)
2VP2
3REG4(V3P3/1A)
4IGNIN
5IGNOUT
6RES
7CRES
8EN4
9EN1/3
10ENSW
11HOLD
12GND
13BU(14V/100mA)
14REG2(5V/300mA)
15SW(14V/3A)
16VP1(14.4V)
17 U4
TDA3681J
R7
4.7k
C35
47uF/6.3V
1
2
L17
1nH
C109
0.22uF Y5V
-20%+80%
R284
10k
C5
1nF
Boost 1
VIN
5EN
4
GND
2FB3SW 6
U24
LM2734Y
R324
3.3k
C6
1nF
R43 10k
C66
0.22uF
C1
0.1uF/100V
C47
0.22uF
Q8
MMBT3906
C378
10uF/35V
12D23 1N4148W
C48
0.22uF
C51
47uF/6.3V
R288
2.00k 1%
Q9
MMBT3904
1
2
L18
1nH
C326
0.1uF
C34
47uF/10V
12
34
SW1
TL1105WF160Q
C298
0.22uF Y5V
-20%+80%
C4
1nF
C375
10uF/35V
C64
0.22uF
R255
100k
C278
47uF/6.3V/1206 20%
X5R
Q10
MMBT3904
R323
1k
12
3SG1
STARGND3
C297
10uF/16V/1206 20%
X5R
12F1
FUSE SKT
R289
27.4k 1%
L20 65uH
C50
0.22uF
C67
0.22uF
C305
0.01uF
C376
10uF/35V
RSTVDD 1
GND
2
MR
3SENSE
4
RSTSENSE 5VDD6
U26
TPS3106K33
R283
10k
12
D22
CRS06
R26
4.7k
R298
10k
C36 47uF/6.3V
R8
4.7k
C374
10uF/35V
1234
TB1
4-Position Terminal Block
1
2
L22
15uH
C107
47uF/6.3V
1MH2
MTG HOLE
C38
4700uF/35V
R205
10.0k 1%
3P3V8P5V
5V_ON
+5VA
VCAR
VCAR
VCAR
3P3V_ON
1P2V
5V_DISP
5V_ONAGND
8P5V
5V
VCAR
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
PGND
DGND
PGND
PGND
DGND
PGND
5V
VCAR
AGND
12V
DGND
AGND
DGND
POW_EN
RESET#
DSPLY_PWR_EN
REM_IN_TTL
LOWVOLT#
POW_EN
F1 plugs into socket
  
S EN SE  ha s 0. 551 Vth r e sh old
Coilcraft
MSS7341-153MLB
TDK
C3216X5R1C106M
Place Feedback line away from inductor
preferably on other side of the board
  
P la c e L22 /D22 /C 27 8c lo se  t oge t he r
Place C144/C428
close to VIN pin
Make VIN/SW and GND 
lines as thick and as short
as possible
 
T he  1P 2V  sup pl y m a y ha v e  to so ur c e  a s  m uc h a s  1A.
The only traces that may cross from the
DGND region to the AGND region are: IAUDR,
IAUDL, IAGND, DAC_RESET, AUD_SENSE,ADC_PDN#, MUX0, MUX1, DAC_MUTE, I2S_OUT0,
I2S_OUT1, I2S_OUT2, I2S_OUT3, I2S_IN0,
I2S_IN1, I2S_IN2, I2S_IN3, DAC_MCLK,M_LRCLK, ADC_MCLK, M_BCLK, I2C_SCL,
I2C_SDA, I2C_SCL2, I2C_SDA2, AMP_ON.
5V regulator output for
the main MCU, auto-sense
circuit, display MCU, and
RF transceiver.  This is
always on.  The current
consumption is less than
10mA in standby mode.
LOWVOLT#
 is
active when
 the
input voltage
drops below a
il l
Place capacitor as
close as possible to
the terminal strip
12D34
6A10
Connect TERMGND, PGND,
and AGND/DGND/GND2 near
the terminal block in a
star configuration
Locate these two
resistors close to the
LM2734Y part
DW GNO:
PART NO:
PART NAME:
PRODUCT MODE:
SCALE:       1:1
UNIT:          MM
SIZE:          
REV:          DRAWN BY: 
CHECKED BY:
APPROVED BY:
DATA:
DATA:
DATA:
DESCRIPTON DATA
APPROVED
DESCRIPTON
REV REV
Place
Place
DATA
EVR Regulators
MS-8 MAIN AMP T4ChengHao 2009.09.08
Sheet 7 of 18
B
5,6
6
6
6,18
6
6,18
C95
4700UF/35V
25A
Q4
FDN358P
D2
SMLJ22A-T
D33
MM3Z15VT1G
D24
BZX84C3V9
Q5
FDV301N
1
2
L23
1nH
1
2
L24
1nH
C99
0.22uF
C100
0.22uF
PGND
PGND
8P5VA
C379
0.1uF
R34
10k
1MH1
MTG HOLECGND
 
 MS-8                      
 
 
 
98  
						

							
ABC D
DCBA
M_LRCLK
M_LRCLK
I2S_IN1
ADC_MCLKADC_MCLK
ADC_MCLK
M_BCLK
M_BCLK
ADC_MCLK
SYSCLKDSP_MCLKADC_MCLKDAC_MCLK
ADC_PDN#
ADC_PDN#
ADC_PDN#
ADC_PDN#
I2S_IN2
I2S_IN3
I2S_IN0
M_BCLK
M_BCLKM_LRCLK
M_LRCLK
C182
10uF
C196 10uF
C195
10uFC147 2.2uF
C299
0.1uF
8
9 U16D
74HCU04
C187 10uF
C336
0.1uF
1
2
147U16A
74HCU04
R299
33
C228 10uF
C114
10uF
C167 10uF
C172
2.2uF
C192
10uF
C112 2.2uF
5x5.7XCOINH
1GND
2
Output 3VCC4
Y1
ASSVP-24.576MHZ-C04-T
5
6
U16C
74HCU04
C333
0.1uF
X0
12X1
14X2
15X3
11Y0
1Y1
5Y2
2Y3
4EN
6A
10B
9
X 13Y3
VDD
16
GND
8
VEE
7 U15 74HC4052
C335
0.1uF
12
13
U16F
74HCU04
TSSOP16AINR
1AINL
2CKS1
3VCOM
4AGND
5VA
6VD
7DGND
8
SDTO 9LRCK10MCLK
11SCLK12PDN13DIF14CKS2 15CKS016
U14
AK5358ET
C334
0.1uF
C111 10uF
C206 2.2uF
R294 33
C197 10uF
C203
0.1uF
C169
10uF
C337
0.1uF
C12510uF
R296 33
C116 10uF
C207
0.1uF
C148
10uF
C171 10uF
C229 10uF
TSSOP16AINR
1AINL
2CKS1
3VCOM
4AGND
5VA
6VD
7DGND
8
SDTO 9LRCK
10MCLK 11SCLK
12PDN13DIF
14CKS2 15CKS0
16
U13
AK5358ET
R174
10k
C332
0.1uF
3
4
U16B
74HCU04
C198
10uF
R295 33
TSSOP16AINR
1AINL
2CKS1
3VCOM
4AGND
5VA
6VD
7DGND
8
SDTO 9LRCK10MCLK
11SCLK12PDN13DIF14CKS2 15CKS0
16
U5
AK5358ET
C146 10uF
10
11 U16E
74HCU04
C300
0.1uF
C210
0.1uF
R320 33R321 33
C227
10uF
C222
10uF
TSSOP16AINR
1AINL
2CKS1
3VCOM
4AGND
5VA
6VD
7DGND
8
SDTO 9LRCK
10MCLK 11SCLK
12PDN13DIF
14CKS2 15CKS0
16
U6
AK5358ET
AGND
AGNDAGND
AGNDAGND
AGND
3P3V3P3V
3P3V
3P3V
3P3V
AGND
AGND
AGND
AGND
AGND3P3V
3P3V
AGND
AGND
DGND
3P3V
DGND
5V
AGND
+5VA+5VA
+5VA
+5VA
3P3V
DGND
3P3V
DGND
DGND
3P3V
I2S_IN[3:0]
LIN2RIN2LIN3RIN3
RIN4LIN4
MUX0
DAC_MCLKSYSCLKDSP_MCLK
ADC_PDN#
MicL_analogMicR_analog
LIN1RIN1
MUX1
AUX_RAUX_L
M_BCLKM_LRCLK
 
Ke ep  PD N  low  u nti l  pow eran d  clo ck s h av e s ta bil ize d
 
Th is  re si sto r  is  lo cat edcl os e t o  the  A K53 58
 
Th is  re si sto r  is  lo cat edcl os e t o  the  A K53 58
 
Th is  re si sto r  is  lo cat edcl os e t o  the  A K53 58
MCLK = 24.576 MHz
BCLK = 3.072 MHz
LRCLK = 48 kHz
CH1
CH5
CH2
CH6 CH3
CH7
CH4
CH8
 
Th e  res is tor  n etw or k s hou ld  be cl os e t o  the  74 HC U04  c hi p
 
These resistors are locatedclose to  the AK5358
Use daisy-chain routing
(not tree routing) for
the M_BCLK and M_LRCLK
signals.  The
termination resistors
should be at one end of
the chain.
DW GNO:
PART NO:
PART NAME:
PRODUCT MODE:
SCALE:       1:1
UNIT:          MM
SIZE:          
REV:          
DRAWN BY: 
CHECKED BY:
APPROVED BY:
DATA:
DATA:
DATA:
DESCRIPTON DATA
APPROVED
DESCRIPTON
REV REV
Place
Place
DATA
EVR ADC
MS-8 MAIN AMP T4ChengHao 2009.09.08
Sheet 8 of 18
B
13
10
11
13
10
11
13
13
12
12 6
6
2,9
2,912
12 6
2
2
9
2
1234
5678
RN10
33X4
I2S_IN0I2S_IN1
I2S_IN2
I2S_IN3
3P3V
M_AIN_R
M_AIN_L
3P3V
 
 MS-8                      
 
 
 
99