JBL Ms 8 Service Manual

							
Rev. 1.321
C8051F340/1/2/3/4/5/6/7/8/9/A/B
Figure 1.2. C8051F342/3/6/7 Block Diagram
Analog Peripherals
10-bit
 200 ksps 
ADCA
M UX
Temp 
Sensor
2 Comparators
+
-
VREFVDD
CP0
VDD
+-CP1VREF
Debug / Programming  Hardware
Port 0
Drivers
P0.0
AIN0 - AIN20
Port I/O Configuration
Digital Peripherals
Priority 
Crossbar 
Decoder
Crossbar Control
Power-On  Reset
Power Net
UART0
Timers 0, 1,  2, 3
PCA/WDT
SMBus
SPI
P0.1P0.2/XTAL1P0.3/XTAL2P0.4P0.5P0.6/CNVSTRP0.7/VREF
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
Supply 
Monitor
System Clock Setup
External 
Oscillator
Internal 
Oscillator
XTAL1XTAL2
Low Freq. 
Oscillator*
Clock 
Multiplier
Clock 
Recovery
USB Peripheral
Controller
1 kB RAM
Full / Low  Speed 
Transceiver
SFR 
Bus
Voltage 
Regulator
D+
D-
VBUS VDD
VREG GND
C2CK/RST
Reset
CIP-51 8051 
Controller Core
64/32 kB ISP FLASH  Program Memory
256 Byte RAM
4/2 kB XRAM
C2D
*Low Frequency Oscillator option not available on C8051F346/7
 
 MS-8                      
 
 
 
50  
						

							
Rev. 1.329
C8051F340/1/2/3/4/5/6/7/8/9/A/B
4. Pinout and Package Definitions
Ta b l e 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B  
NamePin NumbersTy p eDescription48-pin32-pin
VDD106Power In
Power 
Out
2.7–3.6 V Power Supply Voltage Input.
3.3 V Voltage Regulator Output. See Section 8.
GND73Ground.
RST/
C2CK
139D I/O
D I/O
Device Reset. Open-drain output of internal POR or VDD 
monitor. An external source  can initiate a system reset by 
driving this pin low for at least 15
 µs. See Section 11.
Clock signal for the C2 Debug Interface.
C2D14—D I/OBi-directional data signal for the C2 Debug Interface.
P3.0 / 
C2D
—10D I/O
D I/O
Port 3.0. See Section 15 for a complete description of Port 
3.
Bi-directional data signal for the C2 Debug Interface.
REGIN117Power In5 V Regulator Input. This pin is the input to the on-chip volt-
age regulator. 
VBUS128D InVBUS Sense Input. This pin should be connected to the 
VBUS signal  of a USB network. A 5
 V signal on this pin indi-
cates a USB network connection.
D+84D I/OUSB D+.
D-95D I/OUSB D–.
P0.062D I/O or
A In
Port 0.0. See Section 15 for a complete description of Port 
0.
P0.151D I/O or
A In
Port 0.1.
P0.2432D I/O or
A In
Port 0.2.
P0.3331D I/O or
A In
Port 0.3.
P0.4230D I/O or
A In
Port 0.4.
P0.5129D I/O or
A In
Port 0.5.
P0.64828D I/O or
A In
Port 0.6.
P0.74727D I/O or
A In
Port 0.7.
 
 MS-8                      
 
 
 
51  
						

							
C8051F340/1/2/3/4/5/6/7/8/9/A/B
P1.04626D I/O or
A In
Port 1.0. See Section 15 for a complete description of Port 
1.
P1.14525D I/O or
A In
Port 1.1.
P1.24424D I/O or
A In
Port 1.2.
P1.34323D I/O or
A In
Port 1.3.
P1.44222D I/O or
A In
Port 1.4.
P1.54121D I/O or
A In
Port 1.5.
P1.64020D I/O or
A In
Port 1.6.
P1.73919D I/O or
A In
Port 1.7.
P2.03818D I/O or
A In
Port 2.0. See Section 15 for a complete description of Port 
2.
P2.13717D I/O or
A In
Port 2.1.
P2.23616D I/O or
A In
Port 2.2.
P2.33515D I/O or
A In
Port 2.3.
P2.43414D I/O or
A In
Port 2.4.
P2.53313D I/O or
A In
Port 2.5.
P2.63212D I/O or
A In
Port 2.6.
P2.73111D I/O or
A In
Port 2.7.
P3.030—D I/O or
A In
Port 3.0. See Section 15 for a complete description of Port 
3.
P3.129—D I/O or
A In
Port 3.1.
P3.228—D I/O or
A In
Port 3.2.
Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B  (Continued)
NamePin NumbersTy p eDescription48-pin32-pin
 
 MS-8                      
 
 
 
52  
						

							
Rev. 1.331
C8051F340/1/2/3/4/5/6/7/8/9/A/B
P3.327—D I/O or
A In
Port 3.3.
P3.426—D I/O or
A In
Port 3.4.
P3.525—D I/O or
A In
Port 3.5.
P3.624—D I/O or
A In
Port 3.6.
P3.723—D I/O or
A In
Port 3.7.
P4.022—D I/O or
A In
Port 4.0. See Section 15 for a complete description of Port 
4.
P4.121—D I/O or
A In
Port 4.1.
P4.220—D I/O or
A In
Port 4.2.
P4.319—D I/O or
A In
Port 4.3.
P4.418—D I/O or
A In
Port 4.4.
P4.517—D I/O or
A In
Port 4.5.
P4.616—D I/O or
A In
Port 4.6.
P4.715—D I/O or
A In
Port 4.7.
Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B  (Continued)
NamePin NumbersTy p eDescription48-pin32-pin
 
 MS-8                      
 
 
 
53  
						

							
C8051F340/1/2/3/4/5/6/7/8/9/A/B
Figure 4.1. TQFP-48 Pinout Diagram (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
484746454443424140393837
VBUS P2.2
P2.0 P1.7 P1.6 P1.2
P2.4 P2.3
P3.5 P3.4 P3.2 P3.1
P2.1 P0.6
P3.3
P0.7
P0.2
D-
REGIN P0.3
P3.0
P1.4
P1.5
P0.5
P1.1 P1.0
P0.4
P1.3
131415161718192021222324
P2.6 P2.5
C8051F340/1/4/5/8-GQTop View
GND
D+
P0.1
P0.0
VDD P2.7
P3.6 P4.1
P4.0
P3.7 P4.2 P4.5
P4.4
P4.3 P4.6
RST / C2CK
C2D
P4.7
 
 MS-8                      
 
 
 
54  
						

							
DATASHEET
S29AL016M
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)  
3.0 Volt-only Boot Sector Flash Memory  
featuring MirrorBitTM technology
Data Sheet
Distinctive Characteristics
Architectural Advantages
„Single power supply operation
— 3 V for read, erase, and program operations
„Manufactured on 0.23 µm MirrorBitTM process 
technology
„ SecSiTM (Secured Silicon) Sector region
— 128-word/256-byte sector for permanent, secure 
identification through an 8-word/16-byte random 
Electronic Serial Number, accessible through a 
command sequence
— May be programmed and locked at the factory or by the customer
„Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-
one 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and thirty-
one 32 Kword sectors (word mode)
„Compatibility with JEDEC standards
— Provides pinout and software compatibility for single-
power supply flash, and superior inadvertent write 
protection
„Top or bottom boot block configurations available
„100,000 erase cycle typical per sector
„20-year typical data retention 
Performance Characteristics
„High performance
— 90 ns access time
— 0.7 s typical sector erase time
„Low power consumption (typical values at 5 MHz)
— 400 nA standby mode current
— 15 mA read current
— 40 mA program/erase current
— 400 nA Automatic Sleep mode current
„Package options
— 48-ball Fine-pitch BGA
— 64-ball Fortified BGA
— 48-pin TSOP
Software Features
— Program Suspend & Resume: read other sectors 
before programming operation is completed
— Erase Suspend & Resume: read/program other sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall multiple-word programming time 
— CFI (Common Flash Interfac e) compliant: allows host 
system to identify and accommodate multiple flash 
devices
Hardware Features
— Sector Protection: hardware-level method of  preventing write operations within a sector 
— Temporary Sector Unprotect: VID-level method of 
changing code in locked sectors
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) indicates program or  erase cycle completion
 
 MS-8                      
 
 
 
55  
						

							
Product Selector Guide
Notes:
1. See “AC Characteristics”  for full specifications.
2. Contact sales office or representative for availability and ordering information.
Block Diagram
Family Part NumberS29AL016M
Speed OptionFull Voltage Range: VCC = 2.7–3.6 V90100
Max access time (ns)90100
Max CE# access time (ns)90100
Max OE# access time (ns)2525
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM VoltageGenerator
TimerVCC Detector
State
Control
Command Register
VCC
VSS
WE#
BYTE#
CE#
OE#
STB STBDQ15–DQ0 (A-1)
Sector Switches
RY/BY#
RESET#
Data
Latch
Y-Gating
Cell Matrix
Address LatchA19–A0
 
 MS-8                      
 
 
 
56  
						

							
Connection Diagrams
A1
A15
A18
A14
A13
A12
A11
A10
A9
A8
A19 NC
WE#
RESET# NC
NC
RY/BY#
A17A7
A6
A5
A4
A3
A2
1
16
2
3
4
5
6
7
8
17
18 19
20
21
22
23
24 9
10
11
12
13
14
15 A16
DQ2 BYTE#
V
SSDQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9 DQ1
DQ8
DQ0
OE#
V
SSCE#A0
DQ5
DQ12
DQ4
V
CCDQ11
DQ3
DQ10
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25 32
31
30
29
28
27
26Standard TSOP
Pin Configuration
A19–A0 = 20 addresses
DQ14–DQ0 = 15 data inputs/outputs
DQ15/A-1 = DQ15 (data input/output, word mode),   
A-1 (LSB address input, byte mode)
BYTE# = Selects 8-bit or 16-bit mode
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin
RY/BY# = Ready/Busy output 
V
CC  = 3.0 volt-only single power supply  
(see Product Selector Guide for speed  
options and voltage supply tolerances)
V
SS= Device ground
NC = Pin not connected internally
Logic Symbol 
20
16 or 8
DQ15–DQ0 (A-1)
A19–A0
CE#
OE# WE#
RESET#
BYTE# RY/BY#
 
 MS-8                      
 
 
 
57  
						

							

  
  
\b  
	

	  
	\b  

  

  

\b
\f
  


  
  
SLOS080J   SEPTEMBER 1978  REVISED MARCH 2005
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NC
2OUT
NC
2IN
NC 1IN+
NC
V
CC+
NC
2IN+
NC
VCC+
NC
OUT
NC
3212019
910111213
4
5
6
7
8
18
17
16
15
14NC
1IN NC
1IN+
NC
(TOP VIEW)
NC
1OUT
NC
NC NC
NC
NC
2IN+ CC
V
CC+
V
1
2
3
4 
5
6
7 14
13
12
11
10 9
81OUT 1IN
1IN+
V
CC+
2IN+ 2IN
2OUT 4OUT
4IN
4IN+
V
CC
3IN+
3IN
3OUT
TL074A, TL074BD, J, N, NS, OR PW PACKAGE
TL074 . . . D, J, N, NS, PW, 
OR W PACKAGE (TOP VIEW)
NC  No internal connection
3212019
910111213
4
5
6
7
8
18
17
16
15
14NC
IN NC
IN+
NC
TL071
FK PACKAGE (TOP VIEW)
NC
OFFSET N1
NC
NC NC
NC
NC
OFFSET N2 NC
CC
V
TL072
FK PACKAGE
3212019
910111213
4
5
6
7
8
18
17
16
15
144IN+
NC
V
CC
NC
3IN+
TL074
FK PACKAGE (TOP VIEW)
1IN
1OUT
NC
3IN 4IN
2IN
NC
3OUT 4OUT
2OUT
1
2
3
4 8
7
6
5OFFSET N1
IN
IN+
V
CC
NC
V
CC+OUT
OFFSET N2
TL071, TL071A, TL071BD, P, OR PS PACKAGE (TOP VIEW)
1
2
3
4 8
7
6
51OUT
1IN
1IN+
V
CC
VCC+2OUT
2IN
2IN+
TL072, TL072A, TL072BD, JG, P, PS, OR PW PACKAGE (TOP VIEW)
TL072
U PACKAGE (TOP VIEW)
1
2
3
4 
5 10
9
8
7
6NC
1OUT 1IN
1IN+
V
CC
NC
V
CC+
2OUT
2IN
2IN+
symbols
+
+
IN+
IN OUTIN+
IN OUT
TL072 (each amplifier)
TL074 (each amplifier)
TL071
OFFSET N1
OFFSET N2
 
 MS-8                       
 
 
58  
						

							
1FEATURES DESCRIPTION
APPLICATIONS

TPS3103xxx TPS3106xxx
TPS3110xxx

SLVS363E – AUGUST 2001 – REVISED SEPTEMBER 2007
www.ti.com
 UltraLow Supply-Current/Supply-Voltage Supervisory Circuits

2
·
Precision Supply Voltage Supervision Range:0.9 V, 1.2 V, 1.5 V, 1.6 V, 2 V, and 3.3 V
The TPS310x and TPS311x families of supervisory circuits provide circuit initialization and timing
·
High Trip-Point Accuracy: 0.75% supervision, primarily for DSP and processor-based
·
Supply Current of 1.2 A (typical) systems.
·
RESET Defined With Input Voltages as Low as
During power-on, RESET is asserted when the0.4 V supply voltage (V
DD
) becomes higher than 0.4 V.
·
Power-On Reset Generator With a Delay Time Thereafter, the supervisory circuit monitors V
DD
and
of 130 ms
keeps the RESET output active as long as V
DD
·
Push/Pull or Open-Drain RESET Outputsremains below the threshold voltage (V IT
). An internal
timer delays the return of the output to the inactive
·
SOT23-6 Package state to ensure proper system reset. The delay time
·
Package Temperature Range: –40 °C to +85°C starts after V
DD
has risen above V IT
. When V DD
drops
below V
IT
, the output becomes active again.
All the devices of this family have a fixed-sense
·
Applications Using Low-Power DSPs, threshold voltage (V
IT
) set by an internal voltage
Microcontrollers, or Microprocessors divider.
·
Portable- and Battery-Powered Equipment The TPS3103 and TPS3106 have an active-low,
·
Intelligent Instruments open-drain RESET output. The TPS3110 has an
·
Wireless Communication Systems active-low push/pull RESET.
·
Industrial Equipment The product spectrum is designed for supply voltages
·
Notebook/Desktop Computers of 0.9 V up to 3.3 V. The circuits are available in
SOT23-6 packages. The TPS31xx family is characterized for operation over a temperature range of –40
°C to +85 °C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2001–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

 
 MS-8                      
 
 
  
(TOPVIEW)
RESET GND
MR V
DD
PFI
TPS3103
DBVPACKAGE
PFO32
46
1
5 (TOPVIEW)
RSTVDD GND
MR V
DD
SENSE
TPS3106
DBVPACKAGE
RSTSENSE 32
46
1
5
(TOPVIEW)
RESET
GNDMR
VDD
SENSE
TPS3110
DBVPACKAGE
WDI
32
46
1
5 TypicalApplicationCircuit TPS3106K33DBV
V
DD
RSTVDD RSTSENSE
GND
SENSE
R1
R2
GNDV
CORE V
IO RESETR3
DSP
3.3V
1.6V
GND MR  
59