GTE Omni Si Database Technical Practices Manual
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Page 791
TL-130200-1001 At the same time, the system assigns channel 18 in control memory A. channel memory and control memory A are connected by channel 18. 4. By looking at the Control Memory address of Channel 18(address 0892) the system knows that Directory Number 2083 is calling directory number 2055. Control memory address 0892 (80 hex) is pointing to 0880 (92 hex). See Figure 6.2. 16 17 18 1908920440 044916 17 18 19 Figure 6.2 Time-Switch Memory Setup (Channel 16)5. Once the connection is complete, the...
Page 792
TL-130200-1001Memory Dumps6.1 Call tracing involves analyzing the address contents of channel memory, control memories A and B, and pad memory. Memory dumps, or printouts of memory contents, are made by entering General Read (GR) commands at the terminal keyboard (see Section 2.0, Maintenance Commands). The GR commands for control memory A and B and pad memory dumps are listed in Table 6.2. Examples of Channel Memory dumps and a Pad Memory dump are also listed. Table 6.2Memory Dump General Read Commands...
Page 793
TL-130200-1001Call Tracing6.3 Assume that the OMNI SI in the following examples has an ExamplesExpansion File. The attendant line circuit is located in the Expansion File, group C, universal card slot 1, Circuit 4. _. Two-Party ConnectionThese examples use the Hardware Identification Number (HID) only. Final determination of the connection requires the data base listing or use of Recent Change. It is assumed that references are made to the memory cross-reference tables (see Table 6.1). Only the addresses...
Page 794
TL-130200-1001 4. See CEC control memory B dump in Table 6.6. Locate address for channel number 18 and group 0. Data BA is different from that in control memory A (82) which shows that this is a three party connection. 5. See pad memory dump in Table 6.7. Locate address by channel number 18 and group 0 (also use memory cross-reference table). Address OC90 contains data 17 which means that Bit 7 (CMM A) of the pad memory control word is set to 1. This indicates that interconnect memory is in use. Refer...
Page 795
5210TL-130200-1001 Connection Between6.3.5 Trace connection between files. Files 1. See channel memory Expansion File dump in Table 6.4. Address 025C has HID data 16.2. See control memory A dump in Table’65 and Control Memory 6 dump in Table 6.6 to see that addresses 0889 and OAB9 both have data 92. 3. Address 0892 shows interchange data B9 confirms connection.4. See channel memory Get Started File in Table 6.3. Address shows location to be file Y, universal card slot 3, circuit 7 (a line) at address...
Page 796
TL-130200-1001Table 6.3Channel Memory Get Started File 04000408 0410 0418 0420 0428 0430 0438 - 0440 0448 0450 0458FO FO - -FO FO - -FO FO - -FO FO - -FO FO - -FO FO - -FO FO - -FO FO - -FO 46 -. -11 37 - -03 FF - -01 91 - -EVEN CHANNEL GROUPS 0 1 - - Table 6.4 0200 02080210 0218 0220 02280230 02380240 0248 0250 0258 M-220FO FO FO FO FO FO FO FO FO FO FO FO FO FO FO FO FO FO FO FO FO FO FO FO FO FOFO FO FO FO FO FO FO Fd FO FO FO FO FO FO FO FO 03 FO FO FO 01 FO EVEN CHANNEL GROUPS 4 5 6...
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08000808 08100818 y.08200328 0830 0838 0840 0848 0850 08580860 0868 0870 0878 0880 0888 08900898 08A0 08A80880 08B8 5210GR DO 800 8BFPAGE DO D8 08 D8 D8 D8 D8 D8 D8 08 D8 D8 D8 D8 D8 D8 D8 08 D8 B2 D8 D8 08 D8 D8GRP 0 Table 5.5 Control Memory ATL-130200-1001 D8 D8 D8 D8 08 D8 -D8 D8 D8 08 08 D8 D8 D8 D8 08 D8 D8 D8 D8 D8 08 D8 92GRP 4D8 D8 D8 D8 D8 08 D8 D8 D8 D8 D8 D8 D8 D8 D8 D8 76 D8 B9 D8 08 D8BA 82GRP 1 D8 D8 D8 D8 D8 D8 D8 D8 D8 D8 D8 D8 08 D8 D8 D8 D8 D8 D8 D8 D8 D8 08 D8GRP 5GRP D8 08 D8 D8 08...
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TL-130200-1001 Table 6.6 Control Memory B GR DO A00 ABF PAGE DO OAOO OA08 OAl 0 OA18 OA20 OA28 OA30 OA38 OA40 OA48 OA50 OA58 OA60 OA68 OA70 OA78 OA80 OA88 OA90 OA98 OAAO OAA8 OABO OAB8M-222 D8 D8 D8;.. 08 D8 08 D8 D8 D8 D8 D8 D8 D8 D8 D8 D8 08 D8BA D8 D8 D8 D8 D8D8 D8 D8 D8 D8 D8 D8 08 D8 D8 D8 D8 D8 D8 D8 D8 D8 D8 D8 D8 D8 D8 D8 92GRP GRP 04D8 D8 D8 D8 08 .D8 D8 D8 D8 08 08 D8 D8 D8 D8 D8 76 D8 B9 D8 D8 D8 90 90GRP 1 D8 D8 D8 D8 D8 08 08 D8 D8 D8 D8 D8 D8 D8 D8 D8 D8 D8 08 D8 D8 D8 D8 D8GRP 5GRP D8 D8...
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GR DO COO CBFPAGE DO ocoo OC08 OClO O.Cl8 oc20 OC28 oc30 OC38 oc40 OC48 oc50 OC58 OC60 OC68 oc70OC78 OC80 OC88 oc90OC98 OCAO OCA8 OCBO OCB8 521007 07 07 07 0707 07 07 07 07 07 07 07 07 07 07 07 07 17 07 07 07 07 07GRP 0 Table 6.7 Pad Memory 07 07 07 07 0707 07 07 07 07 07 07 07 07 07 07 07 07 37 07 07 07 17 17GRP 1 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07GRP 5 -GRP 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 07GRP 6 07 07 07 07 0707 b7 07 07 07 07...
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TL-130200-1001 PAD MEMORY WORD LAYOUTCMMCMMPAD PADPAD -*km AB102 . . _.BITS 7, 6: interconnect memory steering bits. Bits 5, 4, 3: pad Information bits as follows: M-22481871 BITS 54DB lossNOTE: CMMA and CMMB are the ninth bit for control memory A and control memory B, respectively. Either bit set to true (1) indicates that the sample will be taken from the Interconnect memory; a bit set to false (0) indicates that the sample will be taken from the network information memory. 5210