ATT System 25 Maintenance Manual

							SYSTEM HARDWARE
Auxiliary Trunk (TN763)
The Auxiliary Trunk circuit pack interfaces four ports provided for customer-
provided equipment (CPE) and the TDM bus. It is connected to the CPE by
up to three pairs of wires. The transmission pair (T and R) carries voice
signals and touch-tone control signals. T and R also provides a loop start
seizure indication to the CPE. The seizure pair (SZ and SZ1) provides
seizure indication to the CPE. The signal pair (S and S1) provides answer
supervision and/or make-busy information from the CPE. Depending on the
application, the transmission pair only or all three pairs are connected to the
CPE.
Figure 3-21 shows the following Auxiliary Trunk unique circuitry:
l Ground detector circuit
l Port Input/Output (I/O) circuit
l Four port circuits.
Ground Detector Circuit: This circuit determines if an answer-supervision or
make-busy signal from the CPE is present. The ground detectors inputs
come from the port circuits as an analog current to the -48 volt dc supply.
Its output is a port control point to the port I/O circuit.
Port I/O Circuit: This circuit consists of bus expanders for communication
between the on-board microprocessor and the port circuits. It receives
commands from the on-board microprocessor and distributes them to the
individual port circuits. It also accesses the port circuit scan points and
passes the information to the on-board microprocessor.
Port Circuits: The four port circuits are identical. Each port circuit consists
of a codec, hybrid circuit, line transformer, relay driver, battery polarity
sensor, and surge protection circuit.
The codec is a 4-wire circuit that converts the analog signal from the CPE to
a PCM data signal. It converts an incoming PCM data signal from the NPE to
an analog signal. The hybrid circuit converts the 4-wire analog signal from
the codec to a 2-wire analog signal that is connected to the CPE by a line
transformer.
The relay driver buffers and inverts the relay drive signals from the port I/O
circuit so that a logic high input operates the appropriate relay. The relay
control circuitry provides the proper interfaces for CPE.
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The surge protection circuit provides lightning surge protection for the circuit
pack. Longitudinal surges are isolated from the hybrid and codec by the line
transformer.
Figure 3-21. Unique Auxiliary Trunk (TN763) Circuitry
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System Resources
The System Resource circuit packs are as follows:
l Service Circuit (ZTN85)
l Tone Detector (TN748)
l Pooled Modem (TN758).
Service Circuit (ZTN85)
The Service Circuit circuit pack provides the systems clock signals. It also
generates and receives tones. The Service Circuit circuit pack (Figure 3-22)
consists of the following:
l Bus buffers
l Sanity And Control Interface (SAKI)
l On-board microprocessor with external RAM
l Clock circuit
l Tone Generator
l Time slot table and counter
l Tone detector ports
l Port I/O and Sanity Check circuit.
The ZTN85 provides four touch-tone receivers, generates all tones for the
system, and supplies the system clocks. The ZTN85 can support up to 75
Dual Tone Multifrequency (DTMF) dialers. Each System 25 must contain one
Service Circuit circuit pack. Power for the circuit pack (+5 V dc) is provided
on the backplane.
Bus Buffers: There are four bus buffers on the circuit pack. The clock driver
and receive buffers interface three system clock signals (2.048 MHz, 8 kHz,
and 160 kHz) to the TDM bus. Two buffers interface the system tones (see
Table 3-A) between the TDM bus and the Service Circuit circuit pack. Music
is not provided by the Service Circuit but may be provided by a port interface
on a Tip Ring Line circuit pack (ZTN78).
SAKI: This circuit functions the same as in the SAKI in the common circuitry
for the intelligent port circuits.
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On-Board Microprocessor With External RAM: This circuit functions the
same as the microprocessor in the common circuitry for the intelligent port
circuits. In addition, it tells the dual-port RAM in the time slot table circuit the
appropriate time slots in which to place a tone. The external RAM also has
work space for complex tones (that is, those tones that vary with time).
Clock Circuit: The clock circuit consists of a 20.48-MHz oscillator, various
dividers, and shift registers. The clock circuit runs independently from the
rest of the Service Circuit circuitry. The clock circuits start running when the
circuit pack is first powered up and is not controlled by the on-board
microprocessor.
The output of the 20.48-MHz oscillator is fed to the clock divider. The divider
divides by 10, 2560, and 128. These circuits produce the 2.048-MHz, 8-kHz,
and 160-kHz clock signals, respectively. The clock generator feeds these
signals to the clock driver/receiver bus buffer and the tone clock. The tone
clock uses these signals to synchronize the counters in the tone generator
and time slot table circuits with the TDM bus.
Tone Generator: The tone generator consists of a digital signal processor
(DSP), a counter, and a dual-port tone RAM. The DSP operates at 10 MHz
and produces 24 different tones. The dual-port tone RAM stores these tones
in 24 different addresses. The counter under control of the tone clock causes
the DSP to transmit one sample of each tone every 8 kHz. The counter is
synchronized to the TDM bus and is offset to provide delay needed for
access time.
Time Slot Table and Counter: The time slot table consists of a dual-port time
slot table RAM and a counter. The dual-port RAM (DPRAM) contains 256
different addresses. These addresses correspond to the time slots on the
TDM bus. The counter sequences through the time slot table addresses in
the dual-port RAM and causes the proper tone(s) to be output by the dual-
port tone RAM on TDM bus time slots.
Tone Detector Ports: The Service Circuit circuit pack provides four Dual-
Tone Multifrequency (DTMF) detector port circuit interfaces via the TDM bus.
Each port circuit is connected to an NPE serial input and output. Ports 0, 1,
2, and 3 are DTMF tone detectors with NPE loop-around paths.
The four port circuits contain a DSP, NPE to DSP interface circuitry, a DSP
restart circuit, and an interrupt generator. One DSP implements two tone
receivers.
The TDM bus signals are connected to the DSP in serial form from the NPEs
by the DSP interface circuits. The DSP controls the output clocking of the
NPE. The system framing signal is synchronized and connects to the DSP.
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Port I/O and Sanity Check Circuit: This circuit interfaces the on-board
microprocessor to the port circuits and checks the sanity status of the port
circuits DSPs.
Figure 3-22. Service Circuit (ZTN85)
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Tone Detector (TN748)
The Tone Detector circuit pack provides four touch-tone receivers and two
general purpose tone receivers that detect appropriate system and network
tones on the TDM bus.
The Tone Detector circuit pack consists of the same common circuitry as the
intelligent port circuits and the following unique circuits (see Figure 3-23):
l Port I/O circuit
l Port and DSP Sanity check circuit
l Four touch-tone port circuits
l Two general purpose tone detector port circuits
l Two NPE loop-around test port circuits.
Up to a maximum of two Tone Detector circuit packs may be provided in the
system.
Port I/O and Sanity Check Circuit: This circuit interfaces the on-board
microprocessor to the port circuits and checks the sanity status of the port
circuits Digital Signal Processors (DSPs).
Port Circuits: There are eight port circuits. Six port circuits are connected to
NPEs. Port circuits 0, 1, 4, and 5 are DTMF tone detector ports. Each of the
six port circuits has an associated DSP, NPE to DSP interface circuitry, a
DSP restart circuit, and an interrupt filter. Port circuits 2 and 6 are general
purpose tone and detector ports. Port circuits 3 and 7 provide digital loop-back
testing of each NPE on the circuit pack.
The NPE serializes TDM bus signals that are connected to the DSP in serial
form from the NPEs by the DSP interface circuit. Serial clock and data
signals connect directly from the NPE to the DSP. The system framing signal
is synchronized and connects to the DSP.
The DSP restart circuit controls the DSPs. When the on-board
microprocessor is not functioning properly, the DSP restart circuit takes all of
the DSPs out of service. It restarts each individual DSP under control of the
port I/O and sanity check circuit.
The touch-tone DSPs, under control of the on-board microprocessor, write
data synchronously to the NPEs. The interrupt filter detects valid touch-tone
signals and allows end-to-end transmission while blocking end-to-end touch-
tone signaling.
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Figure 3-23. Tone Detector (TN748) Circuit
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Pooled Modem (TN758)
The Pooled Modem circuit pack supports 0-300 and 1200 bits per second
(bps) data speeds and provides the following:
l
l
lCircuitry to provide a signal compatible with the modulation formats of
the 212-series modems
Modem emulation (see below)
CapabilityData Module Mode
0-300 AsynchronousLow
300 Asynchronous300 Asynchronous
1200 Asynchronous1200 Asynchronous
Modem control functions corresponding to 212-series modem operations.
A maximum of two Pooled Modem circuit packs are allowed in a single
cabinet (six in a 3-cabinet system).
The Pooled Modem circuit pack (Figure 3-24) consists of common circuitry
and two conversion resources. The conversion resource (port) allows
communications between two dissimilar endpoints. For example, the Pooled
Modem circuit pack enables a digital data endpoint linked to an ADU
connected to a port on the Data Line circuit pack (TN726) to communicate
with either a local analog data endpoint, such as a personal computer with a
modem, or a remote host using a central office (CO) trunk connection. Each
port has two connections to the TDM bus. One connection is made to the
digital data endpoint using an ADU data module. The other connection is
made to an analog endpoint.
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Figure 3-24. Pooled Modem (TN758) Circuit
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Common Circuitry: The Pooled Modem common circuitry, which includes all
circuitry shown on Figure 3-24 except the Conversion Resource circuitry,
provides the same general function as the intelligent port common circuitry.
Conversion Resources: The two conversion resources (port circuits) are
identical and each contains the following:
l Microprocessor
l Transmit and Receive l-channel Controller (TRIC)
l Universal Synchronous/Asynchronous Receiver and Transmitter (USART)
l Data USART Clock (DUCK)
l Digital Signal Processor (DSP).
The microprocessor controls an on-board data module and modem. This
microprocessor communicates with the port circuit microprocessor over a
serial control channel. This channel allows the on-board microprocessor to
send messages to the port circuit microprocessor specifying call startup
information, option settings, information requests, various test modes, and
call termination information. It also allows the port circuit microprocessor to
inform the on-board microprocessor of various port circuit status information.
The DUCK and TRIC interface l-channel information between the port circuit
and the remote data module. The microprocessor controls the operation of
the DUCK and the TRIC by programming their internal registers. The DUCK
and TRIC together recreate the clock and serial data stream from the remote
data module, and process an on-board clock and serial data stream for
delivery to the remote data module. Control information, handshaking, and
RS-232C control leads are passed between the port circuit microprocessor
and the remote data module by the TRIC.
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