ATT System 25 Maintenance Manual

							SYSTEM HARDWARE
MEMORY BUS
COMMON
CONTROLCALLPROCESSORMEMORY
TDM BUS
SWITCHING
NETWORK
PORTCIRCUITSSERVICE
CIRCUITTONE
DETECTORPOOLED
MODEM
SYSTEM RESOURCES
TRUNKS,
VOICE TERMINALS,
DATA TERMINALS
Figure 3-4. System 25 Digital Switch
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							SYSTEM HARDWARE
Common Control
The Common Control circuitry consists of the Call Processor [ZTN82 (V1) or
ZTN128 (V2)] and Memory [ZTN81 (V1) or ZTN127 (V2)] circuit packs and
associated memory bus.
Memory Bus
The memory bus is a 60-wire (including grounds), 39-bit (16-data, 23-
address), 6-MHz frontplane flat ribbon cable.
Call Processor Circuit Pack [ZTN82 (V1) or ZTN128 (V2)]
The Call Processor runs the system feature software. It is powered from the
backplane by +5 and -5 volts. It also draws -48 volts from the backplane to
drive the Emergency Transfer Unit. Each system must include one Call
Processor CP. The Call Processor circuitry, as shown in Figure 3-5, includes:
l Microprocessor
l Memory management
l On-board memory
l EIA channels
l Network controller
l Clock
l Frontplane interface
l Reset circuitry
l Bus error circuitry
l Interrupt circuitry
l Emergency Transfer Unit Control.
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							SYSTEM HARDWARE
Figure 3-5. Call Processor [ZTN82 (V1) or ZTN128 (V2)] Circuitry
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							SYSTEM HARDWARE
Microprocessor: A 68010 16-bit microprocessor that executes call
processing and data processing features. This includes all maintenance,
administration, testing, and reporting software.
Memory Management: Memory management separates the on-board
Random Access Memory (RAM) into 1024 memory pages of 256 bytes each.
Each page is read and write protected, generates bus errors when violated,
and each is recappable allowing data areas to remain contiguous.
On-Board Memory: On-board memory includes 64 K bytes of Read Only
Memory (ROM) containing the power-up tests and the switch operating
system. In addition, there are 80 K bytes of protected RAM containing
writable data storage for call processing. The RAM is backed up by an on-
board trickle-charge battery that maintains memory contents for up to 2
months. Of the 80 K RAM, 24 K is dedicated to translation data. The
remainder is dedicated to call status data and the operating system message
queues.
EIA Channels: Four asynchronous RS-232C EIA ports (1-4) are included to
permit communication with an administration terminal, a maintenance
terminal, a Station Message Detail Recording (SMDR) device, and a Digital
Tape Unit.
Network Controller: The network controller transmits control channel
messages between the Call Processor and the port circuits over the TDM
bus. The controller also monitors system clocks.
The controller includes an 8-bit microprocessor that acts as a throttle,
passing messages between the Call Processor and the port board
microprocessors.
All uplink messages from the port circuits are checked for consistency and
passed to the common control. The controller is the distribution control point
for all downlink control messages. It continuously scans, over the TDM bus,
the port circuit microprocessors for sanity and activity. External RAM
associated with this microprocessor stores control channel information and
port related information.
The controller consists of bus buffers and a System And Control Interface
(SAKI). The bus buffers provide the interface between the TDM bus and the
on-board data buses to the SAKI. The SAKI receives and transmits control
messages on the first five time slots on the TDM bus. The microprocessor
communicates with the SAKI and external RAM over the address and data
bus.
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							SYSTEM HARDWARE
Clock: A clock provides time of day information in seconds, minutes, and
hours and the date to the 68010 microprocessor. The clock automatically
adjusts for leap years. An on-board battery backs up the clock so that
accurate time is maintained even when the system power is off.
Frontplane Interface: Dedicated buffers provide an interface to the
frontplane, which is the communication path to the Memory circuit pack.
Reset Circuitry: The processor is automatically reset when power is turned
on, when the +5 volt power supply drops below 4.5 volts (after it returns to
+5 volts), or when the network controller detects the processor insane. The
processor can also reset the network controller when it detects the network
controller insane.
Bus Error Circuitry: Bus errors suspend the processor from executing code.
Bus errors are generated when memory management detects illegal reads or
writes to RAM, when the processor attempts to access circuit packs or chips
not physically present, or when the network controller detects the processor
insane.
Interrupt Circuitry: Interrupts are prioritized into seven levels, of which the
highest (level 7) is non-maskable. The interrupts are:
Interrupt
Level
AC Fail7
Work cycle6
Off board5
Two EIA ports4
Other two EIA ports3
Off board2
Off board1
Emergency Transfer Unit (ETU) Control: Removes -48 V dc power from the
systems ETUs when the system loses power or a major system malfunction
occurs.
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							SYSTEM HARDWARE
Memory Circuit Pack [ZTN81 (V1) or ZTN127 (V2)]
The Memory circuit pack provides for the storage of software associated with
system operation. This software includes call and administration processing
and other related programs. The circuit pack is powered from the backplane
by +5 volts. Each system must include one Memory circuit pack. The
Memory circuit pack circuitry (Figure 3-6) includes:
l Address and data buffers
l ROM array
l ROM select
l Timing and control logic
l Built-in TDM bus termination resistors.
Address and Data Buffers: The address and data buffers interface the
Memory circuit pack to the address and data lines on the frontplane.
ROM Array: The memory array consists of 16 ROM devices of 32 K, 8-bit
bytes each, for a total capacity of 512 K ROM. The ROMs are organized into
pairs allowing the Call Processor to access 16-bit words.
ROM Select: The memory selects the proper pair of ROMs according to
address information.
Timing and Control Logic: This circuit controls the access speed of the ROM
(no wait states) by returning a Data Transfer Acknowledge signal at the
proper time.
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Termination Resistors: These resistors are required for proper operation of
the TDM bus. The ZTN81 (V1) or ZTN127 (V2) provides the proper
termination for one end of the bus, and a plug-in TDM bus termination circuit
card (plugs into cabinet backplane) is used to terminate the other end. For
this reason, the ZTN81 (V1) or ZTN127 (V2) CP must always be located in
slot #1 of Cabinet 1. 
						

							SYSTEM HARDWARE
TERMINATORRESISTORSROMSELECT
FRONT PANEL
MEMORY BUS
(TO CALL
PROCESSOR
CIRCUIT
PACK )
ADDRESS
ANDROM
DATA BUFFERSTIMINGARRAY
AND
CONTROL
TOTDMBUS
Figure 3-6. Memory [ZTN81 (V1) or ZTN127 (V2)] Circuitry
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							SYSTEM HARDWARE
Switching Network
System 25 uses distributed processing techniques to provide switched voice
and data services. The switch operates at 64 Kbps. The switching network
consists of the following:
l Time Division Multiplex (TDM) bus
l Port Circuits
l System Resources.
The TDM bus connects the intelligent ports to the Common Control circuit
packs and other ports through the network control circuit. The system
resource circuits provide tone sources, receivers, detectors, and pooled
modems. The intelligent ports connect external communications facilities to
the TDM bus.
TDM Bus
The TDM bus consists of two groups of eight signal leads and five control
leads, each with matching grounds. The port circuit packs place digitized
voice [pulse code modulated (PCM)] signals on the bus.
The bus operates at 2.048 MHz. The system framing pulse is 8 kHz. This
provides 256 time slots (0-255) on the bus. The time slots are 488 ns wide.
Time slots are generated as shown in Figure 3-7. The first five time slots are
used for communications between the Common Control, the intelligent port,
and resource circuit packs. Two time slots are required for each 2-party
conversation. Each party transmits (talks) on one time slot and receives
(listens) on another. Only five parties are allowed in a conference. During a
conference connection, each member of the conference transmits on an
individual time slot while receiving on as many as four other time slots. The
actual switch capacity is 115 simultaneous 2-party conversations.
Table 3-A shows the allocation of the 256 time slots. Five are used for
system control, 15 for tones, 235 for call processing, and 1 is not used.
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							SYSTEM HARDWARE
SYSTEM FRAME
8 KHZ
(125 MICROSECONDS)
488 NANOSECONDSI
SYSTEM CLOCK_______
2.048 MHZ
TIME SLOTS O45255 0
256 TIME SLOTS
12
3
Figure 3-7. TDM Bus Time Slot Generation (Not a Timing Diagram)
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							SYSTEM HARDWARE
Table 3-A. TDM Bus Time Slots
TIME SLOT NO.
00
thru
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
thru
254
255
FUNCTION
Control
(5)
-Tones-(15)
Dial Tone
Busy Tone
Reorder Tone
Ringback Tone
Data-Null
Voice-Null
Music
697 Hz*
770 Hz*
852 Hz*
941 Hz*
1209 Hz*
1336 Hz*
1447 Hz*
1637 Hz*
Call
Processing
(235)
Not Used
(1)
* These tones are used to generate touch-tone signals.
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