ATT System 25 Maintenance Manual

SYSTEM HARDWARE
MEMORY BUS
COMMON
CONTROLCALLPROCESSORMEMORY
TDM BUS
SWITCHING
NETWORK
PORTCIRCUITSSERVICE
CIRCUITTONE
DETECTORPOOLED
MODEM
SYSTEM RESOURCES
TRUNKS,
VOICE TERMINALS,
DATA TERMINALS
Figure 3-4. System 25 Digital Switch
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SYSTEM HARDWARE
Common Control
The Common Control circuitry consists of the Call Processor [ZTN82 (V1) or
ZTN128 (V2)] and Memory [ZTN81 (V1) or ZTN127 (V2)] circuit packs and
associated memory bus.
Memory Bus
The memory bus is a 60-wire (including grounds), 39-bit (16-data, 23-
address), 6-MHz frontplane flat ribbon cable.
Call Processor Circuit Pack [ZTN82 (V1) or ZTN128 (V2)]
The Call Processor runs the system feature software. It is powered from the
backplane by +5 and -5 volts. It also draws -48...

SYSTEM HARDWARE
Figure 3-5. Call Processor [ZTN82 (V1) or ZTN128 (V2)] Circuitry
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SYSTEM HARDWARE
Microprocessor: A 68010 16-bit microprocessor that executes call
processing and data processing features. This includes all maintenance,
administration, testing, and reporting software.
Memory Management: Memory management separates the on-board
Random Access Memory (RAM) into 1024 memory pages of 256 bytes each.
Each page is read and write protected, generates bus errors when violated,
and each is recappable allowing data areas to remain contiguous.
On-Board Memory: On-board memory...

SYSTEM HARDWARE
Clock: A clock provides time of day information in seconds, minutes, and
hours and the date to the 68010 microprocessor. The clock automatically
adjusts for leap years. An on-board battery backs up the clock so that
accurate time is maintained even when the system power is off.
Frontplane Interface: Dedicated buffers provide an interface to the
frontplane, which is the communication path to the Memory circuit pack.
Reset Circuitry: The processor is automatically reset when power is...

SYSTEM HARDWARE
Memory Circuit Pack [ZTN81 (V1) or ZTN127 (V2)]
The Memory circuit pack provides for the storage of software associated with
system operation. This software includes call and administration processing
and other related programs. The circuit pack is powered from the backplane
by +5 volts. Each system must include one Memory circuit pack. The
Memory circuit pack circuitry (Figure 3-6) includes:
l Address and data buffers
l ROM array
l ROM select
l Timing and control logic
l Built-in TDM bus...

SYSTEM HARDWARE
TERMINATORRESISTORSROMSELECT
FRONT PANEL
MEMORY BUS
(TO CALL
PROCESSOR
CIRCUIT
PACK )
ADDRESS
ANDROM
DATA BUFFERSTIMINGARRAY
AND
CONTROL
TOTDMBUS
Figure 3-6. Memory [ZTN81 (V1) or ZTN127 (V2)] Circuitry
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SYSTEM HARDWARE
Switching Network
System 25 uses distributed processing techniques to provide switched voice
and data services. The switch operates at 64 Kbps. The switching network
consists of the following:
l Time Division Multiplex (TDM) bus
l Port Circuits
l System Resources.
The TDM bus connects the intelligent ports to the Common Control circuit
packs and other ports through the network control circuit. The system
resource circuits provide tone sources, receivers, detectors, and pooled
modems. The...

SYSTEM HARDWARE
SYSTEM FRAME
8 KHZ
(125 MICROSECONDS)
488 NANOSECONDSI
SYSTEM CLOCK_______
2.048 MHZ
TIME SLOTS O45255 0
256 TIME SLOTS
12
3
Figure 3-7. TDM Bus Time Slot Generation (Not a Timing Diagram)
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SYSTEM HARDWARE
Table 3-A. TDM Bus Time Slots
TIME SLOT NO.
00
thru
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
thru
254
255
FUNCTION
Control
(5)
-Tones-(15)
Dial Tone
Busy Tone
Reorder Tone
Ringback Tone
Data-Null
Voice-Null
Music
697 Hz*
770 Hz*
852 Hz*
941 Hz*
1209 Hz*
1336 Hz*
1447 Hz*
1637 Hz*
Call
Processing
(235)
Not Used
(1)
* These tones are used to generate touch-tone signals.
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