Analog Devices Blackfin AV EZExtender Manual Rev 21

							Blackfin A-V EZ-Extender Manual 2-7 A-V EZ-Extender Hardware Reference
Jumpers
Before using the Blackfin A-V EZ-Extender, follow the procedure in “A-V 
EZ-Extender Setup” on page 1-2.
Figure 2-2 shows the jumper header locations. The jumper headers are 
divided to show each jumpers placement and rotation. The jumpers are 
described by the pins of the header on which the jumpers can be placed.  Figure 2-2. Jumper Locations 
						

							Jumpers
2-8 Blackfin A-V EZ-Extender ManualFor example, 
JP3.4/6/8 refers to a single jumper that can be placed across 
pins
4 and6 (or pins6 and8) of JP3. The dark pin indicates pin1 of each 
header. 
Video Test Loopback Jumpers (JP1.1/2, JP1.3/4, 
JP1.5/6)
For test purposes only, the video test jumpers loop-back the video 
encoder’s output signals to the video decoder’s input signals. By default, 
none of the video test loopback jumpers are installed. 
Connector Voltage Selection Jumper (JP2)
The camera module and LCD display interfaces can be powered via the 
extender. The actual voltage of the interfaces, 3.3V or 5V, is determined 
by the 
JP2 jumper’s placement (see Table 2-2).
TWI Source Selection Jumpers (JP3.3/5/7, 
JP3.4/6/8)
Due to the fact that some Blackfin processors feature a built-in 2-wire 
interface (TWI), while others need to emulate the interface with program-
mable flags, two jumpers are provided to plug the A-V EZ-Extender to 
both TWI sources (see Table 2-3). Table 2-2. Jumper Locations and Connector Voltages
Jumper Location Connector Voltage
JP2.1/23.3V
JP2.2/35V
Not installed No power 
						

							Blackfin A-V EZ-Extender Manual 2-9 A-V EZ-Extender Hardware Reference
PDWN Connect Jumper (JP3.9/10)
Depending on the application, the PDWN pin of the OmniVision and 
Kodak cameras can be left floating or controlled by a flag pin 
(seeTable 2-4).
Decoder HSYNC Disconnect Jumper (JP3.11/12)
To connect the horizontal sync signal of the video decoder to the PPI0 
frame sync signal of the processor, install jumper 
JP3.11/12; otherwise, 
the decoder’s horizontal sync is disconnected.
Decoder VSYNC Connect Jumper (JP3.13/14)
To connect the vertical sync signal of the video decoder to the PPI0 frame 
sync signal of the processor, install jumper 
JP3.13/14; otherwise, the 
decoder’s vertical sync is disconnected. Table 2-3. Jumper Locations and TWI Interface Sources
Jumper Location TWI Interface Source
JP3.3/5 and JP3.4/6Programmable flags
JP3.5/7 and JP3.6/82-wire interface of the processor
Table 2-4. PWDN Pin Connections
JP3.9/10 Jumper PDWN Connection
Uninstalled
PDWN is not used and, by default, the cameras function in standard mode 
Installed The 
PDWN functionality of the cameras is controlled by a flag pin of the 
processor.  
						

							Jumpers
2-10 Blackfin A-V EZ-Extender Manual
Encoder HREF Connect Jumper (JP3.15/16)
To connect the horizontal sync signal of the video encoder to the PPI0 
frame sync signal of the processor, install jumper 
JP3.15/16; otherwise, 
the encoder’s horizontal reference is disconnected. 
Encoder VSYNC Connect Jumper (JP3.17/18)
To connect the vertical sync signal of the video encoder to the PPI0 frame 
sync signal of the processor, install jumper 
JP3.17/18; otherwise, the 
encoder’s vertical sync is disconnected. 
Decoder Output Enable Jumper (JP3.19/20)
When installed, jumper JP3.19/20 enables the video decoder’s data out-
put signals on the 
VID_IN bus.
SNAPSHOT_FODD Disconnect Jumper (JP3.21/22)
The SNAPSHOT_FODD net of the Blackfin A-V EZ-Extender is a general-pur-
pose flag pin. The flag pin connects to 
SNAPSHOT (the Kodak camera 
evaluation board’s signal) and 
FODD (the OmniVision camera evaluation 
board’ control signal). Do not install the jumper unless the processor 
needs to control these signals. The flag pin also connects to the SPI select 
pin of the AD1836A audio codec—do not install 
JP3.21/22 when using 
the audio interfaces. 
						

							Blackfin A-V EZ-Extender Manual 2-11 A-V EZ-Extender Hardware Reference
PPI Clock Setup Jumpers (JP4.1/2, JP4.3/4, JP4.5/6, 
JP4.7/8)
The PPI_CLK signals of PPI0 and PPI1 are configured by the clock setup 
jumpers (see Table 2-5). For more information, refer to Figure 2-1 on 
page 2-4. 
PPI0 D8–15 Enable Jumper (JP5.1/2)
The JP5.1/2 jumper, when is not installed, disables the upper eight bits of 
the 
PPI0 data bus. This allows the signals connected to the upper eight bits 
of the PPI data bus of the EZ-KIT Lite to be used elsewhere on the board.
To disable and re-use the upper eight bits of the 
VID_IN and PPI0 data 
busses, install 
JP5.1/2.  Table 2-5. PPI Clock Setup Jumper Results
Jumper Location Result
JP4.1/2Connects EXT_VID_CLK to the on-board 27 MHz oscillator. For more infor-
mation about the 
EXT_VID_CLK signal, see the JP4.3/4 description. 
JP4.3/4Connects PPI0_CLK to the EXT_VID_CLK net. The EXT_VID_CLK net is the 
external clock, which drives the input clock of all three camera module con-
nectors, plus the flat panel display connector. Depending on the 
JP4 jumper 
installation, 
EXT_VID_CLK can be generated by the PIXEL_CLK net, the 
VDEC_CLKOUT net, a socket (U8), or the on-board 27 MHz oscillator. 
JP4.5/6Connects VDEC_CLKOUT to PPI0_CLK; VDEC_CLKOUT drives the PPI0 clock 
when the video decoder is used.
JP4.7/8Connects the PIXEL_CLK net, which is an output from the three camera inter-
faces, to 
PPI0_CLK. 
						

							Jumpers
2-12 Blackfin A-V EZ-Extender Manual
VID_OUT Data Bus Control Jumpers (JP5.3/4, 
JP5.5/6)
The JP5.3/4 and JP5.5/6 jumpers are used together to set up the direc-
tion of and enable/disable the 
VID_OUT data bus drivers. Table 2-6 shows 
different combinations of 
JP5.3/4 and JP5.5/6.
PPI0_SYNC1 Direction Setup Jumper (JP6.1/3/5)
The direction of the PPI0_SYNC1 signal can be either fixed or programmed, 
depending on the state of a general-purpose flag. Table 2-7 shows how to 
set up the 
PPI0_SYNC1 direction.  Table 2-6. Video Out Data Bus Control Jumper Combinations
JP5.3/4 JP5.5/6 VID_OUT Status
Uninstalled Uninstalled
VID_OUT, PPI1 are all not driven; PPI0 depends on the 
state of 
JP9.2/4/6
Uninstalled InstalledPPI1 drives VID_OUT
Installed UninstalledPPI0 drives VID_OUT
Installed InstalledPPI0 drives VID_OUT, and VID_OUT drives PPI1 
(loop-back mode)
Table 2-7. Setting Direction of PPI0_SYNC1 (JP6.1/3/5)
Jumper Location PPI0_SYNC1 Direction
JP6.1/3Controlled by a flag pin
JP6.3/5Input to the processor
Uninstalled Output from the processor 
						

							Blackfin A-V EZ-Extender Manual 2-13 A-V EZ-Extender Hardware Reference
PPI0_SYNC2 Direction Setup Jumper (JP6.2/4/6)
The direction of the PPI0_SYNC2 signal can be either fixed or programmed, 
depending on the state of a general-purpose flag. Table 2-8 shows how to 
set the 
PPI0_SYNC2 direction.
I2S Enable Jumper (JP7.1/2)
When JP7.1/2 is installed, the SPORT signals are routed for I2S SPORT 
communication protocol mode. To accomplish this, the receive and trans-
mit clocks of the processor are driven by the output clock of the 
AD1836A audio codec. The same is done for the frame sync signals. 
SPORT Data Connect Jumpers (JP7.3/4, JP7.5/6)
The JP7.3/4 and JP7.5/6 jumpers connect data output pins (ASDATA1 and 
ASDATA2) of the audio codec to the primary and secondary SPORT data 
input pins of the processor. The audio codec is driving these pins; with the 
help of the 
JP7.3/4 and JP7.5/6 jumpers, the processor’s pins can be 
re-used when the codec is disabled. Table 2-8. Setting Direction of PPI0_SYNC2 (JP6.2/4/6)
Jumper Location PPI0_SYNC2 Direction
JP6.2/4Controlled by a flag pin 
JP6.4/6Input to the processor
Uninstalled  Output from the processor 
						

							Jumpers
2-14 Blackfin A-V EZ-Extender Manual
VID_OUT Bus SYNC Source Select Jumpers 
(JP8.1/3/5, JP8.2/4/6)
The source of the PPI frame sync signals depends on the PPI port driving 
the 
VID_OUT bus. When using PPI0, place the jumpers at JP8.1/3 and 
JP8.2/4. When using PPI1, place the jumpers at JP8.3/5 and JP8.4/6. 
VID_OUT Bus SYNC Enable Jumper (JP8.7/8)
To enable the VID_OUT frame sync signals, install JP8.7/8.
AV_RESET Source Jumper (JP9.1/3/5)
The source of ICs reset on the Blackfin A-V EZ-Extender is controlled by 
either a flag pin or a system reset; the latter also resets the Blackfin proces-
sor (seeTable 2-9).
Table 2-9. Jumper Reset Sources
Jumper Location Reset Source
JP9.1/3Flag pin multiplexed with PPI1_D11
JP9.3/5
System reset generator
Uninstalled  ICs are not reset 
						

							Blackfin A-V EZ-Extender Manual 2-15 A-V EZ-Extender Hardware Reference
PPI0_D Direction Setup Jumper (JP9.2/4/6)
The direction of the PPI0_D[15:0] signals can be a fixed direction or can 
be programmed, depending on the state of a general-purpose flag. 
Table 2-10 shows how to set up the 
PPI0_D[15:0] direction.
Audio Loopback Jumpers (JP10.1/2, JP10.3/4)
The JP10.1/2 and JP10.3/4 jumpers loop-back audio input to output for 
test purposes and should not be installed. Table 2-10. Setting Direction of PPI0_D[15:0] (JP9.2/4/6)
Jumper Location PPI0_D[15:0] Direction
JP9.2/4Controlled by a flag pin 
JP9.4/6Input to the processor
Uninstalled Output from the processor 
						

							Jumpers
2-16 Blackfin A-V EZ-Extender Manual