Analog Devices Blackfin AV EZExtender Manual Rev 21

							Blackfin A-V EZ-Extender Manual 1-5 A-V EZ-Extender Interfaces
J6 is a connector designated for a Micron camera sensor evaluation mod-
ule. The interface has been tested with the Micron MT9V022 camera. For 
information about Micron camera sensors and evaluation boards, go to 
http://www.micron.com.
J4 is a connector designated for an OmniVision camera sensor evaluation 
module. The interface has been tested with the OmniVision OV6630AA 
camera. For information about OmniVision camera sensors and evalua-
tion boards, go to 
http://www.ovt.com. 
P4 is a connector designated for a Kodak camera sensor evaluation mod-
ule. The interface has been tested with the Kodak KAC-9628 camera. For 
information about Kodak camera sensors and evaluation boards, go to 
http://www.kodak.com. 
To connect the Blackfin A-V EZ-Extender to a camera module, first 
determine the source of the PPI clock. To learn about possible clock set-
tings, refer to “PPI Clock Setup Jumpers (JP4.1/2, JP4.3/4, JP4.5/6,  Figure 1-1. Camera Orientation 
						

							Flat Panel Display Interface
1-6 Blackfin A-V EZ-Extender ManualJP4.7/8)” on page 2-11. Then set the direction of the data and frame sync 
signals, which depend on the camera’s configuration. The data must be set 
as input to the PPI port; refer to “System Architecture” on page 2-2 and 
“Jumpers” on page 2-7 for details.
Before using the camera interfaces, follow the procedure in “A-V 
EZ-Extender Setup” on page 1-2.
Flat Panel Display Interface
The flat panel display interface (FPDI) consists of a 31-pin DB9 connec-
tor linked to the PPI port and frame sync signals of the processor. For a 
general overview of the display interface connections, see Figure 2-1 on 
page 2-3; for details, see the “A-V EZ-Extender Schematic” on page B-1.
A timing and functional analysis is required to determine whether a spe-
cific LCD module can connect to the Blackfin A-V EZ-Extender. An 
example of display that can connect to the extender is the NEC 
NL6448BC20-08 display.
The power for the backlight feature of the LCD module must be 
provided by the customer (use the backlight inverter recommended 
by the manufacturer). In addition, it is necessary to purchase a 
cable to connect the Blackfin A-V EZ-Extender to the display; for 
example, FDC31/xxxxAFF03 from Axon Cable 
(
www.axon-cable.com, part number FDC31/xxxxAFF03). Different 
length cables are available.
Before using the interface, follow the procedure in “A-V EZ-Extender 
Setup” on page 1-2. 
						

							Blackfin A-V EZ-Extender Manual 1-7 A-V EZ-Extender Interfaces
Example Programs
Example programs are provided with the A-V EZ-Extender EZ-KIT Lite 
to demonstrate various capabilities of the product. The programs are 
included in the product installation kit and can be found in the 
Examples 
folder of the installation. Refer to a readme file provided with each exam-
ple for more information.
CCES users are encouraged to use the example browser to find examples 
included with the EZ-KIT Lite Board Support Package. 
						

							Example Programs
1-8 Blackfin A-V EZ-Extender Manual 
						

							Blackfin A-V EZ-Extender Manual 2-1 
2 A-V EZ-EXTENDER 
HARDWARE REFERENCE
This chapter describes the hardware design of the Blackfin A-V 
EZ-Extender. 
The following topics are covered.
“System Architecture” on page 2-2
Describes the extender board configuration and explains how the 
board components interface with the processor and EZ-KIT Lite.
“Jumpers” on page 2-7
Describes the configuration jumpers. 
						

							System Architecture
2-2 Blackfin A-V EZ-Extender Manual
System Architecture
A block diagram of the Blackfin A-V EZ-Extender is shown in Figure 2-1. 
Not shown in the diagram is the analog audio interface, which is a simple 
connection between the serial port of the processor and AD1836A audio 
codec. The audio interface connects directly to 
SPORT0 of the expansion 
interface.
In Figure 2-1, unidirectional buffers are show as triangle symbols, while 
bidirectional buffers are shown as two overlapping triangles. For both 
types of buffers, an output-enable signal comes out of the top and is active 
LOW. For bidirectional buffers, a second signal for the direction is shown. 
When this net is pulled 
HIGH, the buffer is driving in the direction of the 
arrow in the center; when 
LOW, the buffer is driving in the opposite 
direction.
Before applying power to the system, follow the procedure in “A-V 
EZ-Extender Setup” on page 1-2.
The video interface can be split into two main signal sets: 
VID_IN and 
VID_OUT. Both signal sets consist of a 16-bit data bus, two frame sync sig-
nals, and a data clock. 
VID_IN connects to the video decoder and all 
camera interfaces. 
VID_IN connects only to the PPI0 of the EZ-KIT Lite. 
VID_OUT connects to the video encoder and flat panel display interface. On 
the expansion interface, 
VID_OUT connects to either PPI0 or PPI1 of the 
EZ-KIT Lite.  
						

							Blackfin A-V EZ-Extender Manual 2-3 A-V EZ-Extender Hardware Reference
Figure 2-1. A-V EZ-Extender Block Diagram 
						

							System Architecture
2-4 Blackfin A-V EZ-Extender ManualTable 2-1 summarizes the signals coming and going on the expansion 
interface connectors. 
Table 2-1. Signals of Expansion Interface Connectors
Net/Bus Name
(Direction)Blackfin A-V EZ-Extender Function Relevant 
Configuration 
Jumpers 
PPI0_D[0:15]
(Bi)Connects the processor’s 
PPI0 data pins to the 
VID_IN_D[0:15] or VID_OUT_D[0:15] buses, depend-
ing on the jumper settings. This allows 
PPI0 to interface 
with all video interfaces on the board. The bus can be 
bidirectional, where the direction is fixed with a jumper 
or controlled by a flag pin.
JP5.3/4,
JP9.2/4/6
PPI0_CLK
(Output)The clock related to the data on 
PPI0. This can come 
from an on-board oscillator, one of the video interfaces, 
or a socket that allows a user-supplied oscillator.JP4.1/2,
JP4.3/4,
JP4.5/6,
JP4.7/8 
PPI0_SYNC1
(Bi)The frame sync signal going to the processor’s PPI0_SYNC1 pin. The signal behaves as HSYNC or HREF 
for the video interfaces. The signal also can be used to 
drive the FPDI’s
HS signal. The signal can be bidirec-
tional, where the direction is fixed with a jumper or con-
trolled by a flag pin.
JP6.1/3/5,
JP8.1/3/5,
JP8.7/8
PPI0_SYNC2
(Bi)The frame sync signal going to the processor’s PPI0_SYNC2 pin. The signal behaves as VSYNC or VREF 
for the video interfaces. In addition, the signal can drive 
the FPDI’s
VS signal. The signal can be bidirectional, 
where the direction is fixed with a jumper or controlled 
by a flag pin.
JP6.2/4/6,
JP8.2/4/6,
JP8.7/8
PPI1_D[0:15]
(Bi)Connects the processor’s 
PPI1 data pins to the 
VID_OUT_D[0:15] bus. The VID_OUT_D[0:15] bus 
interfaces with the output video interfaces (FPDI and 
video encoder). The bus can be bidirectional but intended 
to be an input. Changing the direction is necessary only 
for test purposes and allows 
PPI0 to loop-back to PPI1. 
Note: 
D2, D3, and D10 of the bus have other functions 
(follows). 
JP5.3/4,
JP5.5/6,
JP3.9/10,
JP3.3/5/7
JP3.4/6/8 
						

							Blackfin A-V EZ-Extender Manual 2-5 A-V EZ-Extender Hardware Reference
PPI1_D10
(Bi)The multifunction net that typically functions as the 
D10 
pin of 
PPI1 but, with a jumper, also can connect to the 
PDWN input of the OmniVision and Kodak camera inter-
faces.
JP3.9/10,
JP5.3/4,
JP5.5/6
PPI1_D2
(Bi)The multifunction net typically functions as the 
D2 pin of 
PPI1 but also can function as the data signal for the pro-
cessor’s 2-wire interface (TWI). Used to program the 
internal configuration registers of most video interfaces.
JP3.3/5/7,
JP5.3/4,
JP5.5/6
PPI1_D3
(Bi)The multifunction net typically functions as the 
D2 pin of 
PPI1 but also can function as the data signal for the pro-
cessor’s TWI. Used to program the internal configuration 
registers of most video interfaces.
JP3.4/6/8,
JP5.3/4,
JP5.5/6
FLAG_SDA
(Bi)In systems whose processor does not have a TWI, the sig-
nal connects to one of the processor’s flag pins to emulate 
the TWI data pin and configure the internal registers of 
most video interfaces.
JP3.3/5/7 
FLAG_SCL_DIR_ 
CTRL
(Input)In systems whose processor does not have a TWI, the sig-
nal connects to one of the processor’s flag pins to emulate 
the TWI clock signal and configure the internal registers 
of most video interfaces.
JP3.4/6/8
PPI1_CLK
(Output)The clock driving the EZ-KIT Lite’s 
PPI1 clock input. 
The source of this clock can be 
PPI0_CLK, the on-board 
27 MHz oscillator, or a socket accepting oscillators of 
other frequencies.
JP4.1/2,
JP4.3/4,
JP4.5/6,
JP4.7/8
PPI1_FS1
(Input)The signal driven to the 
HS signal of the FPDI. The out-
put going to the FPDI can be disabled by a jumper.JP8.1/3/5,
JP8.7/8
PPI1_FS2
(Input)The signal driven to the 
VS signal of the FPDI. The out-
put going to the FPDI can be disabled by a jumper.JP8.2/4/6,
JP8.7/8
SNAPSHOT_FODD_
SSEL
(Bi)The audio codec’s SPI slave select signal; also can connect 
to the 
SNAPSHOT input of the Kodak interface or the FODD 
output of the OmniVision interface.
JP3.21/22
SCK
(Input)The SPI serial clock used to program the control register 
of the AD1836A audio codec.
Table 2-1. Signals of Expansion Interface Connectors (Cont’d)
Net/Bus Name
(Direction)Blackfin A-V EZ-Extender Function Relevant 
Configuration 
Jumpers  
						

							System Architecture
2-6 Blackfin A-V EZ-Extender Manual
MOSI
(Output)The SPI serial output data signal used to program the 
control register of the AD1836A audio codec.
MISO
(Output)The SPI serial input data signal used to read the control 
register of the AD1836A audio codec.
RSCLK0
(Bi)The processor’s 
SPORT0 receive clock signal connected to 
the serial clock on the digital side of the audio codec’s 
analog input. In I
2S mode, the signal can connect to the 
TSCLK0 net.
JP7.1/2
RFS0
(Bi)The processor’s 
SPORT0 receive frame sync signal con-
nected to the frame sync on the digital side of the audio 
codec’s analog input. In I
2S mode, the signal can connect 
to the 
TFS0 net.
JP7.1/2
DR0PRI
(Output)A connection to the data output of the audio codec; can 
be disconnected with a jumper if needed for another pur-
pose.
JP7.3/4
DR0SEC
(Output)A secondary connection to the data output of the audio 
codec. Can be disconnected with a jumper if needed for 
another purpose.
JP7.5/6
TSCLK0
(Bi)The processor’s 
SPORT0 transmit clock signal, connects to 
the serial clock on the digital side of the audio codec’s 
analog output. In I
2S mode, the signal can connect to the 
RSCLK0 net.
JP7.1/2
TFS0
(Bi)The processor’s 
SPORT0 transmit frame sync signal. Con-
nects to the frame sync on the digital side of the audio 
codec’s analog output. In I
2S mode, the signal can con-
nect to the 
RFS0 net. 
JP7.1/2
DT0PRI
(Input)A connection to the data input of the audio codec.
DT0SEC
(Input)A secondary connection to the data input of the audio 
codec.
Table 2-1. Signals of Expansion Interface Connectors (Cont’d)
Net/Bus Name
(Direction)Blackfin A-V EZ-Extender Function Relevant 
Configuration 
Jumpers