Acer Extensa 670 Service Guide

4-2Theory of Operation 4.2.2 Memory Subsystem
The memory subsystem comprises the following components:
· Main memory
· L2 Secondary Memory (cache)
· Flash ROM
The Extensa Series uses fast Extended Data Out (EDO) DRAM for main and video memory and
high-speed synchronous, pipelined burst SRAM  for L2 cache memory. Main BIOS and Video BIOS
are stored in Flash ROM.
4.2.2.1 Main Memory
The 67x Series Notebooks come standard with 16 MB main memory, expandable to 80 MB.
Memory expansion accommodations are...

Service Guide4-3 4.2.5 Keyboard Subsystem
The keyboard subsystem, implemented on the Keyboard Assembly and the Motherboard
Assemblies Board, consists of the following major sections:
· Keyboard Assembly
· Keyboard Scanner
· Status LED Interface
4.2.6 Hard Disk Drive Subsystem
The Hard Disk Drive Subsystem, implemented on the Motherboard Board and on the associated
hard disk drive module(s), provides disk storage for all system software and user files.
The notebook is equipped with an  1.6 GB or larger...

4-4Theory of Operation 4.2.8.1 AC Power Adapter
The computer is equipped with a universal AC power adapter that converts AC voltage  into DC
voltage (approx. 46 Watts of power) used to operate the notebook and charge the batteries.  The
specifications for the AC adapter include:
· Input Voltage:  100 to 250 VAC
· Input Current:  Approximately 1.5 Amps
· Input Frequency: 50 to 60 Hz
4.3. Detailed Circuit Theory
The remainder of this chapter provides chip-level circuit description for the Extensa Series...

Service Guide4-5 4.3.2 System Architecture
Figure 4-1 shows the Extensa system architecture. The remainder of this chapter provides a
detailed description of the major chips used in the Extensa Notebooks.586
CPUSRAMM1521
BGADRAMHDDM1523UMA
Graphic
controllerIDE Master
Aladdin III System Block DiagramCDCPU BusPCI BusISA BusUSB connector
Figure 4-1Extensa 670 System Architecture Diagram 

4-6Theory of Operation 4.3.3 ALI M1521 (PCI, Cache and Memory Controller)
The ALADDIN-III consists of tow chips, ALI M1521 and M1523 to give a 586 class system the
complete solution with the most up-to-date feature and architecture for the new multimedia/
multithreading operating system.  It utilizes the BGA package to improve the AC characterization,
resolves system bottleneck and make the system manufacturing easier.  The ALADDIN-III gives a
highly-integrated system solution and a most up-to-date...

Service Guide4-7Figure 4-2M1521 Pin Assignments 

4-8Theory of Operation 4.3.4 ALI M1523 (PCI, Cache and Memory Controller)
The M1523 is a bridge between PCI and ISA bus, providing full PCI and ISA compatible functions.
The M1523 has Integrated System Peripherals (ISP) on-chip and provides advanced features in the
DMA controller.  This chip contains the keyboard controller, real-time clock and IDE master
controller.  This chip also supports the Advanced Programmable Interrupt controller (APIC)
interface.
One eight-byte bidirectional line buffer is...

Service Guide4-9                                                       VDD
IRQ12
MSCLK
KBDATA
KBCLK/KBCSJ
KBINH/IRQ1
IDESCS3J
IDESCS1J
IDEPCS3J
IDEPCS1J
IDE_A0
IDE_A2
IDE_A1
IDAKJ1
IDAKJ0
IDERDY
IDEIORJ
IDEIOWJ
IDRQ1
IDRQ0
IDE_D0
IDE_D15
Vss
IDE_D1
IDE_D14
IDE_D2
IDE_D13
IDE_D3
IDE_D12
IDE_D4
IDE_D11
IDE_D5
IDE_D10
IDE_D6
IDE_D9
IDE_D7
VDD
IDE_D8
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
CBEJ0
AD8
AD9
AD10
AD11
VDD Vss
BALE
SA2
SA1
SA0
SBHEJ
M16J
LA23
IO16J
LA22
IRQ10
LA21
IRQ11
VDD/BAT
RTC32KII
RTC32KI
PWG
LA20...

4-10Theory of Operation 4.3.5 ALI M6377 (Powre Management Unit)
· Three operation states
· ON state
· DOZE state
· SLEEP state
· Programmable DOZE and SLEEP timers
· Programmable EL timer for backlight control
· Three output pins depending on operation state, each pin is programmable and power
configurable
· Provide system activity monitoring, including:
· video
· hard disk
· floppy disk
· serial port
· keyboard
· parallel port
· two programmable I/O groups activity monitor, each group contains 16/8 I/O...

Service Guide4-11ACTIVITY
MONITOREL TIMERPROGRAMABLE
APM TIMER
x 2BATTERY
MONITORGPIOSMI
HANDLERSTATE
CONTROLLERWAKEUP
EVENT
HANDLERBUS
INTERF
ACETimebaseOTHERFigure 4-5M6377 Chip Simplified Block Diagram