Acer Extensa 670 Service Guide
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4-2Theory of Operation 4.2.2 Memory Subsystem The memory subsystem comprises the following components: · Main memory · L2 Secondary Memory (cache) · Flash ROM The Extensa Series uses fast Extended Data Out (EDO) DRAM for main and video memory and high-speed synchronous, pipelined burst SRAM for L2 cache memory. Main BIOS and Video BIOS are stored in Flash ROM. 4.2.2.1 Main Memory The 67x Series Notebooks come standard with 16 MB main memory, expandable to 80 MB. Memory expansion accommodations are provided via standard soDIMM connectors on the bottom of the Motherboard Assembly. 4.2.2.2 Flash ROM All versions of the Extensa notebook family use a Flash ROM that contains both the main system BIOS and the VGA BIOS. The Flash ROM execution is 8 bits wide. However, better performance can be attained by enabling the Shadow ROM in the CMOS setup routine. When the Shadow ROM is enabled, BIOS is copied into 32-bit high speed memory system. 4.2.3 Video Subsystem The video subsystem is implemented on the Motherboard Assemblies. The notebook contains a built-in 12.1 inch LCD and features simultaneous LCD and external VGA display. The video subsystem includes a 2 MB DRAM memory, 32-bit DRAM bus, and separate display and memory clocks. An additional frame buffer/accelerator DRAM increases the available memory band width for CPU accesses. The video section also uses additional levels of write FIFOs, a read cache, page mode DRAM. 4.2.4 Sound Subsystem The Extensa Series Notebook is equipped with a sound chip set that is Sound BlasterTM and Sound Blaster Pro compatible. Internal stereo speakers provide the Notebook with sound generation capabilities. A set of 3.5 mm connectors allow for external microphone and line inputs and headphone/speaker outputs. The sound subsystem also includes a variety of sound utilities that combine to provide additional multi-media functions:
Service Guide4-3 4.2.5 Keyboard Subsystem The keyboard subsystem, implemented on the Keyboard Assembly and the Motherboard Assemblies Board, consists of the following major sections: · Keyboard Assembly · Keyboard Scanner · Status LED Interface 4.2.6 Hard Disk Drive Subsystem The Hard Disk Drive Subsystem, implemented on the Motherboard Board and on the associated hard disk drive module(s), provides disk storage for all system software and user files. The notebook is equipped with an 1.6 GB or larger hard disk drive. The hard disk drive also features built-in power conservation features configured from the standard CMOS Setup Routine. An Automatic Power Down mode can be selected which powers down the drive motor during periods of inactivity. An additional level of power conservation may also be selected which powers down the motor plus all control circuits. The hard disk drives are factory formatted as a single drive (Drive C:) and are preloaded with installation versions of Windows 95, Windows NT or Windows for Workgroups. 4.2.6.1 Hard Disk Drive Power Management Both the internal hard disk drive and the hard disk drive installed in the media bay implement power savings features. From the CMOS setup routine, an automatic power down mode can be selected which enables the drive to turn off its motor after a specified period of inactivity. Additional Sleep modes can direct additional power savings during inactive periods by powering down the control circuitry. 4.2.7 Floppy Disk Drive Subsystem The Extensa 67x Series notebooks contain provisions for supporting a Floppy Disk Drive installed internally or externally connected to the parallel port. The Floppy Disk Drive Subsystem consists of a Floppy Controller and the Floppy Disk Drive located either in the media bay or external to the notebook (not both). The 3.5-inch floppy disk drive can read/write standard 3.5-inch disks (either1.44 MB or 2 MB capacity). The drive can also read a 720 KB disk (for interchange of data with other computers). The data transfer rate for the floppy disk drive is 500 Kbits per second for high-density disks and 250 Kbits per second for double-density disks. 4.2.8 Power Subsystem The notebook is equipped with a software/hardware monitored/controlled Power Subsystem that minimizes battery usage for prolonged battery operation and automatically recharges the batteries when the notebook is used with an AC adapter.
4-4Theory of Operation 4.2.8.1 AC Power Adapter The computer is equipped with a universal AC power adapter that converts AC voltage into DC voltage (approx. 46 Watts of power) used to operate the notebook and charge the batteries. The specifications for the AC adapter include: · Input Voltage: 100 to 250 VAC · Input Current: Approximately 1.5 Amps · Input Frequency: 50 to 60 Hz 4.3. Detailed Circuit Theory The remainder of this chapter provides chip-level circuit description for the Extensa Series Notebooks. 4.3.1 Major Components Table 4-1 shows a listing the of the major components used in the Extensa Series Notebooks. Table 4-1Major Chips List ComponentVendorDescriptionM1521AcerPCI, cache and memory controller (Host-PCI Bridge)M1523AcerSystem controller chip (PCI-ISA Bridge)M6377AcerPower management controller65550C&T (Chips & Technology)Video controllerTI1130Texas InstrumentsPCMCIA controllerNS87336VJGNS (National Semiconductor)Super I/O controllerES1878ESS TechnologyAudio controllerT62.045.C.00AmbitCharger boardDAC-07B008DeltaLCD inverterDC-R05DeltaLCD ID boardM38802PhoenixKeyboard encoder and decoder
Service Guide4-5 4.3.2 System Architecture Figure 4-1 shows the Extensa system architecture. The remainder of this chapter provides a detailed description of the major chips used in the Extensa Notebooks.586 CPUSRAMM1521 BGADRAMHDDM1523UMA Graphic controllerIDE Master Aladdin III System Block DiagramCDCPU BusPCI BusISA BusUSB connector Figure 4-1Extensa 670 System Architecture Diagram
4-6Theory of Operation 4.3.3 ALI M1521 (PCI, Cache and Memory Controller) The ALADDIN-III consists of tow chips, ALI M1521 and M1523 to give a 586 class system the complete solution with the most up-to-date feature and architecture for the new multimedia/ multithreading operating system. It utilizes the BGA package to improve the AC characterization, resolves system bottleneck and make the system manufacturing easier. The ALADDIN-III gives a highly-integrated system solution and a most up-to-date system architecture including the UMA, ECC, PBSRAM, SDRAM/BEDO and multi-bus with highly efficient, deep FIFO between the buses, such as the HOST/PCI/ISA dedicated IDE bus. The M1521 provides a complete integrated solution for the system controller and data path components in a Pentium-based system. It provides a 64-bit CPU bus interface, 32-bit PCI bus interface, 64/72 DRAM data bus with ECC or parity, secondary cache interface including pipeline burst SRAM or asynchronous SRAM, PCI master to DRAM interface, four PCI master arbiters and a UMA arbiter. The M1521 bus interfaces are designed to interface with 3V and 5V buses. The chip pinouts are provided in Figure 4-2.
4-8Theory of Operation 4.3.4 ALI M1523 (PCI, Cache and Memory Controller) The M1523 is a bridge between PCI and ISA bus, providing full PCI and ISA compatible functions. The M1523 has Integrated System Peripherals (ISP) on-chip and provides advanced features in the DMA controller. This chip contains the keyboard controller, real-time clock and IDE master controller. This chip also supports the Advanced Programmable Interrupt controller (APIC) interface. One eight-byte bidirectional line buffer is provided for ISA/DMA master memory read/writes. One 32-bit wide posted-write buffer is provided for PCI memory write cycles to the ISA bus. It also supports a PCI to ISA IRQ routing table and level-to-edge trigger transfer. The chip has two extra IRQ lines and one programmable chip select for motherboard Plug and Play functions. The interrupt lines can be routed to any of the available ISA interrupts. The on-chip IDE controller supports two IDE connectors for up to four IDE devices providing an interface for IDE hard disk and CD-ROMs. The ATA bus pins are dedicated to improve the performance of IDE master. The M1523 supports the Super Green feature for Intel and Intel compatible CPUs. It implements programmable hardware events, software event and external switches (for suspend/turbo/ring-in). The M1523 provides CPU clock control (STPCLKJ). The STPCLKJ can be active (low) or inactive (high) in turn by throttling control. A simplified block diagram of the M1523 chip is shown in Figure 4-3 and the associated pinouts are provided in Figure 4-4. M1523 Block DiagramDATA Buffer ControlAddress BufferDecoderClock & ResetPCI BUS Interface UNITPCI Arbiter InterfaceISA Interrupt UNITPCI Interrupt UNITCPU InterfaceUSB Interface (reserved)PCI IDE Master InterfaceISA BUS Interface UNITDMA Refresh UNITPMU or APIC InterfacePS2/AT Keyboard ControllerTimer UNITMISC. LogicREAL Time ClockPWG CPURST RSTDRV OSC14MPCICLK CBEJ[3:0] AD[31:0] FRAMEJ TRDYJ IRDYJ STOPJ DEVSELJ SERRJ PARPHOLDJ PHLDAJFERRJ IRQ[15:14] IRQ[11:3] INTAJ/M1II NTBJ/S0 INTCJ/S1 INTDJ/S2IGNNEJ INTR NMI A20MJ USBCLK USBP[11:10] IDRQ[0:1] IDAKJ[0:1] IDERDY IDEIORJ IDEIOWJ IDESCS3J IDESCS1J IDEPCS3J IDEPCS1J IDE_A[2:0] IDE_D[15:0]SD[15:8] XD[7:0] SA[19:0] SBHEJ LA[23:17] IO16J M16J MEMRJ MEMWJ AEN IOCHRDYJ NOWSJ IOCHKJ SYSCLK BALE IORJ IOWJ SMEMRJ/LMEGJ SMEMWJ/RTCAS EXTSW STPCLKJSPKRSIRQI XDIR SPLED ROMCSJSIRQII RTC32KI RTC32KIIKBINH/IRQ1 KBCLK/KBCSJ KBDATA MSCLK IRQ12/MDATA DREQ[7:5] DREQ[3:0] DACKJ[7:5] DACK2J/3J TC REFSHJFigure 4-3M1523 Chip Simplified Block Diagram
Service Guide4-9 VDD IRQ12 MSCLK KBDATA KBCLK/KBCSJ KBINH/IRQ1 IDESCS3J IDESCS1J IDEPCS3J IDEPCS1J IDE_A0 IDE_A2 IDE_A1 IDAKJ1 IDAKJ0 IDERDY IDEIORJ IDEIOWJ IDRQ1 IDRQ0 IDE_D0 IDE_D15 Vss IDE_D1 IDE_D14 IDE_D2 IDE_D13 IDE_D3 IDE_D12 IDE_D4 IDE_D11 IDE_D5 IDE_D10 IDE_D6 IDE_D9 IDE_D7 VDD IDE_D8 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 CBEJ0 AD8 AD9 AD10 AD11 VDD Vss BALE SA2 SA1 SA0 SBHEJ M16J LA23 IO16J LA22 IRQ10 LA21 IRQ11 VDD/BAT RTC32KII RTC32KI PWG LA20 LA19 IRQ15 LA18 IRQ14 LA17 MEMRJ DREQ0 Vss MEMWJ DACK5J SD8 DREQ5 SD9 DACK6J SD10 DREQ6 SD11 DACK7J SD12 DREQ7 SD13 VDD SD14 SD15 OSC14M SIRQI SIRQII USBCLK DACK0J DACK1J CPURST SMIJ STPCLKJ Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 ALi M1523Figure 4-4M1523 Chip Pinouts
4-10Theory of Operation 4.3.5 ALI M6377 (Powre Management Unit) · Three operation states · ON state · DOZE state · SLEEP state · Programmable DOZE and SLEEP timers · Programmable EL timer for backlight control · Three output pins depending on operation state, each pin is programmable and power configurable · Provide system activity monitoring, including: · video · hard disk · floppy disk · serial port · keyboard · parallel port · two programmable I/O groups activity monitor, each group contains 16/8 I/O addresses · one predefined I/O group activity monitor · Multiple external wake up events from DOZE and SLEEP states: · External push button · RTC alarm · Two levels battery warning monitor · AC power monitoring to disable PMU function A simplified block diagram of the M6377 Power Management Unit is provided in Figure 4-5. The chip pinouts are provided in Figure 4-6.
Service Guide4-11ACTIVITY MONITOREL TIMERPROGRAMABLE APM TIMER x 2BATTERY MONITORGPIOSMI HANDLERSTATE CONTROLLERWAKEUP EVENT HANDLERBUS INTERF ACETimebaseOTHERFigure 4-5M6377 Chip Simplified Block Diagram