Acer Aspire S3 Ms2346 Service Guide
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Troubleshooting4-21 2FhEnable cache before system BIOS shadow 30h 1-4-1-1 RAM failure on data bits xxxx of high byte of memory bus 32h Test CPU bus-clock frequency 33h Initialize Phoenix Dispatch Manager 36h Warm start shut down 38h Shadow system BIOS ROM 3Ah Autosize cache 3Ch Advanced configuration of chipset registers 3Dh Load alternate registers with CMOS values 42h Initialize interrupt vectors 45h POST device initialization 46h 2-1-2-3 Check ROM copyright notice 48h Check video configuration against CMOS 49h Initialize PCI bus and devices 4Ah Initialize all video adapters in system 4Bh QuietBoot start (optional) 4Ch Shadow video BIOS ROM 4Eh Display BIOS copyright notice 50h Display CPU type and speed 51h Initialize EISA board 52h Test keyboard 54h Set key click if enabled 58h 2-2-3-1 Test for unexpected interrupts 59h Initialize POST display service 5Ah Display prompt “Press F2 to enter SETUP” 5Bh Disable CPU cache 5Ch Test RAM between 512 and 640 KB 60h Test extended memory 62h Test extended memory address lines 64h Jump to User Patch1 66h Configure advanced cache registers 67h Initialize Multi Processor APIC 68h Enable external and CPU caches Table 4-3. BIOS Beep Codes Code BeepsPOST Routine Description
4-22Troubleshooting 69hSetup System Management Mode (SMM) area 6Ah Display external L2 cache size 6Bh Load custom defaults (optional) 6Ch Display shadow-area message 6Eh Display possible high address for UMB recovery 70h Display error messages 72h Check for configuration errors 76h Check for keyboard errors 7Ch Set up hardware interrupt vectors 7Eh Initialize coprocessor if present 80h Disable onboard Super I/O ports and IRQs 81h Late POST device initialization 82h Detect and install external RS232 ports 83h Configure non-MCD IDE controllers 84h Detect and install external parallel ports 85h Initialize PC-compatible PnP ISA devices 86h Re-initialize onboard I/O ports 87h Configure Motherboard Configurable Devices (optional) 88h Initialize BIOS Area 89h Enable Non-Maskable Interrupts (NMIs) 8Ah Initialize Extended BIOS Data Area 8Bh Test and initialize PS/2 mouse 8Ch Initialize floppy controller 8Fh Determine number of ATA drives (optional) 90h Initialize hard-disk controllers 91h Initialize local-bus hard-disk controllers 92h Jump to UserPatch2 93h Build MPTABLE for multi-processor boards 95h Install CD ROM for boot 96h Clear huge ES segment register 97h Fixup Multi Processor table 98h 1-2 Search for option ROMs. One long, two short beeps on checksum failure. Table 4-3. BIOS Beep Codes Code BeepsPOST Routine Description
Troubleshooting4-23 99hCheck for SMART drive (optional) 9Ah Shadow option ROMs 9Ch Set up Power Management 9Dh Initialize security engine (optional) 9Eh Enable hardware interrupts 9Fh Determine number of ATA and SCSI drives A0h Set time of day A2h Check key lock A4h Initialize Typematic rate A8h Erase F2 prompt AAh Scan for F2 key stroke ACh Enter SETUP AEh Clear Boot flag B0h Check for errors B2h POST done- prepare to boot operating system B4h 1 One short beep before boot B5h Terminate QuietBoot (optional) B6h Check password (optional) B9h Prepare Boot BAh Initialize DMI parameters BBh Initialize PnP Option ROMs BCh Clear parity checkers BDh Display MultiBoot menu BEh Clear screen (optional) BFh Check virus and backup reminders C0h Try to boot with INT 19 C1h Initialize POST Error Manager (PEM) C2h Initialize error logging C3h Initialize error display function C4h Initialize system error handler C5h PnPnd dual CMOS (optional) C6h Initialize notebook docking (optional) C7h Initialize notebook docking late Table 4-3. BIOS Beep Codes Code BeepsPOST Routine Description
4-24Troubleshooting C8hForce check (optional) C9h Extended checksum (optional) D2h Unknown interrupt E0h Initialize the chipset E1h Initialize the bridge E2h Initialize the CPU E3h Initialize the system timer E4h Initialize system I/O E5h Check force recovery boot E6h Checksum BIOS ROM E7h Go to BIOS E8h Set Huge Segment E9h Initialize Multi Processor EAh Initialize OEM special code EBh Initialize PIC and DMA ECh Initialize Memory type EDh Initialize Memory size EEh Shadow Boot Block EFh System memory test F0h Initialize interrupt vectors F1h Initialize Run Time Clock F2h Initialize video F3h Initialize System Management Mode F4h 1 Output one beep before boot F5h Boot to Mini DOS F6h Clear Huge Segment F7h Boot to Full DOS Table 4-3. BIOS Beep Codes Code BeepsPOST Routine Description
Troubleshooting4-25 POST Codes0 There are two types of POST codes: Progress Codes and Error Codes. Progress Codes are designed to show the execution point while b ooting or executing services. Error Codes are designed to halt on exceptional (fatal) error conditions. Component Codes0 The Component Code is an unsigned integer value that is assigned by the build process. The following tables describe the various ranges of component codes: The Component Code is assigned to an individual component (or driver) using the POSTCODE= option in the DSC file. If the valu e that follows POSTCODE= is a hexadecimal or decimal number, in th e range 0x00-0xdf, then that code will be used with all POST Codes associated with that driver. Table 4-4. Component Codes Range Description 0x00-0x1f OEM Components. These values are reserved for OEM components 0x20-0x9f These values are reserved for SecureCore Tiano™ core components. POSTCODE_CC_VARIABL E_SERVICES (0x20) POSTCODE_CC_KEYBOARD_ CONTROLLER (0x21) POSTCODE_CC_BOOT _MODE (0x22) POSTCODE_CC_S3_S UPPORT (0x23) POSTCODE_CC_TCG (0x24) POSTCODE_CC_HDD_PASSWORD (0x25) POSTCODE_CC_CPU_IO (0x26) POSTCODE_CC_BOOT_SCRIPT (0x27) POSTCODE_CC_STATUS_CODE (0x28) POSTCODE_CC_DATA_HUB (0x29) POSTCODE_CC_HII_DATABASE (0x2a) POSTCODE_CC_RESET (0x2b) POSTCODE_CC_METRONOME (0x2c) POSTCODE_CC_INTERRUPT_CONTROLLER (0x2d) POSTCODE_CC_DIAGNOSTIC_SUMMARY (0x2e) POSTCODE_CC_SMBIOS (0x2f) POSTCODE_CC_SMM_COMMUNICATION (0x30) POSTCODE_CC_SMM_RUNTIME (0x31) POSTCODE_CC_SMM_ SERVICES (0x32) POSTCODE_CC_FIRMWARE_DEVICE (0x33) POSTCODE_CC_CAPSULE_SERVICES (0x34) POSTCODE_CC_MONOTONIC_COUNTER (0x35) POSTCODE_CC_SMBIOS _EVENT_LOG (0x36) POSTCODE_CC_RTC (0x37) POSTCODE_CC_BOOT_MANAGER (0x38) POSTCODE_CC_VGA (0x39)
4-26Troubleshooting POSTCODE_CC_HII_FORMS_BROWSER (0x3a) POSTCODE_CC_BOOT_MENU (0x3b) POSTCODE_CC_USER_MANAGER (0x3c) POSTCODE_CC_TIMER (0x3d) POSTCODE_CC_PCI_BUS (0x3e) POSTCODE_CC_ISA_BUS (0x3f) POSTCODE_CC_IDE_BUS (0x40) POSTCODE_CC_AHCI_BUS (0x41) POSTCODE_CC_SCSI_BUS (0x42) POSTCODE_CC_U SB_BUS (0x43) POSTCODE_CC_FLOPPY (0x44) POSTCODE_CC_SERIAL_PORT (0x45) POSTCODE_CC_PS2_MOUSE (0x46) POSTCODE_CC_PS2_KEYBOARD (0x47) POSTCODE_CC_EHCI (0x48) POSTCODE_CC_XHCI (0x49) POSTCODE_CC_UHCI (0x4a) POSTCODE_CC_OHCI (0x4b) POSTCODE_CC_USB_KEYBOARD (0x4c) POSTCODE_CC_USB_MOUSE (0x4d) POSTCODE_CC_USB_MASS _STORAGE (0x4e) POSTCODE_CC_CONSOLE_SPLITTER (0x4f) POSTCODE_CC_GRAPHICS_CONSOLE (0x50) POSTCODE_CC_SERIAL_CONSOLE (0x51) POSTCODE_CC_TEXT_CONSOLE (0x52) POSTCODE_CC_DISK_IO (0x53) POSTCODE_CC_PARTITION (0x54) POSTCODE_CC_SETUP (0x55) POSTCODE_CC_LEGACY_BIOS (0x56) POSTCODE_CC_BLOCK_ IO_THUNK (0x57) POSTCODE_CC_CRYPTO (0x58) Table 4-4. Component Codes Range Description
Troubleshooting4-27 0xa0-0xaf These values are reserved for SecureCore Tiano™ platform components. POSTCODE_CC_PLATFORM_STAGE0 (0xa0) - Early PEI Platform Initialization. POSTCODE_CC_PLATFORM_STAGE 1 (0xa1) -PEI Platform Initialization. POSTCODE_CC_PLATFORM_DXE (0xa1) - DXE Platform Initialization. POSTCODE_CC_PLATFORM_SMM (0xa1) - SMM Platform Initialization. POSTCODE_CC_PLATFORM_FLASH (0xa2) - Flash Platform Initialization. POSTCODE_CC_PLATFORM_CSM (0xa3) - CSM Platform Initialization. 0xa4-0xa7 - Reserved for future expansion. 0xa8-0xaf - Reserved for use by the individual platform. 0xb0-0xbf These values are reserved for future expansion. 0xc0-0xcf These values are reserved for core chipset drivers (north bridge, south bridge and CPU) and are assigned by chipset family. POSTCODE_CC_MEMORY_CONTR OLLER (0xc0) - Memory Controller. 0xd0-0xd7 These values are reserved fo r Small Silicon drivers (SIOs, flash, fingerprint, etc.) POSTCODE_CC_SUPER_IO (0xd0) - Super I/O POSTCODE_CC_FLASH_CONTROLLER (0xd1) - Flash Controller POSTCODE_CC_FLASH_DEVICE (0xd2) - Flash Device POSTCODE_CC_FINGERPRINT (0xd 3) - Fingerprint Sensor POSTCODE_CC_CLOCK_CONTROLLER (0xd4) - Clock Controller POSTCODE_CC_MGMT_CONTROLLER (0xd5) - Embedded controller or management controller. 0xd6-0xd7 - Reserved for future expansion. 0xd8-0xdf Reserved for platform usage. Table 4-4. Component Codes Range Description
4-28Troubleshooting 0xe0-0xff These are not components, but rather represent Architectural Progress Codes or Error Codes detailing milest ones in the system boot progress. The corresponding Progress Code value is always set to zero. POSTCODE_PC_SEC_ENTRY (0xe0) - Reset vector. POSTCODE_PC_SEC_EXIT (0xe1) - Leaving SEC/Going to PEI. POSTCODE_PC_PEI_ENTRY (0xe2) - Entering PEI Dispatch. POSTCODE_PC_PEI_EXIT (0xe3) - Exiting PEI Dispatch. POSTCODE_PC_IPL_DXE (0xe4) - En tering DXE IPLs normal boot path. POSTCODE_PC_IPL_S3 (0xe5) - Ente ring DXE IPLs S3 boot path. POSTCODE_PC_S3_OS (0xe6) - Exiting S3 boot path back to the OS. POSTCODE_PC_IPL_RECOVERY (0 xe7) - Entering DXE IPLs recovery boot path. POSTCODE_PC_IPL_EXIT (0xe8) POSTCODE_PC_DXE_ENTRY (0xe9) - Entering DXE Dispatch. POSTCODE_PC_DXE_EXIT (0xea) - Exiting DXE Dispatch. POSTCODE_EC_PEI_MEMORY (0xeb) - No permanent memory found at the end of PEI. POSTCODE_EC_PEI_IPL (0xec) - No DXE IPL found at the end of PEI. POSTCODE_EC_IPL_DXE (0xed) - No DXE found at end of DXE IPL. POSTCODE_EC_IPL_PPI (0xee) - Co uldnt find PPIs needed by DXE. POSTCODE_EC_DXE_ARCH (0xef) - Missing one or more architectural protocols at the end of DXE. Table 4-4. Component Codes Range Description
Troubleshooting4-29 Progress Codes0 This section describes the progress code values. Table 4-5. Progress Codes Range Description 0x00-0x1f Standard progress Codes. All other values are reserved. POSTCODE_PC_COMP_PEI_BEGIN (0x01) - The component was loaded and the PEI entry point called. POSTCODE_PC_COMP_PEI_END (0x02) - The component returned from the PEI entry point. POSTCODE_PC_COMP_DXE_BEGIN (0x03) - The component was loaded and the DXE/UEFI entry point called. POSTCODE_PC_COMP_DXE_END (0x04) - The component returned from the DE/UEFI entry point. POSTCODE_PC_COMP_SUPPORTED (0x05) - The Supported() member function of the components instance of the Driver Binding protocol was called. POSTCODE_PC_COMP_START (0x06) - The Start() member function of the components instance of the Driver Binding protocol was called. POSTCODE_PC_COMP_STOP (0x07) - The Stop() member function of the components instance of the Driver Binding protocol was called. POSTCODE_PC_COMP_SMM_INIT (0x08) - The component was loaded and the entry point called inside of SMM. POSTCODE_EC_DEVICE_ERROR (0x09) - The driver encountered a condition where it cannot proceed due to a hardware failure. POSTCODE_EC_RESOURCE_ERROR (0x0a) - The driver encountered a condition where it cannot proceed due to being unable to acquire resources. POSTCODE_EC_DATA_CORRUPT (0x0b) - The driver encountered a condition where it found invalid data and could not continue. 0x20-0x3f Component-Specific Progress Codes . These values are specific to the component type. 0x40-0x5f OEM Progress Codes. These progress codes are reserved for OEM usage. 0x60-0x7f Reserved. These are reserved for future expansion.