Acer Aspire 6530 Service Guide
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Chapter 4131 POST Codes Tables These tables describe the chipset and core POST codes, functions, phases, and components for the POST. The following table details the chipset POST codes and functions used in the POST. CodeBeepsPOST Routine Description 02h Verify Real Mode 03h Disable Non-Maskable Interrupt (NMI) 04h Get CPU type 06h Initialize system hardware 08h Initialize chipset with initial POST values 09h Set IN POST flag 0Ah Initialize CPU registers 0Bh Enable CPU cache 0Ch Initialize caches to...
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132Chapter 4 42h Initialize interrupt vectors 45h POST device initialization 46h 2-1-2-3 Check ROM copyright notice 48h Check video configuration against CMOS 49h Initialize PCI bus and devices 4Ah Initialize all video adapters in system 4Bh QuietBoot start (optional) 4Ch Shadow video BIOS ROM 4Eh Display BIOS copyright notice 50h Display CPU type and speed 51h Initialize EISA board 52h Test keyboard 54h Set key click if enabled 58h 2-2-3-1 Test for unexpected interrupts 59h Initialize POST display...
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Chapter 4133 89h Enable Non-Maskable Interrupts (NMIs) 8Ah Initialize Extended BIOS Data Area 8Bh Test and initialize PS/2 mouse 8Ch Initialize floppy controller 8Fh Determine number of ATA drives (optional) 90h Initialize hard-disk controllers 91h Initialize local-bus hard-disk controllers 92h Jump to UserPatch2 93h Build MPTABLE for multi-processor boards 95h Install CD ROM for boot 96h Clear huge ES segment register 97h Fixup Multi Processor table 98h 1-2 Search for option ROMs. One long, two short...
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134Chapter 4 * If the BIOS detects error 2C, 2E, or 30 (base 512K RAM error), it displays an additional word-bitmap (xxxx) indicating the address line or bits that failed. For example, 2C 0002 means address line 1 (bit one set) has failed. 2E 1020 means data bits 12 and 5 (bits 12 and 5 set) have failed in the lower 16 bits. Note that error 30 cannot occur on 386SX systems because they have a 16 rather than 32-bit bus. The BIOS also sends the bitmap to the port-80 LED display. It first displays the...
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Chapter 4135 Chipset POST Codes The following table details the Chipset POST codes and components used in the POST. POST CodeFunctionPhaseComponent 0xA0 MRC Entry PEI chipset/MRC 0x01 Enable MCHBAR PEI chipset/MRC 0x02 Check ME existence PEI chipset/MRC 0x03 Check for DRAM initialization interrupt and reset fail PEI chipset/MRC 0x04 Determine the system Memory type based on first populated socketPEI chipset/MRC 0x05 Verify all DIMMs are DDR2 and SO-DIMMS, which are unbufferedPEI chipset/MRC 0x06 Verify...
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136Chapter 4 0x39 Set Enhanced addressing mode for each channel PEI chipset/MRC 0x40 Perform steps required after JEDEC init PEI chipset/MRC 0x41 Program the receive enable reference timing control register PEI chipset/MRC 0x42 Post receive enable initialization PEI chipset/MRC 0x43 Enable sense amps. Reset read/write DQS pointers PEI chipset/MRC 0x44 Perform ME steps PEI chipset/MRC 0x45 Clear DRAM initialization bit in the ICH. PEI chipset/MRC 0x46 Program Thermal Management PEI chipset/MRC 0x47...
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Chapter 4137 Core POST Code Table The following table details the core POST codes and functions used in SecureCore. POST CodeFunctionPhaseComponent 0x00 Early Microcode update for CAR CEI / SEC Core 0x01 Enable CAR CEI / SEC Core 0x02 CAR Done, initial stack CEI / SEC Core 0xEE unknown CPU ID to load uCode CEI / SEC CPU 0xEF unknown DT CPU to load uCode CEI / SEC CPU 0xnn File count found in a volume PEI Core 0x11 Debug Test driver for debug test PPI 1 (If install debugTest driver)PEI Core 0x22 Debug...
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138Chapter 4 0x91 Initialize interrupt vectors Crisis Recovery Core 0x92 Initialize Run Time Clock Crisis Recovery Core 0x99 Initialize security Crisis Recovery Core 0x93 Initialize video Crisis Recovery Core 0x94 Output one beep Crisis Recovery Core 0x98 USB Initialization Crisis Recovery Core 0x95 Initialize the installed boot devices Crisis Recovery Core 0x96 Clear Huge segment Crisis Recovery Core 0x97 Boot Crisis Disk Crisis Recovery Core 0x20 DXE starts DXE Core 0x30 BIOSPSM DXE Core 0x02...
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Chapter 4139 0x22 TCG Physical Presence execution DXE TCG 0xB1 TCG DXE common pass through DXE TCG 0xE3 First Legacy BIOS Task table for legacy reset LBT Core 0x20 Verify that DRAM refresh is operating by polling the refresh bit in PORTB.LBT Core 0xDA Dummy PCIE Init entry, now handled by driver LBT Core 0x29 PMM (POST Memory Manager) init LBT Core 0xE5 WHEA init LBT Core 0x33 PDM (Post Dispatcher Manager) init LBT Core 0x01 IPMI init LBT Core 0xD8 ASF Init LBT Core 0x09 Set in-POST flag in CMOS that...
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140Chapter 4 0x6B If CMOS is bad, load Custom Defaults from flash into CMOS. If successful, reboot.LBT Core 0x3C If CMOS is valid, load chipset registers with values from CMOS, otherwise load defaults and display Setup prompt. If Auto Configuration is enabled, always load the chipset registers with the Setup defaults (Rel 6.0).LBT Core 0x3D Load alternate registers with CMOS values LBT Core 0x42 Initialize interrupt vectors 0 thru 77h LBT Core 0x46 Verify the ROM copyright notice LBT Core 0x45...