Yamaha Tyros 1 Service Manual
Have a look at the manual Yamaha Tyros 1 Service Manual online for free. It’s possible to download the document as PDF or print. UserManuals.tech offer 255 Yamaha manuals and user’s guides for free. Share the user manual or guide on Facebook, Twitter or Google+.
![Page 35
35 Tyros / TRS-MS01
PIN PIN
NO.NAMEI/O FUNCTION
NO.NAMEI/O FUNCTION
1 AB2 I Address bus input (A [12:1]) 65 MA2 O Maltiplex memory address bus
2 AB1 I Address bus input (A [12:1]) 66 MA4 O Maltiplex memory address bus
3 AB0 I SH-3 bus Interface 67 MA3 O Maltiplex memory address bus
4 CS# I Decode 68 V
SSVSS5 M/R# I/O Registor Setting 69 CLKI I Selectable Input clock
6 BS# I Bus Start Signal Input 70 TESTEN I Test enable interface
7 RD# I Read Signal Input 71 CLKI2 I Selectable Input clock
8 WE0# I Wright...](http://img.usermanuals.tech/thumb/83/104040/w64_tyros-1-service-manual-1517409781_d-34.png "Page 35
35 Tyros / TRS-MS01
PIN PIN
NO.NAMEI/O FUNCTION
NO.NAMEI/O FUNCTION
1 AB2 I Address bus input (A [12:1]) 65 MA2 O Maltiplex memory address bus
2 AB1 I Address bus input (A [12:1]) 66 MA4 O Maltiplex memory address bus
3 AB0 I SH-3 bus Interface 67 MA3 O Maltiplex memory address bus
4 CS# I Decode 68 V
SSVSS5 M/R# I/O Registor Setting 69 CLKI I Selectable Input clock
6 BS# I Bus Start Signal Input 70 TESTEN I Test enable interface
7 RD# I Read Signal Input 71 CLKI2 I Selectable Input clock
8 WE0# I Wright...")
31 Tyros / TRS-MS01 PIN NO.I/O FUNCTION NAMEPIN NO.I/O FUNCTION NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 OUTER NO. E5 D4 C3 B2 A1 D5 E6 C4 B3 A2 A3 D6 E7 C5 B4 A4 D7 C6 E8 D8 B5 A5 C7 B6 E9 D9 C8 A6 B7 A7 E10 D10 C9 B8 A8 B9 E11 D11 C10 A9 B10 A10 E12 D12 C11 B11 A11 C12 B12 E13 D13 C13 A12 B13 A13 A14 E14 D14 C14 B14 B15 C15 D15 E15 A15 A16 B16 C16 D16 E16 A17 B17 A18 C17 D17 E17 B18 A19 C18 B19 D18 E18 C19 A20 B20 C20 D19 E19 A21 B21 A22 D20 C21 E20 D21 B22 A23 C22 B23 E21 D22 C23 A24 B24 A25VSS2 VDDC CD15 CD13 CD14 CD6 CD2 CD9 CD11 CD12 CD10 CD1 VSS CD5 CD8 CD7 VSS2 CD0 VSS VDDS CD4 CD3 CA2 CA0 CA8 CA9 CA5 CA1 CA3 CA4 VSS2 VDDC CA10 CA6 CA7 CA11 CA14 CA15 CA13 CA12 CSN0 CSN1 VSS VDDS WRN RDN WAIT0 IRQ0 DREQ0 TCK TRST VSS XO XI VDDS SLAVE TMS TDO ICN RFCLK0 PLL_ TSTN PLL_ BP VDDS VSS RFCLK1 VDDC TMODE PLL_ AVD NC NC PLL_ AVS TEST1 VSS SY1 VDDC VSS2 KONTRG0 KONTRG1 CK512 CK128 BCLK SY0 HMA20 HMA21 HMA19 HMA18 VDDS VSS HMA9 HMA7 HMA6 HMA8 HMA10 HMA17 VDDS HMA11 HMA4 HMA5 HMA13 VSS HMA12 HMA3 HMA14 HMA2 HMA1- - I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O - I/O I/O I/O - I/O - - I/O I/O I I I I I I I I - - I I I I I I I I I I - - I I O O O I I - O I - I I O I O I I - - I - I - - - - I - I - - O I O O O O O O O O - - O O O O O O - O O O O - O O O O OGround Power supply +1.5 V Data bus of internal register Ground Data bus of unternal register Ground Data bus of unternal register Ground Power supply +3 V Data bus of internal register Address bus of internal regisuter Ground Power supply +1.5 V Address bus of internal regisuter Chip select Ground Power supply +3 V Write strobe Read strobe Hardware wait request Interrupt request Test pin Ground Crystal osc. output Crystal osc. input Power supply +3 V Master/Slave select Test pin Initial clear PLL Clock Power supply Power supply +3 V Ground PLL Clock Power supply +1.5 V Test pin Power supply (PLL) Not used Not used Power supply (PLL) Test pin Ground Sync. clock Power supply +1.5 V Ground Key on data Master clock (256 Fs) Master clock (64 Fs) Sync. clock Wave memory address bus Power supply +1.5 V Ground Wave memory address bus Power supply +1.5 V Wave memory address bus Ground Wave memory address bus106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 OUTER NO. E22 D23 C24 B25 A26 E23 F22 D24 C25 B26 C26 F23 G22 E24 D25 D26 G23 F24 H22 H23 E25 E26 G24 F25 J22 J23 H24 F26 G25 G26 K22 K23 J24 H25 H26 J25 L22 L23 K24 J26 K25 K26 M22 M23 L24 L25 L26 M24 M25 N22 N23 N24 M26 N25 N26 P26 P22 P23 P24 P25 R25 R24 R23 R22 R26 T26 T25 T24 T23 T22 U26 U25 V26 U24 U23 U22 V25 W26 V24 W25 V23 V22 W24 Y26 Y25 Y24 W23 W22 AA26 AA25 AB26 Y23AA24Y22AA23 AB25 AC26 AB24 AC25 AA22 AB23 AC24 AD26 AD25 AE26 VSS2 VDDC HMA15 HMA16 HMA22 HMA25 VDDS HMA27 HMA0 HMA23 HMA24 VDDS HMA26 HMA30 HMA28 HMA29 LMA17 LMA19 VSS VDDS LMA20 LMA21 LMA9 LMA18 LMA12 LMA4 LMA6 LMA8 LMA7 LMA10 VSS2 VDDC LMA13 LMA11 LMA5 LMA3 LMA16 LMA0 LMA2 LMA14 LMA15 LMA1 VSS VDDS LMA22 LMA23 LMA24 LMA27 LMA28 LMA25 LMA26 LMA30 LMA29 MOEN MWEN LMD15 VSS VDDS LMD13 LMD14 LMD11 LMD10 VDDS VSS LMD12 LMD9 LMD8 LMD7 VSS2 VSS LMD6 LMD5 LMD3 LMD4 VDDC VSS2 LMD2 LMD0 LMD1 DCSL0 VDDS VDDC DCSL1 DQML3 DQML1 DMAL14 VDDS VSS DMAL13 DMAL12 DMAL9 VSS DMAL11 VSS DMAL10 DMAL8 DMAL6 DMAL7 DMAL5 VSS2 VSS DMAL4 DMAL3 DMAL2 DMAL0- - O O O O - O O O O - O O O O O O - - O O O O O O O O O O - - O O O O O O O O O O - - O O O O O O O O O O O I/O - - I/O I/O I/O I/O - - I/O I/O I/O I/O - - I/O I/O I/O I/O - - I/O I/O I/O O - - O O O O - - O O O - O - O O O O O - - O O O OGround Power supply +1.5 V Wave memory address bus Power supply +3 V Wave memory address bus Power supply +3 V Wave memory address bus Wave memory address bus (Lower data memory) Ground Power supply +3 V Wave memory address bus (Lower data memory) Ground Power supply +1.5 V Wave memory address bus (Lower data memory) Ground Power supply +3 V Wave memory address bus (Lower data memory) Wave memory output enable Wave memory write enable Wave memory data bus (Lower 16 bit) Ground Power supply +3 V Wave memory data bus (Lower 16 bit) Power supply +3 V Ground Wave memory data bus (Lower 16 bit) Ground Ground Wave memory data bus (Lower 16 bit) Power supply +3 V Ground Wave memory data bus (Lower 16 bit) Power supply +3 V Power supply +1.5 V MASK signal Address bus (DIMM, SDRAM) Power supply +3 V Ground Address bus (DIMM, SDRAM) Ground Address bus (DIMM, SDRAM) Ground Address bus (DIMM, SDRAM) Ground Ground Address bus (DIMM, SDRAM) T8F02TB-0102 (X0060A00) SWP50 (Tone Generator)DM: IC39,IC40
32Tyros / TRS-MS01 PIN NO.I/O FUNCTION NAMEPIN NO.I/O FUNCTION NAME 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 303 314 315VSS2 VDDC DMAL1 DCSL2 DRAS0 DCAS0 VDDS DCLKIN DQML2 DCSL3 DQML0 VDDS VSS DWEN0 DCLK0 DCLK1 DCLKE HMD13 VSS VDDS HMD15 HMD14 HMD10 HMD12 VDDC VDDS HMD7 HMD11 HMD9 HMD8 VSS2 VDDC HMD4 HMD6 HMD5 HMD3 VSS VSS2 HMD1 HMD2 HMD0 DCSH0 VSS VDDS DCSH1 DQMH3 DQMH1 DMAH14 DMAH13 VSS VSS2 DMAH11 DMAH12 DMAH10 DMAH9 DMAH8 VDDS VDDS DMAH6 DMAH7 DMAH4 DMAH3 VDDS VSS DMAH5 DMAH2 DMAH1 DMAH0 VSS VSS DRAS1 DCSH2 DQMH2 DCSH3 VDDC VSS2 DQMH0 DWEN1 DCAS1 DCLK2 VDDS VDDC DCLK3 MELO0 MELO1 MELO2 VDDS VSS MELO3 MELO4 MELO5 MELO6 MELO7 WCLK0 WCLK1 EIRQ EICN ESDA ESCL MELI0 MELI1 MELI2 MELI3 MELI4 MELI5- - O O O O - I O O O - - O O O O I/O - - I/O I/O I/O I/O - - I/O I/O I/O I/O - - I/O I/O I/O I/O - - I/O I/O I/O O - - O O O O O - - O O O O O - - O O O O - - O O O O - - O O O O - - O O O O - - O O O O - - O O O O O O O O O I/O I/O I I I I I IGround Power supply +1.5 V Address bus (DIMM, SDRAM) Power supply +3 V MASK signal MASK signal Power supply +3 V Ground Wave memory data bus (Upper data memory) Ground Power supply +3 V Wave memory data bus (Upper data memory) Power supply +1.5 V Power supply +3 V Wave memory data bus (Upper data memory) Ground Power supply +1.5 V Wave memory data bus (Upper data memory) Ground Ground Wave memory data bus (Upper data memory) Ground Power supply +3 V MASK signal Address bus (DIMM, SDRAM) Ground Ground Address bus (DIMM, SDRAM) Power supply +3 V Power supply +3 V Address bus (DIMM, SDRAM) Power supply +1.5 V Ground Address bus (DIMM, SDRAM) Ground Ground MASK signal Power supply +1.5 V Ground MASK signal Power supply +3 V Power supply +1.5 V MEL wave data output Ground MEL wave data output For DAC LR clock MEL wave data input316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 OUTER NO.OUTER NO. AB22 AC23 AD24 AE25 AF26 AC22 AB21 AD23 AE24 AF25 AF24 AC21 AB20 AD22 AE23 AF23 AC20 AD21 AB19 AC19 AE22 AF22 AD20 AE21 AB18 AC18 AD19 AF21 AE20 AF20 AB17 AC17 AD18 AE19 AF19 AE18 AB16 AC16 AD17 AF18 AE17 AF17 AB15 AC15 AD16 AE16 AF16 AD15 AE15 AB14 AC14 AD14 AF15 AE14 AF14 AF13 AB13 AC13 AD13 AE13 AE12 AD12 AC12 AB12 AF12 AF11 AE11 AD11 AC11 AB11 AF10 AE10 AF9AD10 AC10 AB10 AE9 AF8 AD9 AE8 AC9 AB9 AD8 AF7 AE7 AD7 AC8 AB8 AF6 AE6 AF5 AC7 AD6 AB7 AC6 AE5 AF4 AD5 AE4 AB6 AC5 AD4 AF3 AE3 AF2AB5 AC4 AD3 AE2 AF1 AB4 AA5 AC3 AD2 AE1 AD1 AA4 Y5 AB3 AC2 AC1 Y4 AA3 W5 W4 AB2 AB1 Y3 AA2 V5 V4 W3 AA1 Y2 Y1 U5 U4 V3 W2 W1 V2 T5 T4 U3 V1 U2 U1 R5 R4 T3 T2 T1 R3 R2 P5 P4 P3 R1 P2 P1 N1 N5 N4 N3 N2 M2 M3 M4 M5 M1 L1 L2 L3 L4 L5 K1 K2 J1 K3 K4 K5 J2 H1 J3 H2 J4 J5 H3 G1 G2 G3 H4 H5 F1 F2 E1 G4 F3 G5 F4 E2 D1 E3 D2 F5 E4 D3 C1 C2 B1VSS2 VDDC MELI6 MELI7 ADLR DITO VSS AFRM ACLK ADIR ADAT0 VDDS ADAT9 ADAT3 ADAT1 ADAT2 ADAT10 ADAT6 VSS VDDS ADAT4 ADAT5 ADAT11 ADAT7 ADAT14 ADAT15 ADAT13 ADAT8 ADAT12 TDI VSS2 VDDC HRD13 HRD15 HRD14 HRD12 HRD7 HRD6 HRD10 HRD11 HRD9 HRD8 VSS VDDS HRD5 HRD4 HRD3 HRD2 HRD1 VDDS HRD0 RWEN RQML RCAS RRAS RA13 VDDS VDDS RA10 RA12 RA1 RA2 VDDS VSS RA0 RA3 RA4 RA5 VSS2 VSS RA6 RA7 RA9 RA8 VDDC VSS2 RA11 RCLK RCLKE RCLKIN VDDS VDDC RQMH LRD15 LRD14 LRD13 VDDS VSS LRD12 LRD11 LRD8 VDDS LRD10 VDDS LRD9 LRD7 LRD5 LRD6 LRD4 VSS2 VSS LRD3 LRD2 LRD1 LRD0- - I I O O - I/O I/O O I/O - I/O I/O I/O I/O I/O I/O - - I/O I/O I/O I/O I/O I/O I/O I/O I/O I - - I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O - - I/O I/O I/O I/O I/O - I/O O O O O O - - O O O O - - O O O O - - O O O O - - O O O I - - O I/O I/O I/O - - I/O I/O I/O - I/O - I/O I/O I/O I/O I/O - - I/O I/O I/O I/OGround Power supply +1.5 V MEL wave data input Power supply +3 V Ground Data bus (ABUS) Power supply +3 V Data bus (ABUS) Ground Power supply +3 V Data bus (ABUS) Ground Power supply +1.5 V DRAM data bus Ground Power supply +3 V DRAM data bus Power supply +3 V DRAM data bus DRAM write enable DRAM column address strobe (RAS signal) DRAM row address strobe (RAS signal) DRAM address bus Power supply +3 V Power supply +3 V DRAM address bus Power supply +3 V Ground DRAM address bus Ground Ground DRAM address bus Power supply +1.5 V Ground DRAM address bus Power supply +3 V Power supply +1.5 V DRAM data bus (Lower data) Power supply +3 V Ground DRAM data bus (Lower data) Ground DRAM data bus (Lower data) Ground DRAM data bus (Lower data) Ground Ground DRAM data bus (Lower data)
33 Tyros / TRS-MS01 PIN PIN NO.NAME I/O FUNCTION NO.NAME I/O FUNCTION 1 TEST I Test pin 41 SD0 I/O 2 VDD Power supply 42 SD1 I/O 3 XIN I Clock 43 SD2 I/O 4 XOUT O Clock 44 SD3 I/O 5 VSS Ground 45 SD4 I/O 6 /RESET I Reset 46 SD5 I/O 7 /MCS I Main CPU chip select 47 SD6 I/O 8 /MRD I Main CPU read 48 SD7 I/O 9 /MWR I Main CPU write 49 SD8 I/O Slave CPU data 0-15 10 /MIRQ O Main CPU interrupt request 50 SD9 I/O 11 MA0 I Main CPU address 0 51 SD10 I/O 12 VSS Ground 52 VSS (Ground) 13 MA1 I 53 SD11 I/O 14 MA2 I Main CPU address 1-454 SD12 I/O 15 MA3 I 55 SD13 I/O 16 MA4 I 56 SD14 I/O 17 MD0 I/O 57 SD15 I/O 18 MD1 I/O 58 /TXREQ I 4-bit CPU send data request 19 MD2 I/O 59 RRDY I 4-bit CPU ready 20 MD3 I/O 60 SCLK O 4-bit CPU clock 21 VSS (Ground) 61 SD I/O 4-bit CPU data 22 MD4 I/O 62 DR1 O KBS interface drive (pedal) 23 MD5 I/O 63 DR2 O KBS interface drive (lower keyboard)24 MD6 I/O 64 DR3 OKBS interface drive (upper keyboard)25 MD7 I/O 65 KD1 I Keyboard data scan (pedal) 26 MD8 I/O 66 KD2 IKeyboard data scan (lower keyboard)27 MD9 I/O Main CPU data 0-15 67 KD3 IKeyboard data scan (upper keyboard)28 MD10 I/O 68 KBSCLK O KBS clock 29 MD11 I/O 69 XCLK1 I 30 MD12 I/O 70 XCLK2 I KSN interface clock 31 MD13 I/O 71 XCLK3 I 32 MD14 I/O 72 KSEL I KBS/KSN select 33 VDD (Power supply) 73 VDD Power supply 34 MD15 I/O 74 ADSEL0 O 35 /SCS I Slave CPU chip select 75 ADSEL1 O FSV interface CH select 36 /SRD I Slave CPU read 76 ADSEL2 O 37 /SWR I Slave CPU write 77 ADMCLK O FSV A/D system clock (8 MHz) 38 /SIRQ O Slave CPU interrupt request 78 ADL/R O FSV A/D L/R clock(31.25 kHz) 39 SA0 I Slave CPU address 0 79 ADSCLK O FSV A/D bit clock(1 MHz) 40 VSS Ground 80 ADDATA I FSV A/D data TC160G22AF-1252 (XU135A00) MI2 ( MPU Interface 2 ) PIN PIN NO.NAME I/O FUNCTION NO.NAME I/O FUNCTION 1 DVSS - Digital Ground Pin 15 BVSS I Substrate Ground Pin, 0V 2 DVDD - Digital Power Supply Pin, 3.3V or 5.0V16 VREFL ILow Level Voltage Reference Input Pin3 MCLK I Master Clock Input Pin 17 VREFH -High Level Voltage Reference Input Pin4 PD I Power-Down Mode Pin 18 AVDD - Analog Power Supply Pin,5VWhen at L,the Ak4393 is in power-downmode and is held in reset. The AK4393 should always be reset upon power-up. 5 BICK I Audio Serial Data Clock Pin 19 AVSS O Analog Ground Pin, 0V The clock of 64fs or more than is 6 SDATA I recommended to be input on this pin. 20 AOUTR- O Rch Negative analog output Pin Audio Serial Data Input Pin 2s complement MSB-first data is input on this pin.7 LRCK I L/R Clock Pin 21 AOUTR+ O Rch Positive analog output Pin 8 SMUTE I Soft Mute Pin 22 AOUTL- O Lch Negative analog output Pin When this pin goes H, soft mute cycle is initiated.When returning L,the output mute releases.CS I Chip Select Pin in serial mode 9 DFS I Doubla speed sampling mode Pin 23 AOUTL+ O Lch Positive analog output Pin (Internal pull-down pin) L:Normal Speed, H:Double Speed 10 DEM0 I De-emphasis Enable pin 24 VCOM O Common Voltage Output Pin,2.6V CCLK I Control Data Clock Pin in serial mode 11 DEM1 I De-emphasis Enable pin 25 P/S I Parallel/Serial Select Pin(Internal pull-up pin)CDTI I Control Data Input Pin in serial modeL:Serial control mode,H: Parallel control mode12 DIF0 I 26 CKS0 I 13 DIF1 I Digital Input Format Pin 27 CKS1 I Master Clock Select Pin 14 DIF2 I 28 CKS2 I AK4393-VF-E2 (XW029A00) D/A Converter DM: IC71 DM: IC45 Main CPU data 0-15
34Tyros / TRS-MS01 PIN PIN NO.NAME I/O FUNCTION NO.NAME I/O FUNCTION 1 8//5 I Data transmission speed 33 /TRKO I Track 00 signal 2 XTALSET I Clock select 34 /INDEX I Index signal 3 /RESET I Rest 35 /RDATA I Read data input from FDD 4 E//RD I Enable/Read 36 XTAL2 Clock 5 RW//WR I Read/write/Write 37 EXTAL2 6 /CS I Chip select 38 NC 7 /DACK I DMA acknowledge 39 XTAL1 Clock 8 RS0 I Register select 40 EXTAL1 9 RS1 I 41 VSS4 Ground 10 VSS1 Ground 42 VSS5 11 VSS2 43 NC 12 D0 I/O 44 VCC2 13 D1 I/O 45 VCC3 Power supply 14 D2 I/O 46 VCC4 15 D3 I/O Data bus47 /WGATE O Write control 16 D4 I/O 48 /WDATA O Writ data to FDD 17 D5 I/O 49 VSS6 Ground 18 D6 I/O 50 /STEP O Step signal to control head of FDD 19 D7 I/O 51 /HDIR O Direction 20 /DREQ O DMA request 52 /HLOAD O Head load 21 /IRQ O Interrupt request 53 /HSEL O Head select 22 /DEND I Data end 54 VSS7 Ground 23 VSS3 Ground 55 /DS0 O 24 1/2 EX1 56 /DS1 O Drive select 25 VCC1 Power supply 57 /DS2 O 26 NUM1 I 58 /DS3 O 27 NUM3 I 59 VSS8 Ground 28 IFS I Host interface select 60 /MON0 O 29 SFORM I Format data 61 /MON1 O Motor on 30 /INP I Index pulse 62 /MON2 O 31 /READY I Ready from FDD 63 /MON3 O 32 /WPRT I Write control signal 64 VSS9 Ground HD63266F (XI939A00) FDC (Floppy Disk Controller) PIN PIN NO.NAME I/O FUNCTION NO.NAME I/O FUNCTION 1 P50/A8 I/O Port 5 / Higher address bus 33 P10/ANI0 I Port 1 / A/D converter analog input 2 P51/A9 I/O Port 5 / Higher address bus 34 AVREF I A/D converter reference voltage input3 P51/A10 I/O Port 5 / Higher address bus 35 AVDD Analog power supply 4 P53/A11 I/O Port 5 / Higher address bus 36 RESET I System reset input 5 P54/A12 I/O Port 5 / Higher address bus 37 XT2 Subsystem clock oscillation 6 P55/A13 I/O Port 5 / Higher address bus 38 XT1 I Subsystem clock oscillation 7 P56/A14 I/O Port 5 / Higher address bus 39 IC Internally connected 8 P57/A15 I/O Port 5 / Higher address bus 40 X2 Main system clock oscillation 9 Vss0 Ground 41 X1 I Main system clock oscillation 10 VDD0 Power supply 42 Vss1 Ground 11 P30 I/O Port 3 43 P00/INTP0I/OPort 0 / External interrupt request input12 P31 I/O Port 3 44P01/INTP1I/OPort 0 / External interrupt request input13P32/SDA0I/O Port 3 / Serial data input/output 45P02/INTP2I/OPort 0 / External interrupt request input14P33/SCL0I/O Port 3 / Serial clock input/output 46P03/INTP3/ADTRGI/OPort 0 / External interrupt request input / Trigger signai input15 P34 I/O Port 3 47P70/TI00/TO0I/OPort 7 / External count clock input / 16-bit timer/event counter 0 output16 P35 I/O Port 3 48 P71/TI01 I/O Port 7 / Capture trigger input 17 P36 I/O Port 3 49P72/TI50/TO50I/OPort 7 / External count clock input / 8-bit timer/event counter 50 output18 P20/SI30 I/O Port 2 / Serial data input 50P73/TI51/TO51I/OPort 7 / External count clock input / 8-bit timer/event counter 51 output19P21/SO30I/O Port 2 / Serial data output 51 P74/PCL I/O Port 7 / Clock output 20P22/SCK30I/O Port 2 / Serial clock input/output 52 P75/BUZ I/O Port 7 / Buzzer output 21P23RxD0I/O Port 2 / Serial data input 53 P64/RD I/OPort 6 / Strobe signal output for reading22P24/TxD0I/O Port 2 / Serial data output 54 P65/WR I/OPort 6 / Strobe signal output for writing23P25/ASCK0I/O Port 2 / Serial clock input/output 55P66/WAITI/O Port 6 / Wait insertion 24 VDD1 Power supply 56P67/ASTBI/O Port 6 / Strobe output 25 AVss Ground 57 P40/AD0 I/O Port 4 / Lower address/data bus 26 P17/ANI7I Port 1 / A/D converter analog input 58 P41/AD1 I/O Port 4 / Lower address/data bus 27P16/ANI6I Port 1 / A/D converter analog input 59 P42/AD2 I/O Port 4 / Lower address/data bus 28P15/ANI5I Port 1 / A/D converter analog input 60 P43/AD3 I/O Port 4 / Lower address/data bus 29P14/ANI4I Port 1 / A/D converter analog input 61 P44/AD4 I/O Port 4 / Lower address/data bus 30P13/ANI3I Port 1 / A/D converter analog input 62 P45/AD5 I/O Port 4 / Lower address/data bus 31P12/ANI2I Port 1 / A/D converter analog input 63 P46/AD6 I/O Port 4 / Lower address/data bus 32P11/ANI1I Port 1 / A/D converter analog input 64 A47/AD7 I/O Port 4 / Lower address/data bus UPD780031AYGK-NO1-9ET (XZ916100) LED DRIVER/SWITCH SCAN DM: IC1 PNR: IC1, PNL: IC1
35 Tyros / TRS-MS01 PIN PIN NO.NAMEI/O FUNCTION NO.NAMEI/O FUNCTION 1 AB2 I Address bus input (A [12:1]) 65 MA2 O Maltiplex memory address bus 2 AB1 I Address bus input (A [12:1]) 66 MA4 O Maltiplex memory address bus 3 AB0 I SH-3 bus Interface 67 MA3 O Maltiplex memory address bus 4 CS# I Decode 68 V SSVSS5 M/R# I/O Registor Setting 69 CLKI I Selectable Input clock 6 BS# I Bus Start Signal Input 70 TESTEN I Test enable interface 7 RD# I Read Signal Input 71 CLKI2 I Selectable Input clock 8 WE0# I Wright Enable input 72 V DDVDD9 WE1# I/O Wright Enable input 73FPFRAMEO Frame pulse 10 RD/WR# I Read / Wright Signal Input 74 FPLINE O Line pulse 11 RESET# I Reset 75 NC 12 V DDVDD76 DRDY O MOD output 13 BUSCLK I System Bus Clock 77 FPSHIFT O Shift clock 14 V SSVSS78 VSSVSS15 WAIT# O Wait Output 79 FPDAT0 O LCD panel data bus 16 DB15 I/O System Data Bus 80 FPDAT1 O LCD panel data bus 17 DB14 I/O System Data Bus 81 FPDAT2 O LCD panel data bus 18 DB13 I/O System Data Bus 82 FPDAT3 O LCD panel data bus 19 DB12 I/O System Data Bus 83 FPDAT4 O LCD panel data bus 20 DB11 I/O System Data Bus 84 FPDAT5 O LCD panel data bus 21 DB10 I/O System Data Bus 85 FPDAT6 O LCD panel data bus 22 DB9 I/O System Data Bus 86 FPDAT7 O LCD panel data bus 23 DB8 I/O System Data Bus 87 V SSVSS24 DB7 I/O System Data Bus 88 FPDAT8 O LCD panel data bus 25 DB6 I/O System Data Bus 89 FPDAT9 O LCD panel data bus 26 DB5 I/O System Data Bus 90 FPDAT10 O LCD panel data bus 27 DB4 I/O System Data Bus 91 FPDAT11 O LCD panel data bus 28 DB3 I/O System Data Bus 92 FPDAT12 O LCD panel data bus 29 DB2 I/O System Data Bus 93 FPDAT13 O LCD panel data bus 30 DB1 I/O System Data Bus 94 FPDAT14 I/O LCD panel data bus 31 DB0 I/O System Data Bus 95 FPDAT15 I/O LCD panel data bus 32 V SSVSS96 VSSVSS33 VDDVDD97 VDDVDD34 MD15 I/O Memory data I/O bus 98 DACVSSDACVSS35 MD0 I/O Memory data I/O bus 99 DACVDDDACVDD36 MD14 I/O Memory data I/O bus 100 RED O CRT output: RED 37 MD1 I/O Memory data I/O bus 101 IREF I DAC current 38 MD13 I/O Memory data I/O bus 102 DACV DDDACVDD39 MD2 I/O Memory data I/O bus 103 GREEN O CRT output: GREEN 40 MD12 I/O Memory data I/O bus 104 DACVDDDACVDD41 MD3 I/O Memory data I/O bus 105 BLUE O CRT output: BLUE 42 MD11 I/O Memory data I/O bus 106 DACVSSDACVSS43 MD4 I/O Memory data I/O bus 107 HRTC O Horizontal trace signal 44 MD10 I/O Memory data I/O bus 108 VRTC O Vertical trace signal 45 MD5 I/O Memory data I/O bus 109 V DDVDD46 MD9 I/O Memory data I/O bus 110 VSSVSS47 MD6 I/O Memory data I/O bus 111 AB20 I Address bus input (A20) 48 MD8 I/O Memory data I/O bus 112 AB19 I Address bus input (A19) 49 MD7 I/O Memory data I/O bus 113 AB18 I Address bus input (A18) 50 V SSVSS114 AB17 I Address bus input (A17) 51 LCAS# O LCAS# output 115 AB16 I Address bus input (A [16:13]) 52 UCAS# O UCAS# output 116 AB15 I Address bus input (A [16:13]) 53 WE# O WE# output 117 AB14 I Address bus input (A [16:13]) 54 RAS# O RAS# output 118 AB13 I Address bus input (A [16:13]) 55 V DDVDD119 AB12 I Address bus input (A [12:1]) 56 MA9 I/O GPIO3 120 AB11 I Address bus input (A [12:1]) 57 MA11 I/O GPIO2 121 AB10 I Address bus input (A [12:1]) 58 MA8 O Maltiplex memory address bus 122 AB9 I Address bus input (A [12:1]) 59 MA10 I/O GPIO1 123 AB8 I Address bus input (A [12:1]) 60 MA7 O Maltiplex memory address bus 124 AB7 I Address bus input (A [12:1]) 61 MA0 O Maltiplex memory address bus 125 AB6 I Address bus input (A [12:1]) 62 MA6 O Maltiplex memory address bus 126 AB5 I Address bus input (A [12:1]) 63 MA1 O Maltiplex memory address bus 127 AB4 I Address bus input (A [12:1]) 64 MA5 O Maltiplex memory address bus 128 AB3 I Address bus input (A [12:1]) S1D13506F00A (XZ690A00) COLOR LCD / CRT / TV ControllerDM: IC72
36Tyros / TRS-MS01 IC BLOCK DIAGRAM (Tyrps) TC74HC245AF (XS720A00) TRANSCEIVER 1 D1R 2 3 4 5 6 7 8 9 10 A1 A2 A3 A4 A5 A6 A7 A8 GND11 12 13 14 15 16 17 18 19 20 V CC G B1 B2 B3 B4 B5 B6 B7 B8 TC74VHCT245AFT (XT744A00) HD74LVC245A (XW148A00) HD74LVC138FP (XS963A00) SN74LVC138ANSR (X3510A00) 3 to 8 Demultiplexer 1 2 3 4 5 6 7 15 14 13 12 11 10 16 A B C G2A G2B G1Y7 Vcc Y0 Y1 Y2 Y3 Y4 Y5 89 GND Y6 A B C G2A G1 Y0 Y1 Y2 Y4 Enable Output Select G2B Y3 Y7 Y5 Y6Output TC74VHC157F(EL) (XT475A00) MULTIPLEXER 1G 1A 1B 1Y0 1Y1 1Y2 1Y3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Vcc 2G 2Y2 2Y0 2A 2B 2Y1 2Y3 TC74VHC04F EL (XM332A00) TC74HCU04AFEL (XD598A00) Hex Inverter 1 2 3 4 5 6 7 1A 1Y 2A 2Y 3A 3Y Vss 14 13 12 11 10 9 8 VDD 6A 6Y 5A 5Y 4A 4Y TC74VHC14FT (XV890A00) Hex Inverter 11A 21Y 32A 42Y 53A 63Y 7GND 1VDD 26A 36Y 45A 55Y 64A 74Y TC74VHC74F-EL (XW875A00) Dual D-Type Flip-Flop INPUTS OUTPUTS PR CLR CLK D Q Q L H H L H Q O H L H H L Q O X X X H L X X X X f f L H L L H H H L H L H H H 1 2 3 4 5 6 7 1CLR 1D 1CK 1PR 1Q 1Q GND14 13 12 11 10 9 8 VCC 2CLR CLR2DD 2CKCK 2PRPR 2Q 2Q Q Q CLRD CK PR Q Q HD74LS09FPEL (XP642A00) TC74VHC08FT (XV891A00) Quad 2 Input AND 1 2 3 1A 1Y 4 2A 5 2B 6 2Y 7 VSS 1B 14 13 12 VDD 4A 11 4Y 10 3B 93A 83Y4B TC74VHC11F(EL) (XT812A00) Triple 3 Input AND 1 2 31A 2A 42B 52C 62Y 7VSS 1B 14 13 12VDD 1Y 113C 103B 93A 83Y 1C TC74VHC32FT (XY945A00) TC74VHC32FT (XZ372A00) Quad 2 Input OR 1 2 3 1A 1Y 4 2A 5 2B 6 2Y 7 GND 1B 14 13 12 Vcc 4A 11 4Y 10 3B 93A 83Y4B DM: IC080, IC082, IC091 DM: IC030 DM: IC025, IC026, IC027, IC028, IC029, IC036, IC073, IC074, IC075, IC076, IC077 DM: IC035 DM: IC010 DM: IC081, IC033 DM: IC014 DM: IC037 DM: IC018, IC034
37 Tyros / TRS-MS01 1 2 3 4 5 6 7 89 1011 1213 14 15 16OUT1 IN1 VDD NC NC IN2 OUT2 Balance/Indivdual Volume control Refarence Voltage Filter NC GND Volume/Volume2 control Noise reduction Balance/VOLUME2 Pass/VCA Switching M51132L/FP (XE470A00) VCA Switching Controled Voltage Regulater SN74AHCT1G08DCKR (X0158A00) Single 2-Input Positive-AND Gate 1 2 3 A B GND5 4 Vcc Y INPUTSFUNCTION TABLE OUTPUT AB Y H L L H X L H L X LA6517M-TE-R (XT131A00) NJM2100D (XZ435A00) Dual Low Voltage Power AmplifierDM: IC002, IC006 AJACK: IC007 AJACK: IC004 PC: IC001 µPC4570G2 (XF291A00) Dual Operational Amplifier 1 2 3 4-V8 7 6 5 Output A+V Non-Inverting Input A -DC Voltage Supply+DC Voltage Supply Output B Inverting Input B Non-Inverting Input B Inverting Input A+- +- DM: IC044, IC047, IC049, IC050, IC053, IC056, IC058 AJACK:IC001, IC002, IC003, IC005, IC006 IC BLOCK DIAGRAM (TRS-MS01) KIA7812AP (XN324A00) Dual Operational Amplifier 1 2 3 4-V8 7 6 5 Output A+V Non-Inverting Input A -DC Voltage Supply+DC Voltage Supply Output B Inverting Input B Non-Inverting Input B Inverting Input A+- +- MAIN: IC1, IC2, IC7
38Tyros / TRS-MS01 CIRCUIT BOARDS (Tyros) CONTENTS DJACK Circuit Board (X2510C0) .................................................................................. 39 DM Circuit Board (X2584D0) ........................................................................................ 40 PNL Circuit Board (X2501E0) ....................................................................................... 44 PNR Circuit Board (X2500E0) ...................................................................................... 48 PNC Circuit Board (X2502C0) ...................................................................................... 52 AJACK Circuit Board (X2509D0) .................................................................................. 54 LCR Circuit Board (X2503D0) ...................................................................................... 56 LCL Circuit Board (X2503D0) ....................................................................................... 57 EN Circuit Board (X2500E0) ......................................................................................... 57 INLET Circuit Board (X2621C0) ................................................................................... 58 PC Circuit Board (X2612B0) ......................................................................................... 58 EMKS-N Circuit Board (X2610C0) ................................................................................ 59 REG Circuit Board (X3184A0) ...................................................................................... 59 SPOUTR Circuit Board (X2612C0) ............................................................................... 60 SPOUTL Circuit Board (X2612C0) ............................................................................... 60 PHONES Circuit Board (X2612C0) .............................................................................. 60 MICVR Circuit Board (X2501E0) .................................................................................. 61 MICVRSUB Circuit Board (X2612C0) ........................................................................... 61 CIRCUIT BOARDS (TRS-MS01) CONTENTS MAIN (A) .......................................................................................................................62 MAIN (B) .......................................................................................................................64 MAIN (C) .......................................................................................................................64 MAIN (S) .......................................................................................................................64
39 Tyros / TRS-MS01 IN OUT VIDEO OUT NTSC / PAL USB MIDI B to DM-CN21 to DM-CN13 to DM-CN2 H H’ 321 IN N OUTMIDI A ASSIGNABLE FOOT PEDAL (VOLUME) (DSP VARIATION) (SUSTAIN) H H’ DJACK Circuit Board Component Side Note: See parts list for details of circuit board component parts. 2NA-V881320 2
40Tyros / TRS-MS01 DM Circuit Board 2NA-V892380 to HARDDISK DRIVE (Option) A A’ Component Side