Yamaha Tyros 1 Service Manual

							Tyros / TRS-MS01
21
[30][40][50][60]
[A]
(Fig.16)
(Fig.17) (Fig.18)
[30]: Bind Head Tapping Screw-B 4.0X12 MFZN2BL (VR138400)
[40]: Bind Head Tapping Screw-B 4.0X12 MFZN2BL (VR138400)
[50]: Bind Head Tapping Screw-B 4.0X12 MFZN2BL (VR138400)
[60]: Bind Head Tapping Screw-B 4.0X12 MFZN2BL (VR138400)
22. MICVR Circuit Board
(Time required: about 10 min)
22-1 Separate the unit into the upper case assembly and the
lower case assembly. (See procedure 1)
22-2 Remove the five (5) screws marked [480d]. (Fig.13)
22-3 Remove the knob marked [40] and the knob marked
[50]. The MICVR circuit board can then be removed.
(Fig.16)
23. The EN Circuit Board
(Time required: about 11 min)
23-1 Separate the unit into the upper case assembly and the
lower case assembly. (See procedure 1)
23-2 Remove the shield upper cover. (See procedure 20-2)
23-3 Insert a screw driver (which is not sharp-edged) into
the hole beside the EN circuit board, and push out the
encoder knob marked [60]. (Fig.16, Fig.17)
* It may damage the encoder knob to push continuously
the same point on it. So push out the encoder knob bit
by bit rotating it.23-4 Remove the hexagonal nut marked [A]. The EN cir-
cuit board can then be removed. (Fig.18)
24. Wheel Assembly (Time required: about 10 min)
24-1 Separate the unit into the upper case assembly and the
lower case assembly. (See procedure 1)
24-2 Remove the four (4) screws marked [480e]. The wheel
assembly can then be removed. (Fig.13)
25. Power Switch (Time required: about 10 min)
25-1 Separate the unit into the upper case assembly and the
lower case assembly. (See procedure 1)
25-2 Remove the two (2) screws marked [480f]. The power
switch can then be removed. (Fig.13) 
						

							Tyros / TRS-MS01
22
Hook
Dust proof foam
(Fig.20) (Fig.21) (Fig.22)
(Fig.23) (Fig.24)
[620b][620b][620a]
(Fig.19)
[620]: Bind Head Tapping Screw-B 3.0X12 MFZN2BL (VQ074600)
26 LCD Panel Assembly
(Time required: about 14 min)
26-1 Separate the unit into the upper case assembly and the
lower case assembly. (See procedure 1)
26-2 Remove the shield upper cover. (See procedure 20-2)
26-3 Remove the two (2) screws marked [620a] to unfix the
stay bar from notch. (Fig.19)
26-4 Remove the four (4) screws marked [620b]. (Fig.19)
26-5 Remove the screw marked [C] to remove the GND2
wire on the PNR circuit board. (Fig.13)
26-6 Lay the upper case assembly right side up, unlock the
hook of LCD panel assembly and raise the LCD unit
upright. (Fig.20)26-7 Remove the two (2) dust proof cloths. (Fig.22)
26-8 Pull out the LCD panel assembly to remove. (Fig.21)
* After removing the LCD panel asssembly, take care
not to lose the dust proof cloth. (Fig.22)
* After reinstalling the LCD panel assembly, follow the
procedure below and confirm that its angle can be ad-
justed.
(1) Lay the upper case assembly right side up.
(2) Unlock the hook, raise the panel forward, and con-
firm that the panel can be steadied at four notches.
(Fig.23)
(3) After raising the panel completely, confirm that it
can be laid down smoothly. (Fig.24) 
						

							Tyros / TRS-MS01
23
[180a] Gear
LCD Lower Case
[180b][180b]
[180] Hinge
Hinge
[180]
LCD Lower Case
[190a] [190b]
[190c]
[A]
LCD
[A]
[B]
[B]
LCLLCR
LCD Upper Case
(Fig.25)
(Fig.26)
(Fig.27)
[180]: Bind Head Tapping Screw-B 3.0X12 MFZN2BL (VQ074600)
[190]: Bind Head Tapping Screw-B 3.0X8 MFZN2Y (EP600250)[180]: Bind Head Tapping Screw-B 3.0X12 MFZN2BL (VQ074600)
27. Disassembly of the LCD Panel Assembly
27a. Gear (Time required: about 15 min)
27a-1 Remove the LCD panel Assembly. (See procedure 26)
27a-2 Remove the four (4) screws marked [180a]. The gear
can then be removed. (Fig.25)
27b Hinge (Time required: about 16 min)
27b-1 Remove the LCD panel Assembly. (See procedure 26)
27b-2 Remove the eight (8) screws marked [180b] to remove
the LCD lower case. (Fig.25)
27b-3Remove the two (2) screws marked [180] for each side.
The hinges can then be removed. (Fig.26)
27c LCL Circuit Board
(Time required: about 16 min)
27c-1 Remove the LCD panel assembly. (See procedure 26)
27c-2 Remove the LCD lower case. (See procedure 27b-2)
27c-3 Remove the five (5) screws marked [190a]. The LCL
circuit board can then be removed. (Fig.27)
* When reinstalling the LCL circuit board, tighten the
two screws marked [A] before others. (Fig.27)
27d LCR Circuit Board
(Time required: about 16 min)
27d-1 Remove the LCD panel assembly. (See procedure 26)
27d-2 Remove the LCD lower case. (See procedure 27b-2)
27d-3 Remove the six (6) screws marked [190b]. The LCR
circuit board can then be removed. (Fig.27)
* When reinstalling the LCR circuit board, tighten the
two (2) screws marked [B] before others. (Fig.27)
27e LCD (Time required: about 16 min)
27e-1 Remove the LCD panel assembly. (See procedure 26)
27e-2 Remove the LCD lower case. (See procedure 27b-2)
27e-3 Remove the four (4) screws marked [190c]. The LCD
can then be removed. (Fig.27) 
						

							Tyros / TRS-MS01
24

 DISASSEMBLY PROCEDURE (TRS-MS01)
1. Rear Panel (Time required: about 1 min)
[30]
AMP Assembly
Cover
2. AMP Assembly (Time required: about 3 min)
2-1 Remove the rear panel. (See procedure 1)
L
RTO KEYBOARD
[17] [18][19]
[16]
Rear Panel
(Fig.1)
(Fig.2)
[16]: Bind Head Bonding Screw-B 3x10 MFC2BL (EN335030)
[17]: Bind Head Screw-P 3x12 MFC2BL (EX601360)
[18]: Bind Head Screw 3x8 MFC2BL (ED330086)
[19]: Bind Head Screw-S 4x8 MFC2BL (EK396010)[30]: Bind Head Tapping Screw   4x20 MFZN2BL (EP040070)
1-1 Remove the eight (8) screws marked [30]. (Fig.1, Fig.2)
(The screws to be removed are indicated by arrows on
the panel.)* When reinstalling the rear panel, confirm that the pack-
ing is not damaged to avoid air leakage.)
2-2 Remove the two (2) screws marked [17], the four (4)
screws marked [18], the four (4) screws marked [19].
The AMP assembly can then be removed. (Fig.2) 
						

							Tyros / TRS-MS01
25 3. MAIN (C) [Power Switch]
(Time required: about 2 min)
[16]
Power Switch
(Fig.3)
4. Front Panel (Time required: about 1 min)
4-1 Lay the unit upside down, insert a thin plate such as a
ruler into the two slits on the bottom, then unclench
slightly the front panel. (Fig4)
* Take great care not to damage the cabinet. Stop
unclenching when a small clearance is formed.
4-2 Pull the front panel forward to remove. (Fig.5)
* The front panel is fixed on the cabinet by six dowels,
so take care not to force diagonally too much. (Fig.1)
Front Panel Cabinet Bottom Side
(Fig.4)
(Fig.5)
[24]
[24]
[24]
(Fig.6)
[24]: Bind Head Screw-P 3x10 MFZN2Y (EP600270) [16]: Bind Head Bonding Screw-B 3x10 MFC2BL (EN335030)
3-1 Remove the rear panel. (See procedure 1)
3-2 Remove the two (2) screws marked [16] to remove the
cover. (Fig.2)3-3 Remove the two (2) screws marked [16]. The MAIN
(C) circuit board can then be removed. (Fig.3)
5. Front Grille Assembly (Time required: about 2
min)
5-1 Remove the front panel. (See procedure 4)
5-2 Remove the four (4) screws marked [24]. The fornt
grille assembly can then be removed. (Fig.6)
6. Speaker (Time required: 2 min)
6-1 Remove the front panel. (See procedure 4)
6-2 Raise the front panel vertically. (Fig.7)
6-2 Remove the (4) screws marked [30]. The speaker can
then be removed. (Fig.7)
[30]
[30]
Front Panel Speaker
[30]: Bind Head Tapping Screw   4x20 MFZN2BL (EP040070)
(Fig.7) 
						

							26Tyros / TRS-MS01

 LSI PIN DESCRIPTION
CONTENTS
 HD6417709SF133 (X2081A00) CPU ........................................................................... 27
 HD6417709SHF200 (X2687A00) CPU ......................................................................... 28
 M4A3-64/64-10VC (X2987A00) CPLD ......................................................................... 29
 M66291GP (X2156A00) USB Controller ...................................................................... 29
 µPD780031AYGK-XXX (X0031200) CPU .................................................................... 30
 PCM1730E-1/2K (X2077A00) DAC .............................................................................. 30
 PCM1800 (XU770A00) A/D Converter ......................................................................... 30
 T8F02TB-0102 (X0060A00) SWP50 ............................................................................ 31
 T8F02TB-0102 (X0060A00) SWP50 ............................................................................ 32
 TC160G22AF-1252 (XU135A00) MI2 ........................................................................... 33
 AK4393-VF-E2 (XW029A00) D/A Converter ................................................................. 33
 HD63266F (XI939A00) FDC ......................................................................................... 34
 UPD780031AYGK-NO1-9ET (XZ916100) LED DRIVER/SWITCH SCAN ................... 34
 S1D13506F00A (XZ690A00) COLOR LCD / CRT / TV Controller ................................ 35 
						

							27 Tyros / TRS-MS01
PIN PIN
NO.NAMEI/O FUNCTION
NO.NAMEI/O FUNCTION
1 MD1 I Mode control 105 CKE/PTK5 I/O CK enable / Port K
2 MD2 I 106 RAS3L/PTJ0 I/O RAS address bus / Port J
3 Vcc(RTC) - Power supply +1.8 V 107 PTJ1 I/O Port J
4 XTAL2 O Cry stal oscillator 108 CASL/PTJ2 I/O CAS address bus / Port J
5 EXTAL2 I 109 VssQ - Ground
6 Vss(RTC) - Ground 110 CASU/PTJ3 I/O CAS address bus / Port J
7 NMI I Non-maskable interrupt request 111 VccQ - Power supply +3.3 V
8
IRQ0/IRL0/PTH0I 112 PTJ4 I/O
Port J
9IRQ1/IRL1/PTH1I 113 PTJ5 I/O
10IRQ2/IRL2/PTH2I Interrupt request / Port H 114DACK0/PTD5I/O
DMA acknowledge / Port D
11IRQ3/IRL3/PTH3I115DACK1/PTD7I/O
12 IRQ4/PTH4 I 116 PTE6 I/O
Port E
13 D31/PTB7 I/O 117 PTE3 I/O
14 D30/PTB6 I/O 118
RAS3U/PTE2I/O RAS address bus / Port E
15 D29/PTB5 I/O
Data bus / Port B119 PTE1 I/O Port E
16 D28/PTB4 I/O 120 TDO/PTE0 I/O Test data / Port E
17 D27/PTB3 I/O 121 BACK O Bus acknowledge
18 D26/PTB2 I/O 122 BREQ I Bus request
19 VssQ - Ground 123 WAIT I Hardware wait request
20 D25/PTB1 I/O Data bus / Port B 124 RESETM I Manual reset
21 VccQ - Power supply +3.3 V 125
ADTRG/PTH5I Analog trigger / Port H
22 D24/PTB0 I/O Data bus / Port B 126IOIS16/PTG7I Write protect / Port G
23 D23/PTA7 I/O 127ASEMD0/PTG6I ASE mode / Port G
24 D22/PTA6 I/O
Data bus / Port A128ASEBRKAK/PTG5I/O ASE break acknowledge / Port G
25 D21/PTA5 I/O 129PTG4/CKIO2I/O Port G / Clock output
26 D20/PTA4 I/O 130AUDATA3/PTG3I/O
AUD data / Port G
27 Vss - Ground 131AUDATA2/PTG2I/O
28 D19/PTA3 I/O Data bus / Port A 132 Vss - Ground
29 Vcc - Power supply +1.8 V 133
AUDATA1/PTG1I/O AUD data / Port G
30 D18/PTA2 I/O 134 Vcc - Power supply +1.8 V
31 D17/PTA1 I/O Data bus / Port A 135
AUDATA0/PTG0I/O AUD data / Port G
32 D16/PTA0 I/O 136TRST/PTF7/PINT15I Test reset / Port F / Port interruption
33 VssQ - Ground 137TMS/PTF6/PINT14I Test mode switch / Port F / Port interruption
34 D15 I/O Data bus 138TDI/PTF5/PINT13I Test data / Port F / Port interruption
35 VccQ - Power supply +3.3 V 139TCK/PTF4/PINT12I Test clock / Port F / Port interruption
36 D14 I/O 140IRLS3/PTF3/PINT11I
37 D13 I/O 141IRL2/PTF2/PINT10I
Interrupt request / Port F / Port interruption
38 D12 I/O 142IRLS1/PTF1/PINT9I
39 D11 I/O 143IRLS0/PTF0/PINT8I
40 D10 I/O Data bus 144 MD0 I Mode control
41 D9 I/O 145 Vcc(PLL1) - Power supply +1.8 V
42 D8 I/O 146 CAP1 - Capacitor
43 D7 I/O 147 Vss(PLL1) - Ground
44 D6 I/O 148 Vss(PLL2) - Ground
45 VssQ - Ground 149 CAP2 - Capacitor
46 D5 I/O Data bus 150 VCC(PLL2) - Power supply +1.8 V
47 VccQ - Power supply +3.3 V 151
AUDCK/PTH6I AUD clock / Port H
48 D4 I/O 152 Vss - Ground
49 D3 I/O 153 Vss -
50 D2 I/O Data bus 154 Vcc - Power supply +1.8 V
51 D1 I/O 155 XTAL1 O Crystal oscillator
52 D0 I/O 156 EXTAL1 I
53 A0 O 157
STATUS0/PTJ6I/O
Processor status / Port J
54 A1 O
Address bus158STATUS1/PTJ7I/O
55 A2 O 159 TCLK/PTH7 I/O Timer clock / Port H
56 A3 O 160 /IRQOUT O Interrupt request output
57 VssQ - Ground 161 VssQ - Ground
58 A4 O Address bus 162 CKIO I/O System clock input / output
59 VccQ - Power supply +3.3 V 163 VccQ - Power supply +3.3 V
60 A5 O 164
TXD0/SCPT0O Data transmission / SCI port
61 A6 O 165SCK0/SCPT1I/O Serial clock / SCI port
62 A7 O 166TXD1/SCPT2O Data transmission / SCI port
63 A8 O 167SCK1/SCPT3I/O Serial clock / SCI port
64 A9 O Address bus 168TXD2/SCPT4O Data transmission / SCI port
65 A10 O 169SCK2/SCPT5I/O Serial clock / SCI port
66 A11 O 170RTS2/SCPT6I/O Transmit request / SCI port
67 A12 O 171RXD0/SCPT0I
Data reception / SCI port
68 A13 O 172RXD1/SCPT2I
69 VssQ - Ground 173 Vss - Ground
70 A14 O Address bus 174
RXD2/SCPT4I Data reception / SCI port
71 VccQ - Power supply +3.3 V 175 Vcc - Power supply +1.8 V
72 A15 O 176
CTS2/IRQ5/SCPT7I Transmit clear / Interrupt request / SCI port
73 A16 O 177MCS7/PTC7/PINT7I/O
74 A17 O 178MCS6/PTC6/PINT6I/O
Mask ROM chip select / Port C / Port interruption
75 A18 O Address bus 179MCS5/PTC5/PINT5I/O
76 A19 O 180MCS4/PTC4/PINT4I/O
77 A20 O 181 VssQ - Ground
78 A21 O 182
WAKEUP/PTD3I/O Standby mode Interrupt request output / Port D
79 Vss - Ground 183 VccQ - Power supply +3.3 V
80 A22 O Address bus 184
RESETOUT/PTD2I/O Reset output / Port D
81 Vcc - Power supply +1.8 V 185MCS3/PTC3/PINT3I/O
82 A23 O Address bus 186MCS2/PTC2/PINT2I/O
Mask ROM chip select / Port C / Port interruption
83 VssQ - Ground 187MCS1/PTC1/PINT1I/O
84 A24 O Address bus 188MCS0/PTC0/PINT0I/O
85 VccQ - Power supply +3.3 V 189DRAK0/PTD1I/O DMA acknowledge / Port D
86 A25 O Address bus 190DRAK1/PTD0I/O
87 BS/PTK4 I/O Bus cycle / Port K 191DREQ0/PTD4I
DMA request / Port D
88 RD O Read strobe 192DREQ1/PTD6I
89WE0/DQMLLO Select signal (D7-D0) / D QM (SDRAM) 193 RESETP I Power on reset
90WE1/DQMLU/WEOSelect signal (D15-D8) / D QM (SDRAM) / Write enable194 CA I Chip active
91WE2/DQMUL/ICIORD/PTK6I/OSelect signal (D23-D16) / D QM (SDRAM) / I/O read / Port K195 MD3 I
92WE3/DQMUU/ISIOWR/PTK7I/OSelect signal (D31-D24) / D QM (SDRAM) / I/O write / Port K196 MD4 I Mode control
93 RD/WR O Read / Write 197 MD5 I
94
AUDSYNC/PTE7I/O AUD cycle / Port E 198 AVss - Analog ground
95 VssQ - Ground 199 AN0/PTL0 I
96 CS0/MCS0 O Chip select / Mask ROM chip select 200 AN1/PTL1 I
97 VccQ - Power supply +3.3V 201 AN2/PTL2 I
Analog input / Port L
98 CS2/PTK0 I/O 202 AN3/PTL3 I
99 CS3/PTK1 I/O Chip select / Port K 203 AN4/PTL4 I
100 CS4/PTK2 I/O 204 AN5/PTL5 I
101
CS5/CE1A/PTK3I/O Chip select / Chip enable / Port K 205 AVcc - Analog power supply +3.3 V
102 CS6/CE1B O Chip select / Chip enable 206AN6/DA1/PTL6I/O Analog input / Analog output / Port L
103 CE2A/PTE4 I/O Chip enable / Port E 207AN7/DA0/PTL7I/O
104 CE2B/PTE5 I/O 208 AVss - Analog ground
HD6417709SF133 (X2081A00) CPU (SH3)DM: IC63 
						

							28Tyros / TRS-MS01
PIN PIN
NO.NAMEI/O FUNCTION
NO.NAMEI/O FUNCTION
1 MD1 I
Mode control105 CKE/PTK5 I/O CK enable / Port
2 MD2 I 106RAS3L/PTJ0I/O RAS address bus / Port J
3 Vcc(RTC) - Power supply +1.8 V 107 PTJ1 I/O Port J
4 XTAL2 O Crystal oscillator 108 CASL/PTJ2 I/O CAS address bus / Port J
5 EXTAL2 I 109 VssQ - Ground
6 Vss(RTC) - Ground 110 CASU/PTJ3 I/O CAS address bus / Port J
7 NMI I Non-maskable interrupt request 111 VccQ - Power supply +3.3 V
8
IRQ0/IRL0/PTH0I 112 PTJ4 I/O
Port J
9IRQ1/IRL1/PTH1I 113 PTJ5 I/O
10IRQ2/IRL2/PTH2I Interrupt request / Port H 114DACK0/PTD5I/O
DMA acknowledge / Port D
11IRQ3/IRL3/PTH3I115DACK1/PTD7I/O
12 IRQ4/PTH4 I 116 PTE6 I/O
Port E
13 D31/PTB7 I/O 117 PTE3 I/O
14 D30/PTB6 I/O 118
RAS3U/PTE2I/O RAS address bus / Port E
15 D29/PTB5 I/O
Data bus / Port B119 PTE1 I/O Port E
16 D28/PTB4 I/O 120 TDO/PTE0 I/O Test data / Port E
17 D27/PTB3 I/O 121 BACK O Bus acknowledge
18 D26/PTB2 I/O 122 BREQ I Bus request
19 VssQ - Ground 123 WAIT I Hardware wait request
20 D25/PTB1 I/O Data bus / Port B 124 RESETM I Manual reset
21 VccQ - Power supply +3.3 V 125
ADTRG/PTH5I Analog trigger / Port H
22 D24/PTB0 I/O Data bus / Port B 126IOIS16/PTG7I Write protect / Port G
23 D23/PTA7 I/O 127ASEMD0/PTG6I ASE mode / Port G
24 D22/PTA6 I/O
Data bus / Port A128ASEBRKAK/PTG5I/O ASE break acknowledge / Port G
25 D21/PTA5 I/O 129PTG4/CKIO2I/O Port G / Clock output
26 D20/PTA4 I/O 130AUDATA3/PTG3I/O
AUD data / Port G
27 Vss - Ground 131AUDATA2/PTG2I/O
28 D19/PTA3 I/O Data bus / Port A 132 Vss - Ground
29 Vcc - Power supply +1.8 V 133
AUDATA1/PTG1I/O AUD data / Port G
30 D18/PTA2 I/O 134 Vcc - Power supply +1.8 V
31 D17/PTA1 I/O Data bus / Port A 135
AUDATA0/PTG0I/O AUD data / Port G
32 D16/PTA0 I/O 136TRST/PTF7/PINT15I Test reset / Port F / Port interruption
33 VssQ - Ground 137TMS/PTF6/PINT14I Test mode switch / Port F / Port interruption
34 D15 I/O Data bus 138TDI/PTF5/PINT13I Test data / Port F / Port interruption
35 VccQ - Power supply +3.3 V 139TCK/PTF4/PINT12I Test clock / Port F / Port interruption
36 D14 I/O 140IRLS3/PTF3/PINT11I
37 D13 I/O 141IRL2/PTF2/PINT10I
Interrupt request / Port F / Port interruption
38 D12 I/O 142IRLS1/PTF1/PINT9I
39 D11 I/O 143IRLS0/PTF0/PINT8I
40 D10 I/O Data bus 144 MD0 I Mode control
41 D9 I/O 145 Vcc(PLL1) - Power supply +1.8 V
42 D8 I/O 146 CAP1 - Capacitor
43 D7 I/O 147 Vss(PLL1) - Ground
44 D6 I/O 148 Vss(PLL2) - Ground
45 VssQ - Ground 149 CAP2 - Capacitor
46 D5 I/O Data bus 150 VCC(PLL2) - Power supply +1.8 V
47 VccQ - Power supply +3.3 V 151
AUDCK/PTH6I AUD clock / Port H
48 D4 I/O 152 Vss - Ground
49 D3 I/O 153 Vss -
50 D2 I/O Data bus 154 Vcc - Power supply +1.8 V
51 D1 I/O 155 XTAL1 O Crystal oscillator
52 D0 I/O 156 EXTAL1 I
53 A0 O 157
STATUS0/PTJ6I/O
Processor status / Port J
54 A1 O 158STATUS1/PTJ7I/O
55 A2 OAddress bus
159 TCLK/PTH7 I/O Timer clock / Port H
56 A3 O 160 /IRQOUT O Interrupt request output
57 VssQ - Ground 161 VssQ - Ground
58 A4 O Address bus 162 CKIO I/O System clock input / output
59 VccQ - Power supply +3.3 V 163 VccQ - Power supply +3.3 V
60 A5 O 164
TXD0/SCPT0O Data transmission / SCI port
61 A6 O 165SCK0/SCPT1I/O Serial clock / SCI port
62 A7 O 166TXD1/SCPT2O Data transmission / SCI port
63 A8 O 167SCK1/SCPT3I/O Serial clock / SCI port
64 A9 O Address bus 168TXD2/SCPT4O Data transmission / SCI port
65 A10 O 169SCK2/SCPT5I/O Serial clock / SCI port
66 A11 O 170RTS2/SCPT6I/O Transmit request / SCI port
67 A12 O 171RXD0/SCPT0I
Data reception / SCI port
68 A13 O 172RXD1/SCPT2I
69 VssQ - Ground 173 Vss - Ground
70 A14 O Address bus 174
RXD2/SCPT4I Data reception / SCI port
71 VccQ - Power supply +3.3 V 175 Vcc - Power supply +1.8 V
72 A15 O 176
CTS2/IRQ5/SCPT7I Transmit clear / Interrupt request / SCI port
73 A16 O 177MCS7/PTC7/PINTI/O
74 A17 O 178 7 I/O
Mask ROM chip select / Port C / Port interruption
75 A18 O Address bus 179
MCS6/PTC6/PINTI/O
76 A19 O 180 6 I/O
77 A20 O 181
MCS5/PTC5/PINT- Ground
78 A21 O 182 5 I/O Standby mode Interrupt request output / Port D
79 Vss - Ground 183
MCS4/PTC4/PINT- Power supply +3.3 V
80 A22 O Address bus 184 4 I/O Reset output / Port D
81 Vcc - Power supply +1.8 V 185 VssQ I/O
82 A23 O Address bus 186
WAKEUP/PTD3I/O Mask ROM chip select / Port C / Port interruption
83 VssQ - Ground 187 VccQ I/O
84 A24 O Address bus 188
RESETOUT/PTD2I/O
85 VccQ - Power supply +3.3 V 189MCS3/PTC3/PINTI/O DMA acknowledge / Port D
86 A25 O Address bus 190 3 I/O
87 BS/PTK4 I/O Bus cycle / Port K 191
MCS2/PTC2/PINTI DMA request / Port D
88 RD O Read strobe 192 2 I
89
WE0/DQMLLO Select signal (D7-D0) / D QM (SDRAM) 193MCS1/PTC1/PINTI Power on reset
90WE1/DQMLU/WEOSelect signal (D15-D8) / D QM (SDRAM) / Write enable194 1 I Chip active
91WE2/DQMUL/ICIORD/PTK6I/OSelect signal (D23-D16) / D QM (SDRAM) / I/O read / Port K195MCS0/PTC0/PINTI
92WE3/DQMUU/ISIOWR/PTK7I/OSelect signal (D31-D24) / D QM (SDRAM) / I/O write / Port K196 0 I Mode control
93 RD/WR O Read / Write 197DRAK0/PTD1I
94AUDSYNC/PTE7I/O AUD cycle / Port E 198DRAK1/PTD0- Analog ground
95 VssQ - Ground 199DREQ0/PTD4I
96 CS0/MCS0 O Chip select / Mask ROM chip select 200DREQ1/PTD6I
97 VccQ - Power supply +3.3V 201 RESETP I
Analog input / Port L
98 CS2/PTK0 I/O 202 CA I
99 CS3/PTK1 I/O Chip select / Port K 203 MD3 I
100 CS4/PTK2 I/O 204 MD4 I
101
CS5/CE1A/PTK3I/O Chip select / Chip enable / Port K 205 MD5 - Analog power supply +3.3 V
102 CS6/CE1B O Chip select / Chip enable 206 AVss I/O Analog input / Analog output / Port L
103 CE2A/PTE4 I/O Chip enable / Port E 207 AN0/PTL0 I/O
104 CE2B/PTE5 I/O 208 AN1/PTL1 - Analog ground
HD6417709SHF200 (X2687A00) CPU (SH3)DM: IC9 
						

							29 Tyros / TRS-MS01
PIN PIN
NO.NAME I/O FUNCTION
NO.NAME I/O FUNCTION
1 GND Ground 51 GND Ground
2 TDI I Test data in 52 ENABLE Program
3 A1 I/O Data bus block A 53 C1 I/O Data bus block C
4 A3 I/O Data bus block A 54 C3 I/O Data bus block C
5 A5 I/O Data bus block A 55 C5 I/O Data bus block C
6 A7 I/O Data bus block A 56 C7 I/O Data bus block C
7 A9 I/O Data bus block A 57 C9 I/O Data bus block C
8 A11 I/O Data bus block A 58 C11 I/O Data bus block C
9 A13 I/O Data bus block A 59 C13 I/O Data bus block C
10 A15 I/O Data bus block A 60 C15 I/O Data bus block C
11 I0/CLK1 I 61 I3/CLK2
12 VCC Power supply 62 VCC Power supply
13 GND Ground 63 GND Ground
14 I1/CLK1 I 64 I4/CLK3
15 B15 I/O Data bus block B 65 D15 I/O Data bus block D
16 B13 I/O Data bus block B 66 D13 I/O Data bus block D
17 B11 I/O Data bus block B 67 D11 I/O Data bus block D
18 B9 I/O Data bus block B 68 D9 I/O Data bus block D
19 B7 I/O Data bus block B 69 D7 I/O Data bus block D
20 B5 I/O Data bus block B 70 D5 I/O Data bus block D
21 B3 I/O Data bus block B 71 D3 I/O Data bus block D
22 B1 I/O Data bus block B 72 D1 I/O Data bus block D
23 TMS Test mode select 73 TRST Test reset
24 TCK Test clock 74 TDO O Test data out
25 GND Ground 75 GND Ground
26 GND Ground 76 GND Ground
27 GND Ground 77 GND Ground
28 B14 I/O Data bus block B 78 D14 I/O Data bus block D
29 B12 I/O Data bus block B 79 D12 I/O Data bus block D
30 B10 I/O Data bus block B 80 D10 I/O Data bus block D
31 B8 I/O Data bus block B 81 D8 I/O Data bus block D
32 B6 I/O Data bus block B 82 D6 I/O Data bus block D
33 B4 I/O Data bus block B 83 D4 I/O Data bus block D
34 B2 I/O Data bus block B 84 D2 I/O Data bus block D
35 B0 I/O Data bus block B 85 D0 I/O Data bus block D
36 I2 I 86 I5 I
37 VCC Power supply 87 VCC Power supply
38 GND Ground 88 GND Ground
39 GND Ground 89 GND Ground
40 VCC Power supply 90 VCC Power supply
41 C0 I/O Data bus block C 91 A0 I/O Data bus block A
42 C2 I/O Data bus block C 92 A2 I/O Data bus block A
43 C4 I/O Data bus block C 93 A4 I/O Data bus block A
44 C6 I/O Data bus block C 94 A6 I/O Data bus block A
45 C8 I/O Data bus block C 95 A8 I/O Data bus block A
46 C10 I/O Data bus block C 96 A10 I/O Data bus block A
47 C12 I/O Data bus block C 97 A12 I/O Data bus block A
48 C14 I/O Data bus block C 98 A14 I/O Data bus block A
49 GND Ground 99 GND Ground
50 GND Ground 100 GND Ground
M4A3-64/64-10VC (X2987A00) CPLD
PIN PIN
NO.NAME I/O FUNCTION
NO.NAME I/O FUNCTION
1 Core Vcc  Core power supply 25 D2 I/O
2 GND Ground 26 D3 I/O
3 D- I/O USB data (-) 27 D4 I/O
4 D+ I/O USB data (+) 28 D5 I/O
5 Vbus I V bus input 29 D6 I/O
Data bus
6 Tr ON O Tr ON output 30 D7 I/O
7 TEST I TEST input 31 D8/P0 I/O
8 /Dack1 I DMA reception signal 1 32 D9/P1 I/O
9 /Dreq1 O DMA request 1 33 D10/P2 I/O
10 /TC1 I TC input 34 D11/P3 I/O
11
/INT1//SOFO Interrupt 1/SOF output 35 IOVcc I/O power supply
12 IOVcc I/O power supply 36 GND Ground
13 Xout O Output for oscillation 37 D12/P4 I/O
14 Xin I Input for oscillation 38 D13/P5 I/O
Data bus
15 GND Ground 39 D14/P6 I/O
16
Core VccCore power supply 40 D15/A0 I/O
17 A1 I 41/HWR//BYTEI Highlight strobe/bus width select
18 A2 I 42 /INT0 O Interrupt 0
19 A3 I
Address bus43 /RD I Read strobe
20 A4 I 44 /LWR I Low write strobe
21 A5 I 45 /CS I Chip select
22 A6 I 46 /RST I Reset signal
23 D0 I/O Data bus 47 /Dreq0 O DMA request 0
24 D1 I/O 48 /Dack0 I DMA reception signal 0
M66291GP (X2156A00) USB Controller
PNL: IC2
PNR: IC2
DM: IC7 
						

							30Tyros / TRS-MS01
PIN PIN
NO.NAME I/O FUNCTION
NO.NAME I/O FUNCTION
1 P50/A8 I/O Address bus 33 P10/ANI0 I Port1
2 P51/A9 I/O Address bus 34 AV
REFI Analog reference voltage
3 P52/A10 I/O Address bus 35 AVDDAnalog power supply
4 P53/A11 I/O Address bus 36 RESET I Reset
5 P54/A12 I/O Address bus 37 XT2 Subsystem clock
6 P55/A13 I/O Address bus 38 XT1 I Subsystem clock
7 P56/A14 I/O Address bus 39 IC I Internally connected
8 P57/A15 I/O Address bus 40 X2 Main system clock
9V
SS0 Ground 41 X1 I Main system clock
10 VDD0 Power supply 42 VSS1 Ground
11 P30 I/O Port3 43P00/INTP0I/O Port0
12 P31 I/O Port3 44P01/INTP1I/O Port0
13P32/SDA0I/O Port3 45P02/INTP2I/O Port0
14P33/SCL0I/O Port3 46P03/INTP3/ADTRGI/O Port0
15 P34/SI31 I/O Port3 47P70/TI00/TO0I/O Port7
16P35/SO31I/O Port3 48 P71/TI01 I/O Port7
17P36/SCK31I/O Port3 49P72/TI50/TO50I/O Port7
18 P20/SI30 I/O Port2 50P73/TI51/TO51I/O Port7
19P21/SO30I/O Port2 51 P74/PLC I/O Port7
20P22/SCK30I/O Port2 52 P75/BUZ I/O Port7
21P23/RXD0I/O Port2 53 P64/RD I/O Port6
22P24/TXD0I/O Port2 54 P65/WR I/O Port6
23P25/ASCK0I/O Port2 55P66/WAITI/O Port6
24 VDD1 Power supply 56P67/ASTBI/O Port6
25 AVSSAnalog ground 57 P40/AD0 I/O Port4
26P17/ANI7I Port1 58 P41/AD1 I/O Port4
27P16/ANI6I Port1 59 P42/AD2 I/O Port4
28P15/ANI5I Port1 60 P43/AD3 I/O Port4
29P14/ANI4I Port1 61 P44/AD4 I/O Port4
30P13/ANI3I Port1 62 P45/AD5 I/O Port4
31P12/ANI2I Port1 63 P46/AD6 I/O Port4
32P11/ANI1I Port1 64 P47/AD7 I/O Port4
µPD780031AYGK-XXX (X0031200) CPU
PIN PIN
NO.NAME I/O FUNCTION
NO.NAME I/O FUNCTION
1 /RST I Reset 15 MUTE I Analog output mute control
2 ZEROL O Zero flag for L-channel 16 IOUTR- O R-channel analog current output -R-
3 ZEROR O Zero flag for R-channel 17 IOUTR+ O channel analog current output +
4 LRCK I Left and right clock 18 AGND1 Analog ground
5 DATA I Serial audio data input 19 VCOM1 Internal bias de-coupling pin
6 BCK I Bit clock input 20 VCOM2 Common voltage for I/V
7 SCKI I System clock input 21 IREF Output current reference bias pin
8 DGND Digital ground 22 VCOM3 Internal bias de-coupling pin
9 VDD Digital supply, +3.3V 23 VCC1 Analog supply, +5 V
10 DEPMP0 I De-emphasis control 24 VCC2 Analog supply, +5 V
11 DEMP1 I 25 IOUTL+ O L-channel analog current output +
12 FMT0 I 26 IOUTL- O
L-channel analog current output -Ana log13 FMT1 I Audio data format select 27 AGND2 I ground
14 FMT2 I 28 VCC3 I Analog power supply, +5 V
PCM1730E-1/2K (X2077A00) DAC (Digital to Analog Converter)
PIN PIN
NO.NAME I/O FUNCTION
NO.NAME I/O FUNCTION
1 VINL I Analog input (L ch.) 13 LRCK I/O Sampling clock input/output
2 VREF1 - Reference 1 decoupling cap. 14 BCK I/O Bit clock input/output
3
REFCOM- Reference decoupling common 15 DOUT O Audio data output
4 VREF2 - Reference 2 decoupling cap. 16 SYSCK I System clock input
5 VINR I Analog input (R ch.) 17 DGND - Digital ground
6 RSTB I Reset input active “L” 18 VDD - Power supply +5V
7 BYPAS I LCF bypass control 19 CINNR - Anti-aliasing filter cap. (-) R ch.
8 FMT0 I Audio data format 0 20 CINPR - Anti-aliasing filter cap. (+) R ch.
9 FMT1 I Audio data format 1 21 CINNL - Anti-aliasing filter cap. (-) L ch.
10 MODE0 I Master/Slave mode selection 0 22 CINPL - Anti-aliasing filter cap. (+) L ch.
11 MODE1 I Master/Slave mode selection 1 23 VCC - Analog power supply
12 FSYNC I/O Frame sync. input/output 24 AGND - Analog ground
PCM1800E / 2K (XU770A00) A/D Converter
EMKS-N: IC1
DM: IC48
DM: IC46