Motorola Radio Mcs2000 Vol 1 68p81083c20 A Manual

 
Controller Section Theory of Operation 7-9  
that is approximately equal to the voltage present at the inverting input 
during the maximum current voltage drop through R5612.
PA control voltage limit consists of a portion of the control voltage fed back to 
the power control loop. PA_CNTL_LIM is produced by a voltage divider 
network on the PA board. When PA_CNTL_LIM goes above the reference 
voltage of 4.65 V plus one diode voltage drop (i.e. 0.7 V) then protection 
begins. At this point the control...

 
7-10 Controller Section Theory of Operation 
  
Figure 7-1   Clock Distribution Block Diagram 
On the controller there are 2 ICs on the SPI BUS, ASFIC (U0200-F2) and D/A 
(U0551-6). In the UHF and VHF RF sections there are 3 ICs on the SPI BUS, ZIF 
(U3201-21), Pendulum (Reference Oscillator U5800-23) and FRAC/N (U5801-
4). For the 800 and 900 MHz radios the 3 ICs on the SPI BUS are: ZIF (U6201), 
Pendulum (Reference Oscillator U6704) and FRAC/N (U6702). The SPI TX 
DATA and CLK lines going to the RF...

 
Controller Section Theory of Operation 7-11 
The timing and operation of this interface is speciÞc to the option connected, 
but generally follows the pattern 1) an option board device generates the 
interrupt, 2) main board asserts a chip for that option board device, 3) the 
main board  
m 
P generates the CLK, and 4) when data transfer is complete the 
main board terminates the chip select and CLK activity. Typical Data rate for 
the SPI BUS is 1 Megabit/sec. 
SB9600 Serial 
Interface 
(Refer to...

 
7-12 Controller Section Theory of Operation 
An option can reset the radio by driving the LH RESET line to a logic 1. This 
gets buffered by Q0409 and Q0425 and goes to the reset input of SLIC (U0104-
A8). This then causes the reset input of the  
m 
P (U0103-50) RESET to go to a 
logic 0 resulting in the  
m 
P restarting operation. 
General Purpose 
Input/Output 
(Refer to IO Buffers schematic page 10-28 for reference) 
Five general purpose I/O lines (GP I/O 2 through GP I/O 6) are provided to...

 
Controller Section Theory of Operation 7-13 
Normal 
(=Expanded) 
Microprocessor 
Operation 
In expanded mode on this radio, the  
m 
P has access to 3 external memory 
devices; U0100 (EEPROM), U0101 (SRAM) U0102 (FLASH EEPROM). In 
addition the  
m 
P has access to U0104 (SLIC). Also, within the  
m 
P there are 1 
Kbytes of internal RAM and 512 
  
bytes of internal EEPROM, as well as logic to 
select external memory devices.
The external EEPROM (U0100) as well as the  
m 
PÕs own internal EEPROM...

 
7-14 Controller Section Theory of Operation 
running, this signal is an open-drain CMOS output which goes low whenever 
the  
m 
P begins a new instruction (an instruction typically requires 2-4 external 
bus cycles, or memory fetches). However, since it is an open-drain output, the 
waveform rise assumes an exponential shape similar to an RC circuit.
There are 8 analog to digital converter ports (A/D) on U0103. They are labelled 
within the device block as PE0-PE7. These lines sense the voltage level...

Controller Section Theory of Operation 7-15 The circuitry in the SLIC is reset when either the RESET IN (U0104-A8) is a 
logic 1, or RESET* (U0104-E4) is a logic 0, or PWR RST is a logic 0. These lines 
must be in the opposite logic state for the SLIC to function normally.
The SLIC supports hardware signalling decoding for certain signalling 
standards such as MPT 1327 and Trunking (OSW). There are different versions 
of SLIC each having a different decoder. Currently there are no SLIC devices 
which...

7-16 Controller Section Theory of OperationAdditional EEPROM is contained in the mP (U0103). This EEPROM is used to 
store radio tuning and alignment data. Like the external EEPROM this 
memory can be programmed multiple times and will retain the data when 
power is removed from the radio. 
Note: the external EEPROM plus the 512 bytes of internal EEPROM in the 
68HC11F1 comprise the complete codeplug.
Static Random 
Access Memory 
(SRAM)The SRAM (U0101) contains temporary radio calculations or parameters...

Controller Section Theory of Operation 7-17
Audio and 
Signalling 
Circuits(Refer to ASFIC schematic page 10-23 for reference)
Audio Signalling 
Filter IC (ASFIC)The ASFIC has 4 functions;
1. RX/TX audio shaping, i.e. Þltering, ampliÞcation, attenuation
2. RX/TX signalling, PL/DPL/HST/MDC/MPT
3. Squelch detection
4. Microprocessor clock signal generation (see Microprocessor Clock 
Synthesizer Description Block).
The ASFIC is programmable through the SPI BUS (U0200-E3/F1/F2), normally 
receiving 21 bytes....

7-18 Controller Section Theory of Operationenabled or disabled in the ASFIC is the VOX. This circuit, along with C0205, 
provides a DC voltage that can allow the mP to detect microphone audio. The 
ASFIC can also be programmed to route the microphone audio to the speaker 
for public address operation.
External Mic PathThe external microphone signal enters the radio on accessory connector J0403 
pin 23. It is then routed to the ASFIC through resistor R0229 and capacitors 
C0223 and C0221, with DC bias...