Motorola Gp328plus Gp338plus Gp338xls Detailed 6804112j28 G Manual

							Transmitter5C-5
4.1.2 Antenna Switch
The antenna switch circuit consists of two PIN diodes (CR101 and CR102), a pi network (C107, L104 
and C106), and two current limiting resistors (R101, R170).  In the transmit mode,  B+ at PCIC (U102) 
pin 23 will go low and turn on Q111 where a B+ bias is applied to the antenna switch circuit to bias the 
diodes on.  The shunt diode (CR102) shorts out the receiver port, and the pi network, which 
operates as a quarter wave transmission line, transforms the low impedance of the shunt diode to a 
high impedance at the input of the harmonic filter.  In the receive mode, the diodes are both off, and 
hence, there exists a low attenuation path between the antenna and receiver ports.
4.1.3 Harmonic Filter
The harmonic filter consists of C104, L102, C103, L101 and C102.  The design of the harmonic filter 
for UHF is that of a modified Zolotarev design. It has been optimized for efficiency of the power 
module.  This type of filter has the advantage that it can give a greater attenuation in the stop-band for 
a given ripple level.  The harmonic filter insertion loss is typically less than 1.2dB.  
4.1.4 Antenna Matching Network
A matching network which is made up of L116 is used to match the antennas impedance to the 
harmonic filter.  This will optimize the performance of the transmitter and receiver into an antenna.
4.1.5 Power Control Integrated Circuit (PCIC)
The transmitter uses the Power Control IC (PCIC), U102 to regulate the power output of the radio. 
The current to the final stage of the power module is supplied through R101, which provides a voltage 
proportional to the current drain.   This voltage is then  fedback to the Automatic Level Control (ALC) 
within the PCIC  to regulate the output power of the transmitter.  
The PCIC has internal digital to analog converters (DACs) which provide the reference voltage of the 
control loop.  The reference voltage level is programmable through the SPI line of the PCIC.
There are resistors and integrators within the PCIC, and external capacitors (C133, C134 and C135)  
in controlling the transmitter rising and falling time.  These are necessary in reducing the power 
splatter into adjacent channels.
CR105 and its associated components are part of the temperature cut back circuitry.  It senses the 
printed circuit board temperature around the transmitter circuits and output a DC voltage to the PCIC. 
If the DC voltage produced exceeds the set threshold in the PCIC, the transmitter output power will be 
reduced so as to reduce the transmitter temperature. 
						

							5C-6Receiver
5.0 Receiver
5.1 Receiver Front-End
(Refer to UHF Band 2 Receiver Front End Schematic Diagram on page 5C-22 and UHF Band 2 
Transmitter Schematic Diagram on page 5C-26)
The RF signal is received by the antenna and applied to a low-pass filter. For UHF, the filter consists 
of L101, L102, C102, C103, C104. The filtered RF signal is passed through the antenna switch. The 
antenna switch circuit consists of two PIN diodes(CR101 and CR102) and a pi network (C106, L104 
and C107).The signal is then applied to a varactor tuned bandpass filter. The UHF bandpass filter  
comprises of L301, L302, C302, C303, C304, CR301 and CR302. The bandpass filter is tuned by 
applying a control voltage to the varactor diodes(CR301 and CR302) in the filter.
The bandpass filter is electronically tuned by the DACRx from IC404 which is controlled by the 
microprocessor. Depending on the carrier frequency, the DACRx will supply the tuned voltage to the 
varactor diodes in the filter. Wideband operation of the filter is achieved by shifting the bandpass filter 
across the band.
The output of the bandpass filter is coupled to the RF amplifier transistor Q301 via C307. After being 
amplified by the RF amplifier, the RF signal is further filtered by a second varactor tuned bandpass 
filter, consisting of  L306, L307, C313, C317, CR304 and  CR305. 
Both the pre and post-RF amplifier varactor tuned filters have similar responses. The 3 dB bandwidth 
of the filter is about 50 MHz. This enables the filters to be electronically controlled by using a single 
control voltage which is DACRx .
Figure 5-2: UHF Receiver Block Diagram
Demodulator
Synthesizer
Crystal 
Filter Mixer Varactor 
Tuned Filter RF Amp Va r a c t o r  
Tuned Filter Pin Diode 
Antenna 
Switch
RF Jack Antenna
AGC
Control Voltage
from  ASFICFirst LO
from FGU
Recovered Audio
Squelch
RSSI
IFIC
SPI Bus 16.8 MHz
Reference Clock
Second
LO VCO U301IF Amp 
						

							Receiver5C-7
The output of the post-RF amplifier filter which is connected to the passive double balanced mixer 
consists of T301, T302 and CR306. Matching of the filter to the mixer is provided by C381. After 
mixing with the first LO signal from the voltage controlled oscillator (VCO) using low side injection, the 
RF signal is down-converted to the 45.1 MHz IF signal. 
The IF signal coming out of the mixer is transfered to the crystal filter (FL301) through a resistor pad 
and a diplexer (C322 and L310). Matching to the input of the crystal filter is provided by C324 and 
L311. The crystal filter provides the necessary selectivity and intermodulation protection. 
5.2 Receiver Back-End
(Refer to UHF Band 2 Receiver Back End Schematic Diagram on page 5C-23)
The output of crystal filter FL301 is matched to the input of IF amplifier transistor Q302 by 
components R352 and C325. Voltage supply to the IF amplifier is taken from the receive 5 volts (R5). 
The IF amplifer provides a gain of about 7dB.  The amplified IF signal is then coupled into U301(pin 3) 
via C330, C338 and L330 which provides the matching for the IF amplifier and U301.
The IF signal applied to pin 3 of U301 is amplified, down-converted, filtered, and demodulated, to 
produce the recovered audio at pin 27 of U301. This IF IC is electronically programmable, and the 
amount of filtering (which is dependent on the radio channel spacing) is controlled by the 
microprocessor. Additional filtering, once externally provided by the conventional ceramic filters, is 
replaced by internal filters in the IF module (U301). 
The IF IC uses a type of direct conversion process, whereby the externally generated second LO 
frequency is divided by two in U301 so that it is very close to the first IF frequency. The IF IC (U301) 
synthesizes the second LO  and phase-locks the VCO to track the first IF frequency. The second LO 
is designed to oscillate at twice the first IF frequency because of the divide-by-two function in the IF 
IC.
In the absence of an IF signal, the VCO will “search” for a frequency, or its frequency will vary close to 
twice the IF frequency. When an IF signal is received, the VCO will lock onto the IF signal. The 
second LO/VCO is a Colpitts oscillator built around transistor Q320. The VCO has a varactor diode, 
CR310, to adjust the VCO frequency. The control signal for the varactor is derived from a loop filter 
consisting of C362, C363, C364, R320 and R321.
The IF IC (U301) also performs several other functions. It provides a received signal-strength 
indicator (RSSI) and a squelch output. The RSSI is a dc voltage monitored by the microprocessor, 
and used as a peak indicator during the bench tuning of the receiver front-end varactor filter. The 
RSSI voltage is also used to control the automatic gain control (AGC) circuit at the front-end. 
The demodulated signal on pin 27 of U301 is also used for squelch control. The signal is routed to 
U404 (ASFIC) where squelch signal shaping and detection takes place. The demodulated audio 
signal is also routed to U404 for processing before going to the audio amplifier for amplification.  
						

							5C-8Receiver
5.3 Automatic Gain Control Circuit
(Refer to UHF Band 2 Receiver Front End Schematic Diagram on page 5C-22)
The front end automatic gain control circuit  is to provide automatic gain reduction of the front end RF 
amplifier via feedback. This action is necessary to prevent overloading of back end circuits. This is 
achieved by drawing some of the output power from the RF amplifier’s output. At high radio 
frequencies, capacitor C331 provides the low impedance path to ground for this purpose. CR308 is a 
PIN diode used for switching the path on or off. A certain amount of forward biasing current is needed 
to turn the PIN diode on. Transistors Q315 provides this current where upon saturation, current will 
flow via R347, PIN diode, collector and emitter of Q315 and R319 before going to ground. Q315 is an 
NPN transistor used for switching here. Maximum current flowing through the PIN is mainly limited by 
the resistor R319. 
Radio signal strength indicator, RSSI,  a voltage signal, is used to drive Q315 to saturation hence  
turning it on. RSSI is produced by U301 and is proportional to the gain of the RF amplifier and the 
input RF signal power to the radio. 
Resistor network at the input to the base of Q315 is scaled to turn on Q315, hence activating the 
AGC, at certain RSSI levels. In order to turn on Q315, the voltage across the transistor’s base to 
ground must be greater or equal to the voltage across R319, plus the base-emitter voltage (Vbe) 
present at Q315. The resistor network with thermistor RT300 is capable of providing temperature 
compensation to the AGC circuit, as RSSI generated by U301 is lower at cold temperatures 
compared to normal operation at room temperature. Resistor R300 and capacitor C397 form an R-C 
network used to dampen any transient instability while the AGC is turning on. 
						

							Frequency Generation Circuitry5C-9
6.0 Frequency Generation Circuitry
The Frequency Generation Circuitry is composed of two main ICs, the Fractional-N synthesizer 
(U201), and the VCO/Buffer IC (U241). Designed in conjunction to maximize  compatibility, the two 
ICs provide many of the functions that normally would require additional circuitry. The synthesizer  
block diagram illustrates the interconnect and support circuitry used in the region. Refer to the 
relevant schematics for the reference designators.
The synthesizer is powered by regulated 5V and 3.3V which come from U247 and U248 respectively. 
The synthesizer in turn generates a superfiltered 4.5V which powers U241.
In addition to the VCO, the synthesizer must interface with the logic and ASFIC circuitry. 
Programming for the synthesizer is accomplished through the data , clock and chip select lines from 
the microprocessor. A 3.3V dc signal from synthesizer lock detect line indicates to the microprocessor 
that the synthesizer is locked.
Transmit modulation from the ASFIC is supplied to pin10 of U201. Internally the audio is digitized by 
the Fractional-N and applied to the loop divider to provide the low-port modulation. The audio runs 
through an internal attenuator for modulation balancing purposes before going out to the VCO.
Figure 5-3: Frequency Generation Unit Block Diagram
Vo l t a g e  
Multiplier
Synthesizer 
U201
Dual 
Tran-
sistor
Loop 
Filter
VCOBIC 
U241Low 
Pass 
Filter
Matching 
Network
Attenuator
To
Mixer
To
PA  D r i v e rVCP
Vmult1Aux3
Aux4
MOD Out
Modulating
Signal Vmult2Rx VCO Circuit
Tx VCO CircuitTRB
16.8 MHz
Ref. Osc.Rx Out
Tx Out 
						

							5C-10Frequency Generation Circuitry
6.1 Synthesizer
(Refer to UHF Band 2 Synthesizer Schematic Diagram on page 5C-24)
The Fractional-N Synthesizer uses a 16.8MHz crystal (FL201) to provide a reference  for the system. 
The LVFractN IC (U201) further divides this to 2.1MHz, 2.225MHz, and 2.4MHz as reference 
frequencies. Together with C206, C207, C208, R204 and CR203 , they build up the  reference 
oscillator which is capable of 2.5ppm stability over temperatures of -30 to 85°C. It also provides 
16.8MHz at pin 19 of U201 to be used by ASFIC and LVZIF. 
The loop filter which consist of  C231, C232, C233, R231, R232 and R233 provides the necessary dc 
steering voltage for the VCO and determines the amount of noise and  spur passing through .
In achieving fast locking for the synthesizer, an internal adapt charge pump provides higher current at 
pin 45 of U201 to put synthesizer within the lock range. The required frequency is then locked by 
normal mode charge pump at pin 43 .
Both the normal and adapt charge pumps get their supply from the capacitive voltage multiplier which 
is made up of C258, C259, C228, triple diode CR201 and level shifters U210 and U211. Two 3.3V 
square waves ( 180 deg out of phase) are first shifted to 5V,  then along with regulated 5V , put 
through arrays of diodes and capacitors to build up 13.3V at pin 47 of U201.
Figure 5-4: Synthesizer Block Diagram
DATA
CLK
CEX
MODIN
V
CC, DC5V
XTAL1
XTAL2
WARP
PREIN
VCP
REFERENCE
OSCILLATOR
 VOLTAGE
MULTIPLIER
  VOLTAGE
CONTROLLED
 OSCILLATOR
2-POLE
LOOP
FILTER
DATA (U409 PIN 100)
CLOCK (U409 PIN 1)
CSX (U409 PIN 2)
MOD IN (U404 PIN 40)
+5V (U247 PIN 4)7
8
9
10
13, 30
23
24
25
32
47
VMULT2 VMULT1BIAS1 SFOUTAUX3
AUX4 IADAPTIOUTGND FREFOUTLOCK4
19
6, 22, 23, 24
43
45
3
2
28
14
1540FILTERED 5VSTEERING
LINE LOCK (U409 PIN 56)
PRESCALER INLO RF INJECTION
TX RF INJECTION
(1ST STAGE OF PA) FREF (U201 PIN 21 & U404 PIN 34)
39 BIAS2
41
DUAL 
TRANSIS
DUAL 
TRANSIS-48
5VR5 5, 20, 34, 36
(U248 PIN 5)
AUX1 V
DD, 3.3VMODOUT          U251 
LOW VOLTAGE 
FRACTIONAL-N 
 SYNTHESIZER
TORSTORS 
						

							Frequency Generation Circuitry5C-11
6.2 VCO - Voltage Controlled Oscillator
(Refer to UHF Band 2 Voltage Controlled Oscillator Schematic Diagram on page 5C-25)
Figure 5-5: VCO Block Diagram
 The VCOBIC (U241) in conjunction with the Fractional-N synthesizer (U201) generates RF in both 
the receive and the transmit modes of operation. The TRB line (U241 pin 19) determines which 
oscillator and buffer will be enabled. A  sample of the RF signal from the enabled oscillator is routed  
from U241 pin 12, through a low pass filter, to the prescaler input (U201 pin 32). After frequency 
comparison in the synthesizer, a resultant CONTROL  VOLTAGE is received at the VCO. This voltage 
is a DC voltage between 3.5V and 9.5V when the PLL is locked on frequency.
 
Presc
RX
TXMatching
NetworkLow Pass
    Filter
Attenuator Pin8
Pin14
Pin10 Level Shifter
   Network5V
(U201 Pin28)
VCC Buffers
TX RF Injection U201 Pin 32AUX4 (U201 Pin3)AUX3 (U201 Pin2)
Prescaler Out
Pin 12 Pin 19 Pin 20
      TX/RX/BS
Switching Network
U241
VCOBIC
       Rx
Active Bias
      Tx
Active Bias
Pin2
Rx-I adjustPin1
Tx-I adjustPins 9,11,17
Pin18Vsens
Circuit Pin15Pin16 RX VCO
 Circuit
TX VCO
 Circuit RX Tank
TX TankPin7
Vcc-Superfilter
Collector/RF in
Pin4
Pin5
Pin6
RX
TX
(U201 Pin28)Rx-SW
Tx-SW
Vcc-Logic
(U201 Pin28) Steer Line 
Voltage 
(VCTRL)Pin13
Pin3TRB_IN
LO RF INJECTION
VSFVSF VSF 
						

							5C-12Frequency Generation Circuitry
The VCOBIC(U241) is operated at 4.54 V (VSF) and Fractional-N synthesizer (U201) at 3.3V. This 
difference in operating voltage requires a level shifter consisting of Q260 and Q261 on the TRB line. 
The operation logic is shown in Table 5-1.
In the receive mode, U241 pin 19 is low or grounded. This activates the receive VCO by enabling the 
receive oscillator and the receive buffer of U241. The RF signal at U241 pin 8 is run through a 
matching network. The resulting RF signal  is the LO RF INJECTION and it is applied to the mixer at 
T302 (refer to 
UHF Band 2 Receiver Front End Schematic Diagram on page 5C-22).
During the transmit condition, when PTT is depressed, five volts is applied to U241 pin 19. This 
activates the transmit VCO by enabling the transmit oscillator and the transmit buffer of U241. The RF 
signal at U241 pin 10 is injected into the input of the PA module (U101 pin16). This RF signal is the 
TX RF INJECTION. Also in transmit mode, the audio signal to be frequency modulated onto the 
carrier is received through the U201 pin 41.
When a high impedance is applied to U241 pin19, the VCO is operating in BATTERY SAVER mode. 
In this case, both the receive and transmit oscillators as well as the receive transmit and prescaler 
buffer are turned off.
Table 5-1: Level Shifter Logic
Desired 
ModeAUX 4AUX 3TRB
TxLowHigh (@3.2V)High (@4.8V)
RxHighLowLow
Battery SaverLowLowHi-Z/Float (@2.5V) 
						

							Notes For All Schematics and Circuit Boards 5C-13
7.0 Notes For All Schematics and Circuit Boards
* Component is frequency sensitive. Refer to the Electrical Parts List for value and usage.
1.Unless otherwise stated, resistances are in Ohms (k = 1000), and capacitances are in picofarads 
(pF) or microfarads (µF).
2.DC voltages are measured from point indicated to chassis ground using a Motorola DC multime-
ter or equivalent. Transmitter measurements should be made with a 1.2 µH choke in series with 
the voltage probe to prevent circuit loading.
3.Reference Designators are assigned in the following manner:
100 Series = Transmitter
200 Series = Frequency Generation
300 Series  = Receiver
400/500 Series = Controller
600 Series = Keypad Board
4.Interconnect Tie Point Legend:
UNSWB+ = Unswitch Battery Voltage (7.5V)
SWB+ = Switch Battery Voltage (7.5V)
R5 = Receiver Five Volts
CLK = Clock
Vdda = Regulated 3.3 Volts (for analog)
Vddd = Regulated 3.3 Volts (for digital)
CSX = Chip Select Line (not for LVZIF)
SYN = Synthesizer
DACRX = Digital to Analog Voltage (For Receiver Front End Filter)
VSF = Voltage Super Filtered (5 volts)
VR = Voltage Regulator
6-LAYER CIRCUIT BOARD DETAIL VIEWING 
COPPER STEPS IN PROPER LAYER SEQUENCE
LAYER 1 (L1)
LAYER 2 (L2)
LAYER 3 (L3)
LAYER 4 (L4)
LAYER 5 (L5)
LAYER 6 (L6)
INNER LAYERS SIDE 1
SIDE 2 
						

							5C-14 Notes For All Schematics and Circuit Boards
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