Motorola Gp328 Gp338 Detailed 6804110j64 F Manual
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3-1Section 3 POWER UP SELF-TEST1.0 Error CodesTurning on the radio using the on/off volume control starts a self-test routine which checks the RAM, ROM checksum, EEPROM hardware and EEPROM checksum. If these checks are successfully completed, the radio will generate the Self-Test Pass Tone. If the self-test is not successful, a “bonk” is heard. Radios with displays are able to display these error messages:•“RAM TST ERROR” for •“ROM CS ERROR” for •“EEPRM HW ERROR” for •“EEPRM CS ERROR” for NOTERadio without display emits only “bonk” (300 Hz) tone if it fails the self-test.Error Code Explanation Corrective Action“RAM TST ERROR”RAM Test FailureRetest radio by turning it off and turning it on again. If message reoccurs, replace RAM (U405). “ROM CS ERROR” ROM Checksum is wrong.Reprogram FLASH Memory, then retest. If message reoccurs, replace ROM (U406).“EEPRM HW ERROR”Codeplug structure mismatch, non existence of codeplug.Reprogram codeplug with correct version and retest radio. If message reoccurs, replace EEPROM (U407). “EEPRM CS ERROR” Codeplug check- sum is wrong.Reprogram codeplug.No DisplayDisplay module is not connected properly. Display module is damaged.Check connection between main board and display module. Replace with new display module.
4-1Section 4 CONTROLLER INFORMATION1.0 OverviewThis section provides a detailed theory of operation for the radio and its components.2.0 Radio Power DistributionFigure 4-1 illustrates the DC distribution throughout the radio board. A 7.5V battery (BATT 7.5V) supplies power directly to the electronic on/off control as UNSWB+. When the radio is turned on, MECH_SWB+ (on/off/volume control) will trigger the electronic on/off control(momentary-on path), then SWB+ is distributed as shown in Figure 4-1. Vdda from 3.3V Vdda regulator will then supply the microprocessor. Data is then sent to ASFIC_CMP to turn on GCB4(DAC). GCB4 will take over the momentary-on path within 12ms. SWB+ will continue to support the whole board until the radio is turned off. Radio will be turned-off on two conditions; 1.MECH_SWB+ turned off 2.Low batteryFigure 4-1: DC Power Distribution Block DiagramControl On/Off SwitchSWB+FuseLow Battery DetectAnt. SW PCIC(ALC)PA , D r i v e r LI Ion3.5V Reg.7.5VAudio PA 4.0V/3.3V Vddd Reg. 5VASFIC_CMPVCOBIC FRACTNLV Z I FLCD Driver5V RF. AMP, IF AMP Ext. RX.MECH. SWB+ UNSWB+TX.Vdda Reg.Int/Ext VddR1 R5 R2R3VddaAccessories 20 pin Connector Keypad/Option Board Prime Expansion Board Switching Reg. R4 Vddd Battery Reg.MCU Micro P, ROM &EEPROMBuffer (NU) LedJumpersDual Vdd Regulator SchemeSingle Vdd Regulator Scheme R1 Y Y R2 N N R3 N Y R4 N N R5 Y N Vdda Y N SW. Reg. N N
4-2Controller BoardWhen low battery level is detected by the microprocessor through both conditions above, it will store the radio personality data to EEPROM before turning off.3.0 Controller Board3.1 GeneralThe controller board is the central interface between the various subsytems of the radio. It is separated into digital and audio architectures. The digital portion consists of a special Motorola microcontroller (HC11FL0). The audio power amplifier (Audio PA) and audio/signalling/filter/ companding IC (ASFIC_CMP) form the backbone of the audio/signalling architecture.Figure 4-2: Controller Block DiagramExternal Microphone Internal Microphone External Speaker Internal Speaker SCI to Side Connector Audio PAAudio/Signalling ArchitectureTo Synthesizer Mod Out 16.8 MHz Reference Clock from Synthesizer Recovered Audio Squelch To RF BoardSPIDigital ArchitecturemPClock 3.3V Regulator (Vddd)RAM EEPROM ROMHC11FL0 ASFIC_CMP3.3V Regulator (Vdda)
Controller Board4-33.2 Digital ArchitectureMCU configuration There is one common MCU architecture for low-tier as well as for the high-tier products. It covers the Conventional and Trunking portables. An open architecture system with the new HC11FL0 as the processor is used. Combinations of different size RAM, ROM and EEPROM are available for various application software. REAL TIME CLOCK (RTC) This radio supports Real Time Clock (RTC) module for purposes of Message Time Stamping and Time Keeping. The RTC module resides in the micro-processor HC11FL0. It is kept alive by a back- up Lithium Ion battery when the primary battery is removed. Circuit Description The RTC module which resides in the HC11FL0 is powered by the ModB/Vstby pin and PI6/PI7 form the crystal oscillator circuit. Clock frequency of 38.4kHz from a crystal oscillator provides the reference signal. In the processor, the frequency is divided down to 1Hz. As the RTC module is powered separately from the processor Vdd, the RTC is kept alive through the ModB / Vstby pin when the radio is switched off. A small button Lithium Ion battery continues to feed the RTC when the primary battery is removed. A MOSFET Q416 switches in the LiO supply when Vdd is removed. Q416 also provides isolation from BOOT_CTRL function in the event of radio program flashing. A small 3.3V regulator is used to charge the LiO battery.Figure 4-3: RTC CircuitLI_ION R462R419 3 4 215CR411 12 3Q416C434 U410 3.3V 3 2 1VINVOUT VSSUNSWB+ R460 C435 R461VdddHC11FL0MODA MODB R420 R426FL401C436 C437 PI6 PI7OUT IN GND 38.4kHzUNSWB+SWB+ 6 4 1 3 23 51 2 4CR413 R463 300 Q417 TEST_POINT TP405 1BOOT_CTRL
4-4Controller BoardModB/Vstby Supply Under various conditions, the supply to the ModB/Vstby would vary. Table 4-1 shows these conditions and circuits in operation.Table 4-1: ModB/Vstby Supply ModesCondition Circuit OperationRadio OnVdd supply voltage via CR411 Radio Off • Vdd turned off • Q416 gate is pulled low by R462 • Q416 is switched on • U410 supplies 3.2V to ModB/VstbyPrimary battery removed• Vdd turned off • Q416 gate is pulled low by R462 • Q416 is switched on • LiO battery provides 3.2V to ModB/Vstby Flash Mode • Boot_Ctrl line pull low • ModA & ModB goes low • Processor in boot-strap mode • Flashing enabled
4-5 3.3 Controller Schematics (330-400MHz for 8485726Z01, 403-470MHz for 8480450Z03 & 450-527MHz for 8485641Z02) INTERFACE RESET RX_AUD_RTN R_W SWB+ TX_AUD_RTN TX_AUD_SND URX_SND VS_AUDSELVS_CS VS_GAINSELVS_INT VS_RACVddd D6 D7 DATA EXT_MIC FLAT_RX_SND FLAT_TX_RTN INT_EXT_Vdd KEYPAD_COL KEYPAD_ROW KEY_INT LCD_SELLEDBL MISO OFF_BATT_DATA_OUTOPT_ENA PTT RDY A0 CLKD0 D1 D2 D3 D4 D5Vddd FLAT_TX_RTN VS_GAINSEL DATA OFF_BATT_DATA_OUT MISO VS_RAC CLK EXT_MIC LCD_SEL R_W SWB+ VS_AUDSEL VS_CS FLAT_RX_SND TX_AUD_SND OPT_ENA RX_AUD_RTN TX_AUD_RTN RDY KEYPAD_ROW URX_SND INT_EXT_Vdd KEYPAD_COL KEY_INT RESET PTT VS_INT LEDBL ON A17A2 A3 A4 A5 A6 A7 A8 A9 A0 A1 A10 A11 A12 A13 A14 A15 A16 D7 D0 D1 D2 D3 D4 D5 D6 FLASH_EN FLASH_OE RAM_CS R_W Vddd XA18MEMORY Vddd FLASH_OE RAM_CS FLASH_EN R_W XA18 LVZIF_SEL VS_CS LCD_SELVS_CS Vddd XA18 RAM_CS R_W FLASH_EN FLASH_OE LCD_SEL LVZIF_SEL A9 D0 D1 D2 D3 D4 D5 D6 D7 A1 A10 A11 A12 A13 A14 A15 A16 A17 A2 A3 A4 A5 A6 A7 A8 A0 SQ_DET SWB+SYN UNSWB+VOX RESETF1200HSIOLSIO MISO BATT_DATA_IN CHACTCLK CSX DATA EE_CS SCI_RXSCI_TX VOL VS_RAC OPT_ENA OPT_SEL1 OPT_SEL2RDY RSSI RTA0 RTA1 RTA2 RTA3 SB1 SB2 SB3 KEYPAD_COL KEYPAD_ROWLI_ION MECH_SWB+ OFF_BATT_DATA_OUTBOOT_CTRL VS_INT PTT EMER KEY_INT LOCK KEY_INT PTT EMER VS_INT LOCK RTA3 SB3 SB2 OFF_BATT_DATA_OUT VOL MECH_SWB+ VS_RAC KEYPAD_COL KEYPAD_ROW OPT_ENA RDY LI_ION RTA1 RTA0 RTA2 SB1 MICRO_P 5V Vdda RESET BATT_CODE LI_IONLOCK 4V_3.3VCSX MODIN DATA CLK UNSWB+ DEMOD RSSI 16.8MHzRTA2 RTA3 MECH_SWB+ VOL PTT LVZIF_SEL SWB+ DACRx RED_LED GREEN_LED SB1 SB2 SB3 EMER RTA0 RTA1 IF_Vdda_CTRL IF_LVZIF_SEL_CTRL IF_16.8MHz_CTRL IF_EMER_CTRL IF_CSX_CTRL IF_LI_ION_CTRL IF_SB3_CTRL IF_RESET_CTRL IF_DATA_CTRL IF_5V_CTRL IF_BATT_CODE_CTRL IF_SWB+_CTRL IF_GREEN_LED_CTRL IF_SB2_CTRL IF_VOL_CTRL IF_4V_3.3V_CTRL IF_CLK_CTRL IF_UNSWB+_CTRL IF_LOCK_CTRL IF_PTT_CTRL IF_MECHSWB+_CTRL IF_RTA1_CTRL IF_RED_LED_CTRL IF_RTA3_CTRL IF_MODIN_CTRL IF_DACRX_CTRL IF_RTA2_CTRL IF_SB1_CTRL IF_RTA0_CTRL IF_DEMOD_CTRL IF_RSSI_CTRL 16.8MHz 5V Vdda RESET BATT_CODE LI_ION LOCK 4V_3.3V DACRx CSX MODIN DATA CLK UNSWB+ DEMOD RSSI RTA2 RTA3 MECH_SWB+ VOL PTT LVZIF_SEL SWB+ RED_LED GREEN_LED SB1 SB2 SB3 EMER RTA0 RTA1 TO/FROM RF C432 NUNU R403 Vdda Vddd SWB+ RESET UNSWB+ MISO DATA CSXCLK VS_AUDSEL VS_GAINSELVddd DEMOD DACRX 4V_3.3V VS_AUDSEL VS_GAINSEL Vdda Vddd LSIO MECH_SWB+ MISO MODIN OFF_BATT_DATA_OUT RED_LED RESETRX_AUD_RTN SQ_DET SWB+ SYNTX_AUD_RTN TX_AUD_SND UNSWB+URX_SND VOX CLK CSX DACRX DATA DEMOD EE_CS EXT_MIC EXT_SPKR_SEL F1200 FLAT_RX_SND FLAT_TX_RTN GREEN_LED HSIO INT_EXT_Vdd INT_MIC LEDBL 16.8MHz 4V_3.3V 5V AUDIO AUDIO_PA_ENA BATT_CODE BATT_DATA_IN CHACT16.8MHz RED_LED RX_AUD_RTN TX_AUD_RTN TX_AUD_SND URX_SND OFF_BATT_DATA_OUT MODIN MECH_SWB+ LEDBL INT_EXT_Vdd GREEN_LED FLAT_TX_RTN BATT_CODE ASFIC Vdda FLAT_RX_SND EXT_MIC 5V RSSIBOOT_CTRL OPT_SEL1 OPT_SEL2 RSSI SCI_RX SCI_TX AUDIO_PA_ENA EXT_MIC EXT_SPKR_SELFLAT_RX_SND INT_MICSWB+ UNSWB+ Vdda 5V AUDIOAUDIO_PA MEMORY SHIELDSH400 SHIELD 1 ON/OFF SHIELDSH401 SHIELD 1 MICROPIC SHIELDSH402 SHIELD 1 ASFIC/AUDIO PA SHIELD1 SH403 SHIELD Complete Controller Schematic Diagram http://www.myradio168.name
4-6 0.1uF C428 1 2 4 3 6 7 5U407 X25320_2.7V MISO 8 WPCLK CS HOLD SISO VCC VSS4K x 8 BIT EEPROM 100pF C427 R429 10K EE_CS5V R413 0 47K R400C422 0.1uF 0.1uF C421Vdda .01uFC420 SQDET GNDSYN HSIO LCAP LSIO GCB0 GCB1 GCB2 CLK CSX DATA CHACT17 23 19 24 18 15 14 13 21 20 22 16 VOX UIO VDDA VDDDAC PLCAP SQIN GNDA DACG DACR DACU DISC AGCCAP7 101 118 9 3 6 5 4 2 12U404 09Z41 VDDSYNTXRTN VDDCPVDDD NC PLCAP2SYN GNDD GNDD0 F1200GCB3 CLK168 VDDRC TXSND URXOUTMICINT MOD GNDRC MICEXT GCB4 GCB5 AUDIO AUXRX AUXTX45 44 39 46 40 47 48 37 38 41 43 42TX_AUD_SND MODIN AUDIO FLAT_TX_RTN LEDBL 270K R448 220K R446 C480 10uF R447 1.5MEG MECH_SWB+CR440 12 339K R416 13 2Q403Q405 24 13 C402 0.1uF C403 10uF3 12 Q400 75K R406UNSWB+ 2.7K R427 5 3 1 2 4 CR412 BATT_CODE Vddd 27 36 32 33 26 25 28 31 30 29 35 34 C416 0.1uFSYN F1200 TX_AUD_RTN 16.8MHzRED_LED C419 NU DATACLK CSX CHACT SQ_DET LSIO HSIO EXT_SPKR_SELAUDIO_PA_ENAGREEN_LED VdddBATT_DATA_IN OFF_BATT_DATA_OUT R476 24K OUTPUT SENSE SHUTDOWN VTAP ERROR FEEDBACKGND INPUTLP2951ACMM-3.3 U400 4 1 2 6 5 3 7 8C400 .01uF 4V_3.3V NU R402 0 R405 SWB+ Vddd INT_MIC EXT_MIC 68K R407 TP406 1 C401 0.1uF 0 R401 INT_EXT_Vdd 0.1uFC410 TP410 1C408 100pF 0.1uF C409 0 R475 Vdda RESET C411 0.1uF DEMOD 24K R449C479 30K 0.1uF R425 0.1uFC407 R445 24K Vdda URX_SND RX_AUD_RTN VOX VS_AUDSEL VS_GAINSELDACRx FLAT_RX_SNDC430 0.1uF .01uF C415 4.7uF C452 0.1uF C414 C451 .022uF Controller ASFIC/ON_OFF Schematic Diagram http://www.myradio168.name
4-7 PH1_PW2 PH2_PW3 PH3_PW4 PH4_CSIO PH5_CSGP1 PH6_CSGP2 PH7_CSPROG PG1_XA14 PG2_XA15 PG3_XA16 PG4_XA17 PG5_XA18 PG6_AS PH0_PW1 PG0_XA13 PC0_DATA0 PC1_DATA1 PC2_DATA2 PC3_DATA3 PC4_DATA4 PC5_DATA5 PC6_DATA6 PC7_DATA7 VSSR VSS VSSL PI1 PI2 PI3 PI4 PI5 PI6 PI7 PI0 PF2_ADDR2 PF3_ADDR3 PF4_ADDR4 PF5_ADDR5 PF6_ADDR6 PF7_ADDR7 PFO_ADDR0 PF1_ADDR1 PB1_ADDR9 PB2_ADDR10 PB3_ADDR11 PB4_ADDR12 PB5_ADDR13 PB6_ADDR14 PB7_ADDR15 PBO_ADDR8 AVSSXIRQ PJ1_CSGP4 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 RESET PJ0_CSGP3PG7_R_W PE1_AN1 PE2_AN2 PE3_AN3 PE4_AN4 PE5_AN5 PE6_AN6 PE7_AN7 PE0_AN0ECLK IRQ MODA_LIR MODB_VSTBY XFC XTAL VDD VDDL VDDR VDDSYNVRHVRL PD0_RXDPD1_TXD PD2_MISO PD3_MOSIPD4_SCKPD5_SS PD6_LVIN PA0_IC3 PA1_IC2 PA2_IC1 PA3_IC4_OC5_OC1PA4_OC4_OC1 PA5_OC3_OC1 PA6_OC2_OC1PA7_PA1_OC1 AVDD EXTAL LVOUT MC68HC11FL0U409 48 94 4 89 96 58 57 VST 72 73 74 75 76 77 78 71 CSGP3 CSGP4 66 65 64 63 62 61 60 67 87 13 40 55 54 53 52 51 50 49 56 70 10 119 21 158 7 14 27 26 25 24 23 22 29 28 30 31 32 33 34 35 36 37 46 45 44 43 42 41 38 47 16 20 19 17 18 5 6 97 98 99 100 12 3 79 80 81 82 83 84 85 86 93 91 12 92 69 68 90 95 39 88 59 C431 100pF100pFC449 C453 100pFC423 100pF R411 10K 100pFC456 KEY_INT RESET R_W RTA0 RTA2 RTA3 SB1 SB2 SB3 OFF_BATT_DATA_OUT RTA1 VS_RAC VOL RSSI VOX KEYPAD_COL KEYPAD_ROWEMER OPT_SEL1 OPT_ENA LOCK VS_INT PTT C436 22pF GNDIN OUT 2 1 3FL401 XTAL 22pF C437 330K R426 R420 10MEG A4 A3 A2 A1 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A0 D7 D0 D1 D2 D3 D4 D5 D6 LVZIF_SEL LCD_SELVS_CS RAM_CS FLASH_ENXA18 BATT_DATA_INCLK CSX EE_CS OPT_SEL2 390nHL410390nHL411 R437 NU HSIO DATA FLASH_OE SYN RDY LSIO SQ_DET CHACT MISOR418 0 11 TP402 TEST_POINT TP401 TEST_POINT SCI_RX SCI_TXF1200 Vddd10K R409 R457 10K Vddd Vddd LOW BATT 91K R415 1%180K R414 1% .01uFC433TP415 TEST_POINT 1 VdddMech_SWB+RT400 33.0K 51K R432 UNSWB+ SWB+ 6 4 1 3 23 51 2 4CR413 R463 300 Q417 TEST_POINT TP405 1 BOOT_CTRL LI_ION 510 R419 10K R4625 3 1 24 1 2 3 Q416CR411 C435 0.1uF 4.7K 180 R461 R4600.1uFC434 2 1 VSS VIN VOUT3 ILC7062CM-33U410 3.3V UNSWB+ Vddd Controller Micro Processor Schematic Diagram http://www.myradio168.name
4-82 6 18 17 16 15 14 13 3 19 31 1 12 4 5 11 10 20 A11 A10A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A14 A17 A16 A15 A13 A12A9 A17 A2 A3 A4 A5 A6 A7 A8 A1 A10 A11 A12 A13 A14 A15 A16 A0 D7 NCD0 D1 D2 D3 D4 D5 D6 FLASH ROM24 GNDXA18D0 D1 D2 D3 D4 D5 D6 D7 29 9 21 22 23 25 26 27 28 EN_CE EN_OE EN_WE VCCFLASH_ENU406 AT49BV020 8 30 32 7 0 R492NU R408XA18C429 0.1uF 100K R410FLASH_OE2.2 R428 C424 10uF VSS14 WE OE CS 27 22 20D0 D1 D2 D3 D4 D5 D6 D7 D2 D3 D4 D5 D6 D7 D8 D1RAM12 13 15 16 17 18 19 11 A4 A5 A6 A7 A8 A9 A1 A10 A11 A12 A13 A14 A2 A3 A0 VDD28U405 SRM2B256 6 5 4 3 25 249 21 23 2 26 1 8 7 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14RAM_CSC425 0.1uF 100pFC426VdddR478 10KVddd R_W Controller Memory Schematic Diagram