Motorola Gm1200e Detailled 68p64115b15 Manual

 
Introduction
Introduction/Theory of Operation3.1-1
 
1.0 Introduction 
This section provides a detailed theory of operation for the radio and its components. The main radio 
is a single board design, consisting of the transmitter, receiver, and controller circuits. 
The main board is designed to accept one additional option board. This may provide functions such 
as secure voice/data or DTMF decoder. The control head is mounted directly on the front of the 
radio or connected via an extension cable in...

 
Open Controller
3.1-2Introduction/Theory of Operation
 
Regulator U0601 is used to generate the 9.3 volts required by some audio circuits, the RF circuitry 
and power control circuitry. Input and output capacitors (C0601-C0603 and C0604/C0605) are used 
to reduce high frequency noise. R0602/R0603 set the output voltage of the regulator. If the voltage 
at pin 1 is greater than 1.3 volts the regulator output decreases and if the voltage is less than 1.3 
volts the regulator output increases. This...

 
Open Controller
Introduction/Theory of Operation3.1-3
 
While EMERGENCY CONTROL is low, SW B+ is on, the microprocessor starts execution, reads 
that the emergency input is active through the voltage level of EMER IGN SENSE, and sets the B+ 
CONTROL output of the ASFIC pin B4 to a logic high. This high will keep Q0611 switched on. This 
operation allows a momentary press of the emergency switch to power up the radio. When the 
microprocessor has finished processing the emergency press, it sets the B+...

 
Open Controller
3.1-4Introduction/Theory of Operation
 
2.8 Microprocessor Clock Synthesizer 
The clock source for the microprocessor system is generated by the ASFIC (U0201). Upon power-
up the synthesizer U5701 (UHF) / U3701 (VHF) / U2701 (MB) generates a 2.1 MHz waveform that is 
routed from the RF section (via C0202) to the ASFIC (on U0201-E1) For the main board controller 
the ASFIC uses 2.1MHz as a reference input clock signal for its internal synthesizer. The ASFIC, in 
addition to audio...

 
Open Controller
Introduction/Theory of Operation3.1-5
 
When the control head with graphical display wants to communicate to the  
m  
P it brings request line 
ANALOG 2 (J0101-11) to a logic “0“. The  
m 
P reads this line via one of the analogue to digital 
converters (U0101-48) and then starts communication by activating the control head select line 
(LED CHT CE) via U0105-9 and J0101-12, sending the clock signal via U0106-3 and J0101-5 and 
sending data via U0106-2 and J0101-6 or receiving data via...

 
Open Controller
3.1-6Introduction/Theory of Operation
 
2.11 General Purpose Input/Output 
The Controller provides one general purpose line (GP I/O) available on the accessory connector 
J0400-12 to interface to external options. The software and the hardware configuration of the radio 
model defines the function of the port. The port uses an output transistor (Q0432) controlled by  
m 
P 
via ASFIC port GCB3 (pin B3).
An external alarm output, available on J0400 pin 4 is generated by the  
m 
P via...

Open Controller
Introduction/Theory of Operation3.1-7
Specifically, the logic high levels should be between 4.8 and 5.0 V, and the logic low levels should be 
between 0 and 0.2 V. No other intermediate levels should be observed, and the rise and fall times 
should be 

Open Controller
3.1-8Introduction/Theory of Operation
2.13 FLASH Electronically Erasable Programmable Memory 
(FLASH EEPROM)
The 512 KByte FLASH EEPROM (U0102) contains the radio operating software. This software is 
common to all open architecture radios within a given model type. This is, as opposed to the 
codeplug information stored in EEPROM (U0104) which could be different from one user to another 
in the same company.
In normal operating mode, this memory is only read, not written to. The memory...

General
Introduction/Theory of Operation3.1-9
2.15 Static Random Access Memory (SRAM)
The SRAM (U0103) contains temporary radio calculations or parameters that can change very 
frequently, and which are generated and stored by the software during its normal operation. The 
information is lost when the radio is turned off. The device allows an unlimited number of write 
cycles. SRAM accesses are indicated by the CS signal U103-20 (which comes from U101-CSGP2) 
going low. U0103 is commonly referred to as...

Transmit Audio Circuits
3.1-10Introduction/Theory of Operation
4.0 Transmit Audio Circuits
Refer to Figure 3-1 for reference for the following sections.
4.1 Mic Input Path 
The radio supports two distinct microphone paths known as internal (from Control Head) and 
external mic (from accessory connector J0400-2) and an auxiliary path (FLAT TX AUDIO). The 
microphones used for the radio require a DC biasing voltage provided by a resistive network.
These two microphone audio inputs are connected together...