Motorola Gm Series Detailed 6864115b62 B Manual

							Controller Circuits1-3
The voltage VSTBY, which is derived  directly from the supply voltage by components R0621 and 
VR0621, is used to buffer the internal RAM. C0622 allows the battery voltage to be disconnected for 
a couple of seconds without losing RAM parameters. Dual diode D0621 prevents radio circuitry from 
discharging this capacitor.  When the supply voltage is applied to the radio, C0622 is charged via 
R0621 and D0621. To avoid that the µP enters the wrong mode when the radio is switched on while 
the voltage across C0622 is still too low, the regulated 5V charges C0622 via diode D0621.
Figure 2-1 DC Power Distribution Block Diagram
The voltage INT SW B+ from switching transistor Q0661 provides power to the circuit controlling the 
audio PA output. The voltage INT SW B+ voltage is monitored by the µP through voltage divider 
R0671 / R0672 and line BATTERY VOLTAGE. Diode VR0671 limits the divided voltage to 5.6V to 
protect the µP.
Regulator U0611 is used to generate the voltage for the switched supply voltage output (SWB+) at 
the accessory connector J0501 pin 13. U0611 is configured to operate as a switch with voltage and 
current limit. R0611 / R0612 set the maximum output voltage to 16.5 volts. This limitation is only 
active at high supply voltage levels. The regulator output is electronically enabled by a 0 volt signal 
on pin 2. Q0661, Q0641 and R0641 are used to disable the regulator when the radio is turned off. 
Input and output capacitors (C0603 and C0611 / C0612) are used to reduce high frequency noise.
Diode VR0601 acts as protection against transients and wrong polarity of the supply voltage.
Fuse F0401 prevents damage of the board in case the FLT A+ line is shorted at the controlhead 
connector.
1.4 Electronic ON/OFF
The radio has circuitry which allows radio software and/or external triggers to turn the radio on or off 
without direct user action. For example, automatic turn on when ignition is sensed and off when 
ignition is off.
Q0661 is used to provide INT SW B+ to the various radio circuits and to enable the voltage 
regulators via transistor Q0641. Q0661 contains an pnp and an npn transistor and acts as an 
electronic on/off switch. The switch is on when the collector of the npn transistor within Q0661 is low. 
When the radio is off the collector is at supply voltage level. This effectively prevents current flow 
  VCOBIC  FRACTN
VSTBY
5V_RF 9V3
FLT_A+
5VD
SWB+
Option Board 
40 Pin Connector PA, Driver 
Antenna SwitchControlhead
12 Pin Connector Accessories
20 Pin ConnectorJ0601 
13.2V
PASUPVLTG
FLT_A+16.5V
Limiter
ON / OFF
Control
ASFIC_CMP
5.6VIgnition
Emergency
ON/OFF
9.3V
Regulator
Audio PA
6V
Regulator5V
Regulator
5VD
5V
Regulator5V/
VDDA
MCU 
µP, RAM, 
FLASH & EEPROM PCIC, 
TX Amp
Temp Sense
 RX RF Amp
IF Amp
F0401 
						

							1-4THEORY OF OPERATION
from emitter to collector of the pnp transistor. When the radio is turned on the voltage at the base of 
the npn transistor is pulled high and the pnp transistor  switches on (saturation). With voltage INT 
SWB+ now at supply voltage level, transistor Q0641 pulls pin 2 of the voltage regulators U0611 and 
U 0641 to ground level and thereby enables their outputs. 
The electronic on/off circuitry can be enabled by the microprocessor (through ASFIC CMP port 
GCB2, line DC POWER ON), the emergency switch (line EMERGENCY CONTROL), the 
mechanical On/Off/Volume knob on the controlhead (line ON OFF CONTROL), or the ignition sense 
circuitry (line IGNITION CONTROL). If any of the 4 paths cause a low at the collector of the npn 
transistor within Q0661, the electronic ON is engaged.
1.5 Emergency
The emergency switch (J0501 pin 9), when engaged, grounds the base of Q0662 via line 
EMERGENCY CONTROL. This switches Q0662 off and resistor R0662 pulls the collector of Q0662 
and the base of Q0663 to levels above 2 volts. Transistor Q0663 switches on and pulls the collector 
of the npn transistor within Q0661 to ground level and thereby enables the voltage regulators via 
Q0641. When the emergency switch is released R0541 pulls the base of Q0662 up to 0.6 volts. This 
causes the collector of transistor Q0662 to go low (0.2V), thereby switching Q0663 off.
While the radio is switched on, the microprocessor monitors the voltage at the emergency input on 
the accessory connector via pin 60 and line GP5 IN ACC9. Three different conditions are 
distinguished, no emergency, emergency, and open connection to the emergency switch. If no 
emergency switch is connected or the connection to the emergency switch is broken, the resistive 
divider R0541 / R0512 will set the voltage to about 4.7 volts. If an emergency switch is connected, a 
resistor to ground within the emergency switch will reduce the voltage on line GP5 IN ACC9 to inform 
the microprocessor that the emergency switch is operational. An engaged emergency switch pulls 
line GP5 IN ACC9 to ground level. Diode D0179 limits the voltage to protect the microprocessor 
input. 
While EMERGENCY CONTROL is low, INT SW B+ is on, the microprocessor starts execution, reads 
that the emergency input is active through the voltage level of line GP5 IN ACC9, and sets the DC 
POWER ON output of the ASFIC CMP pin 13 to a logic high. This high will keep Q0661 and Q0641 
switched on. This operation allows a momentary press of the emergency switch to power up the 
radio. When the microprocessor has finished processing the emergency press, it sets the DC 
POWER ON line to a logic 0. This turns off Q0661 and the radio turns off. Notice that the 
microprocessor is alerted to the emergency condition via line GP5 IN ACC9. If the radio was already 
on when emergency was triggered then DC POWER ON would already be high.
1.6 Mechanical ON/OFF
This refers to the typical on/off/volume knob, located on the controlhead, and which turns the radio 
on and off.
If the radio is turned off and the on/off/volume knob is pressed, line ON OFF CONTROL (J0401 pin 
11) goes high and switches the radio’s voltage regulators on as long as the button is pressed. The 
microprocessor is alerted through line ON OFF SENSE (U0101 pin 6) which is pulled to low by 
Q0110 while the on / off / volume knob is pressed. In addition, an interrupt is generated at µP pin 96. 
The µP asserts line DC POWER ON via ASFIC CMP, pin 13 high which keeps Q0661 and Q0641, 
and in turn the radio, switched on. When the on/off/volume knob is released again the controlhead 
informs the µP via SBEP bus about the knob release. (See SBEP Serial Interface subsection for 
more details). This informs the µP to keep the radio switched on and continue with normal operation.
If the on/off/volume knob is pressed while the radio is on, the controlhead informs the µP via SBEP 
bus about the knob status. (See SBEP Serial Interface subsection for more details). After a short 
delay time the microprocessor switches the radio off by setting DC POWER ON to low via ASFIC 
CMP pin 13. 
						

							Controller Circuits1-5
1.7 Ignition
Ignition sense is used to prevent the radio from draining the vehicle’s battery because the engine is 
not running. 
When the IGNITION input (J0501 pin 10) goes above 5 volts Q0661 is turned on via line IGNITION 
CONTROL. Q0661 turns on INT SW B+ and the voltage regulators by turning on Q0641 and the 
microprocessor starts execution. The microprocessor is alerted through line GP6 IN ACC10. The 
voltage at the IGNITION input turns Q0181 on, which pulls microprocessor pin 74 to low. If the 
software detects a low state it asserts DC POWER ON via ASFIC pin 13 high which keeps Q0661 
and Q0641, and in turn the radio switched on.
When the IGNITION input goes below 3 volts, Q0181 switches off and R0181 pulls microprocessor 
pin 74 to high. This alerts the software to switch off the radio by setting DC POWER ON to low. The 
next time the IGNITION input goes above 5 volts the above process will be repeated. 
1.8 Microprocessor Clock Synthesizer
The clock source for the microprocessor system is generated by the ASFIC CMP (U0221). Upon 
power-up the synthesizer IC (FRAC-N) generates a 16.8 MHz waveform that is routed from the RF 
section to the ASFIC CMP pin 34. For the main board controller the ASFIC CMP uses 16.8 MHz as a 
reference input clock signal for its internal synthesizer. The ASFIC CMP, in addition to audio circuitry, 
has a programmable synthesizer which can generate a synthesized signal ranging from 1200Hz to 
32.769MHz in 1200Hz steps.
When power is first applied, the ASFIC CMP will generate its default 3.6864MHz CMOS square 
wave UP CLK (on U0221 pin 28) and this is routed to the microprocessor (U0101 pin 90). After the 
microprocessor starts operation, it reprograms the ASFIC CMP clock synthesizer to a higher UP 
CLK frequency (usually 7.3728 or 14.7456 MHz) and continues operation.
The ASFIC CMP may be reprogrammed to change the clock synthesizer frequencies at various 
times depending on the software features that are executing. In addition, the clock frequency of the 
synthesizer is changed in small amounts if there is a possibility of harmonics of this clock source 
interfering with the desired radio receive frequency.
The ASFIC CMP synthesizer loop uses C0245, C0246 and R0241 to set the switching time and jitter 
of the clock output. If the synthesizer cannot generate the required clock frequency it will switch back 
to its default 3.6864MHz output.
Because the ASFIC CMP synthesizer and the µP system will not operate without the 16.8 MHz 
reference clock it (and the voltage regulators) should be checked first in debugging the system.
The microprocessor uses XTAL Y0131 and associated components to form a Real Time Clock 
(RTC). It may be used to display the time on controlheads with display or as time stamp for incoming 
calls or messages. The real time clock is powered from the voltage VSTBY to keep it running while 
the radio is switched off. When the radio was disconnected from it’s supply voltage, the time must be 
set again.
1.9 Serial Peripheral Interface (SPI)
The µP communicates to many of the IC’s through its SPI port. This port consists of SPI TRANSMIT 
DATA (MOSI) (U0101-100), SPI RECEIVE DATA (MISO) (U0101-99), SPI CLK (U0101-1) and chip 
select lines going to the various ICs, connected on the SPI PORT (BUS). This BUS is a synchronous 
bus, in that the timing clock signal CLK is sent while SPI data (SPI TRANSMIT DATA or SPI 
RECEIVE DATA) is sent. Therefore, whenever there is activity on either SPI TRANSMIT DATA or SPI 
RECEIVE DATA there should be a uniform signal on CLK. The SPI TRANSMIT DATA is used to send 
serial from a µP to a device, and SPI RECEIVE DATA is used to send data from a device to a µP.  
						

							1-6THEORY OF OPERATION
On the controller there are two ICs on the SPI BUS, ASFIC CMP (U0221-22), and EEPROM 
(U0111-5). In the RF sections there are 2 ICs on the SPI BUS, the FRAC-N Synthesizer, and the 
Power Control IC (PCIC). The SPI TRANSMIT DATA and CLK lines going to the RF section are 
filtered by L0481 / R0481 and L0482 / R0482 to minimize noise. The chip select line CSX from 
U0101 pin 2 is shared by the ASFIC CMP, FRAC-N Synthesizer and PCIC. Each of these IC‘s check 
the SPI data and when the sent address information matches the IC’s address, the following data is 
processed. The chip select lines for the EEPROM (EE CS), Voice Storage (VS CS), expansion board 
(EXP1 CS, EXP2 CS) and option board (OPT CS) are decoded by the address decoder U0141.
When the µP needs to program any of these IC’s it brings the chip select line CSX to a logic 0 and 
then sends the proper data and clock signals. The amount of data sent to the various IC’s are 
different, for example the ASFIC CMP can receive up to 19 bytes (152 bits) while the PCIC can 
receive up to 6 bytes (48 bits). After the data has been sent the chip select line is returned to logic 1.
The Option board interfaces are different in that the µP can also read data back from devices 
connected.The timing and operation of this interface is specific to the option connected, but 
generally follows the pattern: 
1. an option board device generates a service request via J0551-29, line RDY and µP pin 79,
2. the main board asserts a chip select for that option board device via U0141-14, line OPT CS, 
J0551-30,
3. the main board µP generates the CLK (J0551-3),
4. the main board µP writes serial data via J0551-15 and reads serial data via J0551-16 and,
5. when data transfer is complete the main board terminates the chip select and CLK activity.
1.10 SBEP Serial Interface
The SBEP serial interface allows the radio to communicate with the Customer Programming 
Software (CPS), or the Universal Tuner via the Radio Interface Box (RIB). This interface connects to 
the microphone connector via controlheadcontrolhead connector (J0401-8) and to the accessory 
connector J0501-17 and comprises BUS+. The line is bi-directional, meaning that either the radio or 
the RIB can drive the line. The microprocessor sends serial data via pin 98 and D0101 and it reads 
serial data via pin 97. Whenever the microprocessor detects activity on the BUS+ line, it starts 
communication. 
In addition, the SBEP serial interface is used to communicate with a connected controlhead. When a 
controlhead key is pressed or the volume knob is rotated, the line ON OFF CONTROL goes high. 
This turns on transistor Q0110 which pulls line ON OFF SENSE and µP pin 6 to ground level. In 
addition, an interrupt is generated at µP pin 96. This indicates that the controlhead wants to start 
SBEP communication. The microprocessor then requests the data from the controlhead. The 
controlhead starts sending and after all data has been send, the ON OFF CONTROL line goes low. 
The controlheadcontrolhead ignores any data on BUS+ during SBEP communication with the CPS 
or Universal Tuner.
1.11 General Purpose Input/Output
The controller provides eight general purpose lines (DIG1 through DIG8) available on the accessory 
connector J0501 to interface to external options. Lines DIG IN 1,3,5,6, are inputs, DIG OUT 2 is an 
output and DIG IN OUT 4,7,8 are bidirectional. The software and the hardware configuration of the 
radio model define the function of each port.
DIG IN 1 can be used as external PTT input, DATA PTT input or others, set by the CPS. 
The µP reads this port via pin 77 and Q0171. 
						

							Controller Circuits1-7
DIG OUT 2 can be used as normal output or external alarm output, set by the CPS. Transistor Q0173 
is controlled by the µP via ASFIC CMP pin 14.
DIG IN 3 is read by µP pin 61 via resistor R0176
DIG IN 5 can be used as normal input or emergency input, set by the CPS. The µP reads this port via 
R0179 and µP pin 60. Diode D0179 limits the voltage to protect the µP input.
DIG IN 6 can be used as normal input, set by the CPS. The µP reads this port via pin 74 and Q0181.
DIG IN OUT 4,7,8 are bi-directional and use the same circuit configuration. Each port uses an output 
transistor Q0177, Q0183, Q0185 controlled by µP pins 46, 47, 53. The ports are read by µP pins 75, 
54, 76. To use one of the ports as input the µP must turn off the corresponding output transistor.
In addition the signals from DIG IN 1, DIG IN OUT 4 are fed to the option board connector J0551 and 
the expansion board connector J0451.
1.12 Normal Microprocessor Operation
For this radio, the µP is configured to operate in one of two modes, expanded and bootstrap. In 
expanded mode the µP uses external memory devices to operate, whereas in bootstrap operation 
the µP uses only its internal memory. In normal operation of the radio the µP is operating in 
expanded mode as described below.
In expanded mode on this radio, the µP (U0101) has access to 3 external memory devices; U0121 
(FLASH EEPROM), U0122 (SRAM), U0111 (EEPROM). Also, within the µP there are 3Kbytes of 
internal RAM, as well as logic to select external memory devices.
The external EEPROM (U0111) space contains the information in the radio which is customer 
specific, referred to as the codeplug. This information consists of items such as: 1) what band the 
radio operates in, 2) what frequencies are assigned to what channel, and 3) tuning information. (See 
the particular device subsection for more details.)
The external SRAM (U0122) as well as the µP’s own internal RAM space are used for temporary 
calculations required by the software during execution. All of the data stored in both of these 
locations is lost when the radio powers off (See the particular device subsection for more details).
The FLASH EEPROM contains the actual Radio Operating Software. This software is common to all 
open architecture radios within a given model type. For example Trunking radios may have a different 
version of software in the FLASH EEPROM than a non Trunking radio (See the particular device 
subsection for more details).
The µP provides an address bus of 16 address lines (ADDR 0 - ADDR 15), and a data bus of 8 data 
lines (DATA 0 - DATA 7). There are also 3 control lines; CSPROG (U0101-38) to chip select U0121-
30 (FLASH EEPROM), CSGP2 (U0101-41) to chip select U0122-20 (SRAM) and PG7 R W (U0101-
4) to select whether to read or to write. The external EEPROM (U0111-1), the OPTION BOARD and 
EXPANSION BOARD are selected by 3 lines of the µP using address decoder U0141. The chips 
ASFIC CMP / FRAC-N / PCIC are selected by line CSX (U0101-2).
When the µP is functioning normally, the address and data lines should be toggling at CMOS logic 
levels. Specifically, the logic high levels should be between 4.8 and 5.0V, and the logic low levels 
should be between 0 and 0.2V. No other intermediate levels should be observed, and the rise and fall 
times should be 
						

							1-8THEORY OF OPERATION
On the µP the lines XIRQ (U0101-48), MODA LIR (U0101-58), MODB VSTPY (U0101-57) and 
RESET (U0101-94) should be high at all times during normal operation. Whenever a data or address 
line becomes open or shorted to an adjacent line, a common symptom is that the RESET line goes 
low periodically, with the period being in the order of 20msecs. In the case of shorted lines you may 
also detect the line periodically at an intermediate level, i.e. around 2.5V when 2 shorted lines 
attempt to drive to opposite rails.
The MODA LIR (U0101-58) and MODB VSTPY (U0101-57) inputs to the µP must be at a logic 1 for 
it to start executing correctly. After the µP starts execution it will periodically pulse these lines to 
determine the desired operating mode. While the Central Processing Unit (CPU) is running, MODA 
LIR is an open-drain CMOS output which goes low whenever the µP begins a new instruction (an 
instruction typically requires 2-4 external bus cycles, or memory fetches). However, since it is an 
open-drain output, the waveform rise assumes an exponential shape similar to an RC circuit.
There are 8 analogue to digital converter ports (A/D) on U0101. They are labelled within the device 
block as PE0-PE7. These lines sense the voltage level ranging from 0 to 5V of the input line and 
convert that level to a number ranging from 0 to 255 which can be read by the software to take 
appropriate action.
For example U0101-67 is the battery voltage detect line. R0671 and R0672 form a resistor divider on 
INT SWB+. With 30K and 10K and a voltage range of 11V to 17V, that A/D port would see 2.74V to 
4.24V which would then be converted to ~140 to 217 respectively.
U0101-69 is the high reference voltage for the A/D ports on the µP. Capacitor C0101 filters the +5V 
reference. If this voltage is lower than +5V the A/D readings will be incorrect. Likewise U0101-68 is 
the low reference for the A/D ports. This line is normally tied to ground. If this line is not connected to 
ground, the A/D readings will be incorrect.
1.13 FLASH Electronically Erasable Programmable Memory (FLASH EEPROM)
The 512KByte FLASH EEPROM (U0121) contains the radio’s operating software. This software is 
common to all open architecture radios within a given model type. For example Trunking radios may 
have a different version of software in the FLASH EEPROM than a non Trunking radio. This is, as 
opposed to the codeplug information stored in EEPROM (U0111) which could be different from one 
user to another in the same company.
In normal operating mode, this memory is only read, not written to. The memory access signals (CE, 
OE and WE) are generated by the µP.
To upgrade/reprogram the FLASH software, the µP must be set in bootstrap operating mode. This is 
done by pulling microprocessor pins MODA LIR (U0101-58) and MODB VSTBY (U0101-57) to low 
during power up. When accessory connector pin 18 is at ground level, diode D0151 will pull both 
microprocessor pins to low. The same can be done by a level of 12 volts on line ON OFF CONTROL 
from the controlhead. Q0151 pulls diode D0151 and in turn both microprocessor pins to low. Diode 
VR0151 prevents entering bootstrap operating mode during normal power up.
In bootstrap operating mode the µP controls the FLASH EN OE (U0121-32) input by µP pin 86. Chip 
select (U0121-30) and read or write operation (U0121-7) are controlled by µP pins 38 and 4.
The FLASH device may be reprogrammed 1,000 times without issue. It is not recommended to 
reprogram the FLASH device at a temperature below 0°C.
Capacitor C0121 serves to filter out any AC noise which may ride on +5V at U0121. 
						

							Controller Board Audio and Signalling Circuits 1-9
1.14 Electrically Erasable Programmable Memory (EEPROM)
The external 16 Kbyte EEPROM (U0111) contains additional radio operating parameters such as 
operating frequency and signalling features, commonly know as the codeplug. It is also used to store 
radio operating state parameters such as current mode and volume. This memory can be written to 
in excess of 100,000 times and will retain the data when power is removed from the radio. The 
memory access signals (SI, SO and SCK) are generated by the µP and chip select (CS) is generated 
by address decoder U0141-15.
1.15 Static Random Access Memory (SRAM)
The SRAM (U0121) contains temporary radio calculations or parameters that can change very 
frequently, and which are generated and stored by the software during its normal operation. The 
information is lost when the radio is turned off. 
The device allows an unlimited number of write cycles. SRAM accesses are indicated by the CS 
signal U0122-20 (which comes from U0101-CSGP2) going low. U0122 is commonly referred to as 
the external RAM as opposed to the internal RAM which is the 3 Kbytes of RAM which is part of the 
68HC11FL0. Both RAM spaces serve the purpose. However, the internal RAM is used for the 
calculated values which are accessed most often.
Capacitor C0122 serves to filter out any ac noise which may ride on +5V at U0122.
2.0 Controller Board Audio and Signalling Circuits
2.1 General - Audio Signalling Filter IC with Compander (ASFIC CMP)
The ASFIC CMP (U0221) used in the controller has 4 functions;
1) RX/TX audio shaping, i.e. filtering, amplification, attenuation
2) RX/TX signalling, PL/DPL/HST/MDC/MPT
3) Squelch detection
4) Microprocessor clock signal generation (see Microprocessor Clock Synthesizer Description).
The ASFIC CMP is programmable through the SPI BUS (U0221-20/21/22), normally receiving 19 
bytes. This programming sets up various paths within the ASFIC CMP to route audio and/or 
signalling signals through the appropriate filtering, gain and attenuator blocks. The ASFIC CMP also 
has 6 General Control Bits GCB0-5 which are CMOS level outputs and used for NOISE BLANKER 
(GCB0) in Low Band radios, EXTERNAL ALARM (GCB1) and DC POWER ON (GCB2) to switch the 
voltage regulators (and the radio) on and off. GCB3 controls U0251 pin 11 to output either RX FLAT 
AUDIO or RX FILTERED AUDIO on the accessory connector pin 11. GCB4 controls U0251 pin 10 to 
use either the external microphone input or the voice storage playback signal. GCB5 is used to 
switch the audio PA on and off. 
						

							1-10THEORY OF OPERATION
2.2 Transmit Audio Circuits
Refer to Figure 3-1 for reference for the following sections.
Figure 3-1 Transmit Audio Paths
2.2.1 Mic/Data Input Path
The radio supports 2 distinct microphone paths known as internal (from controlhead) and external 
mic (from accessory connector J0501-2) and an auxiliary path (FLAT TX AUDIO, from accessory 
connector J0501-5). The microphones used for the radio require a DC biasing voltage provided by a 
resistive network.
These two microphone audio input paths enter the ASFIC CMP at U0221-48 (external mic) and 
U0221-46 (internal mic). Following the internal mic path; the microphone is plugged into the radio 
controlhead and is connected to the controller board via J0401-9.
From here the signal is routed via R0409 and line INT MIC to R0205. R0201 and R0202 provide the 
9.3VDC bias. Resistive divider R0205 / R0207 divide the input signal by 5.5 and provide input 
protection for the CMOS amplifier input. R0202 and C0201 provide a 560 ohm AC path to ground 
that sets the input impedance for the microphone and determines the gain based on the emitter 
resistor in the microphone’s amplifier circuit.
C0204 serves as a DC blocking capacitor. The audio signal at U0221-46 (TP0221) should be 
approximately 14mV for 1.5kHz or 3kHz of deviation with 12.5kHz or 25kHz channel spacing.
The external microphone signal enters the radio on accessory connector J0501 pin 2 and is routed 
via line EXT MIC to R0206. R0203 and R0204 provide the 9.3VDC bias. Resistive divider R0206 / 
R0208 divide the input signal by 5.5 and provide input protection for the CMOS amplifier input. 
R0204 and C0202 provide a 560 ohm AC path to ground that sets the input impedance for the 
microphone and determines the gain based on the emitter resistor in the microphone’s amplifier 
circuit.
MIC 
IN
MOD IN
TO
RF
SECTION
(SYNTHESIZER)
36 44
33
40
J0501
ACCESSORY
CONNECTOR
J0401
CONTROL HEAD
CONNECTOR
MIC
EXT MIC
FLAT TX
AUDIO4232
548
46 9
2
IN
OUT
OPTION
BOARD
FILTERS AND
PREEMPHASIS
HS SUMMER
SPLATTER
FILTER
LS SUMMERLIMITER
ATTENUATORVCO 
ATN TX RTN TX SND
MIC
INT
AUX 
TX
ASFIC_CMP 
 U0221
TP0221
TP0222MIC
EXT
J0451J0551
18 FLAT
TX RTN
EXPANSION BOARD31
IN/OUT
39
OUT
FROM
µ
P Pin3U0211-4 
						

							Controller Board Audio and Signalling Circuits 1-11
C0254 serves as a DC blocking capacitor. Multi switch U0251 controlled by ASFIC CMP port GCB4 
selects either the external microphone input signal or the voice storage playback signal for entering 
the ASFIC CMP at pin 48. The audio signal at U0221-48 (TP0222) should be approximately 14mV 
for 1.5kHz or 3kHz of deviation with 12.5kHz or 25kHz channel spacing.
The FLAT TX AUDIO path is used for transmitting data signals and has therefore no limiter or filters 
enabled inside the ASFIC CMP. When this path is enabled via CPS and DATA PTT is asserted, any 
signal on this path is directly fed to the modulator. Signals applied to this path either via accessory 
connector J0501, expansion board connector J0451 or option board connector J0551 must be 
filtered and set to the correct level externally or on the option board in order not to exceed the 
maximum specified transmit deviation and transmitted power in the adjacent channels. The 
attenuator inside the ASFIC CMP changes the FM deviation of the data signal according to the 
channel spacing of the active transmit channel.
The FLAT TX AUDIO signal from accessory connector J0501-5 is fed to the ASFIC CMP (U0221) 
pin42 through C0541 and line FLAT TX RTN, switch U0251 and buffer U0211-4. When the radio 
switches from receive to transmit mode the µP opens switch U0251 for a short period to prevent that 
any applied signal can cause a transmit frequency offset. Buffer U0211-4 sets the correct DC level 
and ensures a short settle period when the radio is switched on. Inside the ASFIC CMP the signal is 
routed directly to the attenuator, which sets the FM deviation according to the channel spacing of the 
active transmit channel and emerges from the ASFIC CMP at U0221-40, at which point it is routed to 
the RF section.
The ASFIC has an internal AGC that can control the gain in the mic audio path. The AGC can be 
disabled / enabled by the µP. Another feature that can be enabled or disabled in the ASFIC is the 
VOX. This circuit, along with the capacitor at U0221-7, provides a DC voltage that can allow the µP to 
detect microphone audio. The ASFIC can also be programmed to route the microphone audio to the 
speaker for public address operation.
2.2.2 PTT Sensing and TX Audio Processing
Microphone PTT coming from the controlhead is sent via SBEP bus to the microprocessor. An 
external PTT can be generated by grounding pin 3 on the accessory connector if this input is 
programmed for PTT by the CPS. When microphone PTT is sensed, the µP will always configure the 
ASFIC CMP for the internal mic audio path, and external PTT will result in the external mic audio 
path being selected.
Inside the ASFIC CMP, the mic audio is filtered to eliminate frequency components outside the 300-
3000Hz voice band, and pre-emphasized if pre-emphasis is enabled. The signal is then limited to 
prevent the transmitter from over deviating. The limited mic audio is then routed through a summer, 
which is used to add in signalling data, and then to a splatter filter to eliminate high frequency 
spectral components that could be generated by the limiter. The audio is then routed to an 
attenuator, which is tuned in the factory or the field to set the proper amount of FM deviation. The TX 
audio emerges from the ASFIC CMP at U0221-40 MOD IN, at which point it is routed to the RF 
section.
Dependent on the radio model, input pin 3 on the accessory connector can be programmed for DATA 
PTT by the CPS. When DATA PTT is sensed, the µP will always configure the ASFIC CMP for the flat 
TX audio path. Limiter and any filtering will be disabled. The signal is routed directly to the attenuator, 
which sets the FM deviation according to the channel spacing of the active transmit channel and 
emerges from the ASFIC CMP at U0221-40, at which point it is routed to the RF section.
2.2.3 TX Secure Audio (optional)
The audio follows the normal transmit audio processing until it emerges from the ASFIC CMP TX 
SND pin (U0221-44), which is fed to the Secure board residing at option connector J0551-33. The  
						

							1-12THEORY OF OPERATION
Secure board contains circuitry to amplify, encrypt, and filter the audio. The encrypted signal is then 
fed back from J0551-32 to the ASFIC CMP TX RTN input (U0221-36). The signal level at this pin 
should be about 65mVrms. The signal is then routed through the TX path in the ASFIC CMP and 
emerges at MOD IN pin 40.
2.2.4 Option Board Transmit Audio
The audio follows the normal transmit audio processing until it emerges from the ASFIC CMP TX 
SND pin (U0221-44), which is fed to the option board residing at option connector J0551-33. The 
option board contains circuitry to process the audio. The processed signal is then fed back from 
J0551-32 to the ASFIC CMP TX RTN input (U0221-36). The signal level at this pin should be about 
65mVrms. The signal is then routed through the TX path in the ASFIC CMP and emerges at MOD IN 
pin 40.
2.3 Transmit Signalling Circuits
Refer to Figure 4-1 for reference for the following sections.
Figure 4-1 Transmit Signalling Paths
From a hardware point of view, there are 3 types of signalling:
1) sub-audible data (PL / DPL / Connect Tone) that gets summed with transmit voice or signalling,
2) DTMF data for telephone communication in trunked and conventional systems, and
3) Audible signalling including Select 5, MPT-1327, MDC, High speed Trunking.
NOTE: All three types are supported by the hardware while the radio software determines which 
signalling type is available.
2.3.1 Sub-audible Data (PL/DPL)
Sub-audible data implies signalling whose bandwidth is below 300Hz. PL and DPL waveforms are 
used for conventional operation and connect tones for trunked voice channel operation. The trunking 
connect tone is simply a PL tone at a higher deviation level than PL in a conventional system. 
Although it is referred to as sub-audible data, the actual frequency spectrum of these waveforms 
19
18
40
MOD INTO RF
SECTION
(SYNTHESIZER)
8044
HIGH SPEED
CLOCK IN
(HSIO)
LOW SPEED 
CLOCK IN
(LSIO)
ASFIC_CMP U0221
MICRO
CONTROLLER
U0101
HS
SUMMER
5-3-2 STATE 
ENCODER
DTMF 
ENCODERSPLATTER
FILTER
PL
ENCODERLS
SUMMER
ATTENUATOR
8582
SPI
BUS