Motorola Astro Digitalport Saber Detailed 68p81076c10 A Manual

7-8
The ADSIC contains four general purpose I/O labeled GCB0 -GCB3. 
These are connected to the AUDIO PA and are used for enabling the 
speaker and microphone amplifiers in the IC and for steering the 
speaker and microphone audio paths from internal to external. These 
I/O are controlled by the DSP through the ADSIC parallel 
configuration bus. The DSP then writes speaker data samples to the 
speaker D/A register through the parallel bus at an 8kHz rate and 
configures the AUDIO PA enable lines by writing...

7-9
samples, the DSP reads the microphone samples from registers 
mapped into its memory space starting at Y:FFF0. The ADSIC provides 
an 8kHz interrupt to the DSP on IRQB for processing these 
microphone data samples.
As with the received trunking low speed data, low speed data is 
processed by the MCU and returned to the DSP at the DSP SCLK port 
connected to the MCU port PA0. 
For secure messages, the analog signal may be passed to the secure 
module for encryption prior to further processing. The DSP...

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Controller 
Bootstrap and 
Asynchronous BusesThe SB9600 bus is an asynchronous serial communications bus 
utilizing a Motorola proprietary protocol. Its purpose is a means for 
the MCU to communicate with other hardware devices. In the ASTRO 
Digital SABER radio, it communicates with hardware accessories 
connected to the universal connector.
The SB9600 bus utilizes the UART internal to the MCU operating at 
9600 baud. The SB9600 bus consists of a LH_DATA (J201-4) and 
SB9600_BUSY (J201-6) signals....

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MCU SCI port. Now if the Vpp voltage is raised to 12Vdc required on 
the FLASH devices for programming; the circuit comprised of VR208, 
Q211, and Q208 will trip supplying Vpp to the FLASH devices U205, 
U210, and U404. One more complication exists in that the 
BOOT_DATA_IN signal, RXD is multiplexed with the RS232 data out 
signal RS232_DATA_OUT. This multiplex occurs in the SLIC IV U206, 
which must also be properly configured.
The ASTRO Digital SABER radio has an additional asynchronous serial...

7-12
SPI Bus InterfaceThis bus is a synchronous serial bus made up of a data, a clock, and an 
individual IC unique select line. Its primary purpose is to configure 
the operating state of each IC. ICs programmed by this include; 
display module, ADSIC, Fractional N Synthesizer, Pendulum Reference 
Oscillator, DAIC, and if equipped, the secure module.
The MCU (U204) is configured as the master of the bus. It provides the 
synchronous clock (SPI_SCK), a select line, and data (MOSI [Master 
Out Slave In])....

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Most of the signals are extensions of circuits described in other areas 
of this manual. However there are two option select pins used to 
configure special modes; Option Select 1 and Option Select 2. These 
pins are controlled by accessories connected to the universal 
connector. The following table outlines their functions as defined at 
the universal connector:
Keypad and Display 
ModuleThe front cover assembly contains the internal speaker, and internal 
microphone. An optional integral 2 line by...

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Controls and 
Control Top FlexThe control top controls include an on/off switch, volume, 16 position 
mode select switch with two position toggle, and ergo code/clear mode 
switch with additional emergency switch. The side controls include 
three momentary push button switches (monitor, RAT1, RAT2) and 
PTT. These components are connected through a flex circuit to the 
controller at J901, see Figure 11. 
UNSW_B+ is routed through S901 to provide the B+_SENSE signal 
which provides radio power...

7-15
S902 is a binary coded switch. The output pins from this switch are 
connected to I/O ports on the controller. It provides a 4 bit binary 
word to the MCU indicating which of the 16 positions the rotary is set 
to. This switch provides an additional output, A/B_SWITCH, which 
effectively doubles its range by providing decoding for two sets of 16 
positions. A/B_SWITCH is also read by the MCU on an I/O port.
Controller Memory 
MapFigure 12 depicts the controller section memory map for the parallel...

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external SRAM through the gate U211. XTSCB3 is used as general 
purpose I/O for interrupting the secure module.
In bootstrap mode the memory map is slightly different. Internal 
EEPROM is mapped at $FE00-$FFFF and F1 internal SRAM starts at 
$0000-$03FF. In addition a special bootstrap ROM appears in the ROM 
space from $B600-$BFFF. For additional information on bootstrap 
mode refer to the section Controller Bootstrap and Asynchronous 
Buses.
Figure 12 .  Controller Memory Mapping
$1060
$1500
$1600...

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The SLIC is controlled through sixteen registers mapped into the MCU 
memory at $1400 - $14FF. This mapping is achieved by the following 
signals from the MCU: R/W*, CSIO1*, HA0-HA4,HA8, HA9. Upon 
power-up, the MCU configures the SLIC including the memory map 
by writing to these registers.
The SLIC memory management functions in conjunction with the 
chip selects provided by the MCU provide the decoding logic for the 
memory map which is dependent upon the “map” selected in the 
SLIC. The MCU...