Kenwood Tk 860h Manual

							21
TK-860G/862G
INSTALLATION
2. Accessory Terminal (TX-RX Unit)
2-1. External Connector Accessory Terminal Method
No. Name I/O Description Note
CN1 1 8C O DC 8V output
2 5S O DC 5V output
3 AUX5 O SMRD : Reset output *1
4 AUX6 O5SC : 5S control (Cannot use)*1
5 NC – Non-connection
6 AUX3 O SQ : Squelch detect output *2
7 AUX1 I PTT : External PTT input *2
8 AUX4 TXDTXD : Serial control data output*1
9 AUX2 RXDRXD : Serial control data input*1
I DTC : Data channel control/
External hook input
I CHDATA : Channel control
serial data input
10 ALT I Alert tone input
11 AFO O Receiver audio signal output
12 AFI I Receiver audio signal input
13 MII I Transmit audio signal input
14 MIO O Transmit audio signal output
15 GND – Ground
CN3 1 HOR O Horn alert/call output
2 E – Ground
3 SB O Switched B+, DC 13.6V
output, Maximum 1A
CN4 1 DEO O Receiver detector output
Level : 0.5Vrms
(Standard modulation)
2 DTC I Data channel control/
External hook input
3 IGN I Ignition sense input
4 DI I Data modulation input
5 ME – External microphone ground
6 MI I External microphone input
7 PTT IExternal PTT input, active low
8 SQ O Squelch detect output
CN5 1 AM ISpeaker mute input, active high
2 MM I MIC mute input, active high
3 EMG/TXS I EMG : Foot switch input, *3
active low
CN7 1 PA/LI O Relay for PA function KAP-1
control
OPA/LI ON : High, PA/LI OFF : Low
2 SPO O Audio signal output to KAP-1
3 SPI IAudio signal input from KAP-1
CN8 1 SP O Audio signal output to
internal/external speaker
2 E – Ground
*1 : SmarTrunk OMNI mode
*2 : MDT mode
*3 : Emergency mode
3. Ignition Sense Cable (KCT-18 : Option)
The KCT-18 is an optional cable for enabling the ignition
function. The ignition function lets you turn the power to the
transceiver on and off with the car ignition key.
If you use the Horn Alert function or the Manual Relay
function, you can turn the function off while driving with the
ignition key.
3-1. Connecting the KCT-18 to the Transceiver
1. Install the KCT-19 in the transceiver.   (See the KCT-19
section.)
2. Insert the KCT-18 lead terminal ( ) into pin 3 of the
square plug ( ) supplied with the KCT-19, then insert
the square plug into the KCT-19 connector ( ).
2
1
3
1
3
6 13
15
KCT-18 KCT-19
Contact12 3
Fig. 3 
						

							22
TK-860G/862G
INSTALLATION
3-2. Modifying the Transceiver
Modify the transceiver as follows to turn the power or
the Horn Alert or Manual Relay function on and off with the
ignition key.
1. Remove the lower half of the transceiver case.
2. Set jumper resistors (0Ω) R134 and R135 of the TX-RX
unit (A/2) as shown in Table 1.
TX-RX UNIT
    (A/2)
ANT
KCT-19
CN2
R134R133
R135
Fig. 4
Operation when KCT-18 R134 R135
is connected
Enable Enable← KCT-18 cannot
Power on/off and HornDisable Enable     be connected
Alert or AUX-A on/off
Horn Alert or AUX-AEnable Disable
on/off
Disable Disable← Power cannot
     be turned on
Table 1 R134 and R135 setup chart
23
4
1
3
W1
W2
CN1
CN2
KCT-19
Cushion
(G13-1710-04)
CN3
CN7
1CN3
Fig. 5
4. PA/HA Unit (KAP-1 : Option)
4-1. Installing the KAP-1 in the Transceiver
The Horn Alert (max. 2A drive) and Public Address func-
tions are enabled by inserting the KAP-1 W1 (3P; white/
black/red) into CN3 on the TX-RX unit, inserting W2 (3P;
green) into CN7 on the TX-RX unit, and connecting the KCT-
19 (option) to CN2 and CN3 of the KAP-1.
•Installation procedure
1. Open the upper case of the transceiver.
2. Insert the two cables ( ) with connectors from the
KAP-1 switch unit into the connectors on the transceiver.
3. Secure the switch unit board to the chassis with a screw
( ).  The notch ( ) in the board must be placed at the
front left side.
4. Attach the cushion on the top of the KAP-1 switch unit.
1
32
5. Fitting the Control Panel Upside Down
The TK-860G/862G control panel can be fitted upside
down, so the transceiver can be mounted with its internal
speaker (in the upper half of the case) facing down in your
car.
1. Remove the control panel and the TX-RX unit (B/2) con-
trol section.  (Fig. 6)
Fig. 6 
						

							23
TK-860G/862G
INSTALLATION
12
34
5
6
2. Fold the flat cable ( ) in the opposite direction ( ).
3. Rotate the control section ( ) 180 degrees ( ).
4. Insert the flat cable into the control section connector,
CN501 ( ).
5. Mount the control section on the transceiver ( ).
CN501
1
2
3
4
5
6
Fig. 7
6. External Speaker
6-1. KES-3 : Option
The KES-3 is an external speaker for the 3.5-mm-diam-
eter speaker jack.
•Connection procedure
1. Connect the KES-3 to the 3.5-mm-diameter speaker jack
on the rear of the transceiver.
KES-3
Fig. 9
6. Rotate the control panel 180 degrees and mount it on the
transceiver.  Refit the two halves of the case to complete
installation.  (Fig. 8)
Fig. 86-2. KES-4 : Option
The KES-4 is an external speaker used with the acces-
sory connection cable.
•Connection procedure
1. Install the KCT-19 in the transceiver.  (See the KCT-19
section.)
2. Insert the crimp terminal into the square plug supplied
with the KCT-19.
3. Connect CN8 of the transceiver to connector C of the
KCT-19 instead of to the internal speaker connector.
KES-4
1
3
6 13
15
12
Crimp terminal
(E23-0613-05)Black lead
Black/White lead
Fig. 10 
						

							24
TK-860G/862G
Frequency Configuration
The receiver utilizes double conversion.  The first IF is
49.95MHz and the second IF is 450kHz.  The first local oscil-
lator signal is supplied from the PLL circuit.
The PLL circuit in the transmitter generates the neces-
sary frequencies.  Figure 1 shows the frequencies.
Fig. 1 Frequency configuration
Receiver System
The receiver is double conversion superheterodyne.  The
frequency configuration is shown in Figure 1.

Front-end RF Amplifier
An incoming signal from the antenna is applied to an RF
amplifier (Q34) after passing through a transmit/receive
switch circuit (D33 and D34 are off) and a BPF (L22 : two-
pole helical resonators).  After the signal is amplified (Q34),
the signal is filtered by a BPF (L13 : two-pile herical resona-
tors) to eliminate unwanted signals before it is passed to the
first mixer.  Band pass filters (L22 and L13) have varactor
diodes (D28, D31, D18 and D23).
The voltage of these diodes are controlled by to track the
CPU (IC502) center frequency of the band pass filter. (See
Fig. 2)

First Mixer
The signal from the RF amplifier is heterodyned with the
first local oscillator signal from the PLL frequency synthe-
sizer circuit at the first mixer (Q15) to create a 49.95MHz
first intermediate frequency (1st IF) signal.  The first IF signal
is then fed through two monolithic crystal filters (MCFs :
XF1) to further remove spurious signals.

IF Amplifier
The first IF signal is amplified by Q13, and the enters IC5
(FM processing IC).  The signal is heterodyned again with a
second local oscillator signal within IC5 to create a 450kHz
second IF signal.  The second IF signal is then fed through a
450kHz ceramic filter (Narrow : CF1, Wide : CF2) to further
eliminate unwanted signals before it si amplified and FM
detected in IC5.
Item Rating
Nominal center frequency 49.95MHz
Pass bandwidth±5.0kHz or more at 3dB
35dB stop bandwidth±20.0kHz or less
Ripple 1.0dB or less
Insertion loss 5.0dB or less
Guaranteed attenuation 80dB or more at fo±1MHz
Spurious : 40dB or more within fo±1MHz
Terminal impedance 350Ω±5% / 5.5pF±0.5pF
Table 1 Crystal filter (L71-0551-15) : XF1
Item Rating
Nominal center frequency 450kHz
6dB bandwidth±4.5kHz or more
50dB bandwidth±10.0kHz or less
Ripple 2.0dB or less
Insertion loss 6.0dB or less
Guaranteed attenuation 55.0dB or more within fo±100kHz
Terminal impedance 2.0kΩ
Table 2 Ceramic filter (L71-0959-05) : CF1
Item Rating
Nominal center frequency 450kHz
6dB bandwidth±6.0kHz or more
50dB bandwidth±12.5kHz or less
Ripple 3.0dB or less
Insertion loss 6.0dB or less
Guaranteed attenuation 35.0dB or more within fo±100kHz
Terminal impedance 2.0kΩ
Table 3 Ceramic filter (L72-0973-05) : CF2
Fig. 2 Receiver system
CIRCUIT DESCRIPTION
ANT
SWRF
AMP1st
MIXAF
AMP
TCXO
MIC
AMP
X3
multiply
TX
AMPPA
AMP
CF 450kHz
MCF
49.95MHz
IF SYSTEM
PLL/VCO16.8MHz 50.4MHz
ANT
RX
TX
SP
MIC SW
ANT
L22
BPF
L13BPF Q34
RF AMPQ13
IF AMPIC4
AF AMP Q15
MIXXF1
MCF D33,34
ANT
SW
IC6
D/A
Q7
X3 multiplyX1
VCXOIC5
MIX,IF,DET
1st local 
OSC (VCO/PLL)DEO
CF1 (Narrow)
CF2 (Wide)
TV
CPUQ35
Wide/
Narrow SW 
						

							25
TK-860G/862G

Wide/Narrow Changeover Circuit
The W/N port (pin 4) of the shift register (IC510) is used
to switch between ceramic filters.  When the W/N port is
high, Q4 turns on and the ceramic filter SW diode (D8, D10)
CF1 turns on to receive a Narrow signal.  At the same time,
Q35 turns on and one of the filters is selected so that the
wide and narrow audio output levels are equal.
When the W/N port is low, Q3 turns on and the ceramic
filter SW diode (D8, D10) CF2 turns on to receive a Wide
signal.

AF Signal System
The detection signal (DEO) from the TX-RX unit goes to
the audio processor (IC508) of the control unit.  The signal
passes through a filter in the audio processor to adjust the
gain, and is output to IC507.  IC507 sums the AF signal and
the DTMF signal, BEEP signal and returns the resulting sig-
nal to the TX-RX unit.  The signal (AFO) sent to the TX-RX
unit is input to the D/A converter (IC6).  The AFO output level
is adjusted by the D/A converter.  The signal output from the
D/A converter is input to the audio power amplifier (IC13).
The AF signal from IC13 switches between the internal
speaker and speaker jack (J1) output.

Squelch Circuit
The detection output from the FM IF IC (IC5) passes
through a band-pass filter and a noise amplifier (Q10) in the
control unit to detect noise.  A voltage is applied to the CPU
(IC502).  The CPU controls squelch according to the voltage
(ASQ) level.  The signal from the RSSI pin of IC5 is moni-
tored.  The electric field strength of the receive signal can be
known before the ASQ voltage is input to the CPU, and the
scan stop speed is improved.
FIg. 4 AF signal systemFig. 5 Squelch circuit
CIRCUIT DESCRIPTION
Fig. 3 Wide/Narrow changeover circuit
CF1
(Narrow)
CF2
(Wide)
IFI
MXO IC5
IF system
AFO
DET
OUTC70
C72
C53 R19
R23
R46 R32 R30
R39 R38
+
+
Q358RC Q37
R59
W/N
IC510 4pin
Wide : L
Narrow : HC51
D8 D10Q35C
Q4
Wide : H
Narrow : L
AUDIO
PROCE.SUM
AMPD/A
CONV. IC508 IC507 IC6AF PAIC13 SP
DTMFAFO
DEO
CONTORL UNIT
Q10NOISE AMPD11 IC4 IC5 IC502
AF
RSSIBPFDET
CPU IF
SYSTEM
CONTROL UNIT
ASQ
RSSI
PLL Frequency Synthesizer
The PLL circuit generates the first local oscillator signal
for reception and the RF signal for transmission.

PLL
The frequency step of the PLL circuit is 5 or 6.25kHz.  A
16.8MHz reference oscillator signal is divided at IC3 by a
fixed counter to produce the 5 or 6.25kHz reference fre-
quency.  The voltage controlled oscillator (VCO) output sig-
nal is buffer amplified by Q106 (Sub-unit), then divided in IC3
by a dual-module programmable counter.  The divided signal
is compared in phase with the 5 or 6.25kHz reference signal
in the phase comparator in IC3.  The output signal from the
phase comparator is filtered through a low-pass filter and
passed to the VCO to control the oscillator frequency. (See
Fig. 6)

VCO
The TK-860G/862G has VCO in a Sub-unit (A1) housed in
a solid shielded case and connected to the TX-RX unit
through CN101.
The operating frequency is generated by Q103 in trans-
mit mode and Q101 in receive mode.  The oscillator fre-
quency is controlled by applying the VCO control voltage,
obtained from the phase comparator, to the varactor diodes
(D102 and D104 in transmit mode and D101 and D103 in
receive mode).  The RX (ST) pin is set low in receive mode
causing Q102 to turn Q103 off, and turn Q101 on.  The RX
(ST) pin is set low in transmit mode.  The outputs from Q101
and Q103 are amplified by Q106 and sent to the buffer am-
plifiers. 
						

							26
TK-860G/862G
D102,104Q103
TX VCO
Q106
BUFF
AMP
D101,103Q101
RX VCO
Q102,
104,105
T/R SW Charge
pumpLPF
Phase
comparator
1/M
1/N
PLL/VCO
5kHz/6.25kHz
5kHz/6.25kHz
REF
OSC
16.8MHzPLL
D ATAIC3 : PLL IC
Q9
RF AMP
Fig. 6 PLL circuit

Unlock Circuit
During reception, the 8RC signal goes high, the 8TC sig-
nal goes low, and Q16 turns on.  Q18 turns on and a voltage
is applied to the collector (8R).  During transmission, the
8RC signal goes low, the 8TC signal goes high and Q29
turns on.  Q28 turns on and a voltage is applied to 8T.
The CPU in the control unit monitors the PLL (IC3) LD
signal directly.  When the PLL is unlocked during transmis-
sion, the PLL LD signal goes low.  The CPU detects this
signal and makes the 8TC signal low.  When the 8TC signal
goes low, no voltage is applied to 8T, and no signal is trans-
mitted.
IC9
SHIFT
REG.IC502
CPU
Q16
SW
Q18
SW
IC3
PLL
Q29
SW
Q28
SW
LD
CONTORL UNIT
8RC8C
8R 8T
8TC
PLL lock
: LD H
Fig. 7 Unlock circuit
Q22
RF AMP
2SC4093
Q25
RF AMP
2SC3357
Q27ANT
RF AMP
2SC2954
IC400POWER AMPS-AU27AM(K3) : K,MS-AU27AL(K3) : K3 Q14
BUFFER
2SC5110
(O)IC508 IC6 Q103 IC507(1/2) MIC
AF AMP
NJM2904V
MIC KEY
INPUTAF AMP,
IDC, LPF
TC35453F
IC502
CPU
30622M
4XXXGPD/A 
CONVERTER
M62363FPIC1
SUM AMP
TA75S01FX1
VCXO
16.8MHz
VCO
2SK508NV
(K52)
IC3
PLL
MB15A02
Q106BUFFER
2SC4226
(R24)
Q9
BUFFER
2SC4215
(Y)
Fig. 8 Transmitter system
Transmitter System

Outline
The transmitter circuit produces and amplifies the de-
sired frequency directly.  It FM-modulates the carrier signal
by means of a varicap diode

Power Amplifier Circuit
The transmit output signal from the VCO is amplified to a
specified level of the power module (IC400) by the drive
block (Q22, Q25 and Q27).  The amplified signal passes
through the transmission/reception selection diode (D16)
and goes to a low-pass filter.  The low-pass filter removes
unwanted high-frequency harmonic components, and the
resulting signal is goes the antenna terminal.
CIRCUIT DESCRIPTION 
						

							27
TK-860G/862G

APC Circuit
The automatic transmission power control (APC) circuit
detects part of a power module output with a diode (D35,
D36) and applies a voltage to IC15.  IC15 compares the APC
control voltage (PC) generated by the D/A converter (IC6)
and DC amplifier (IC7) with the detection output voltage to
control Q31 and Q32, generates DB voltage from B voltage,
and stabilizes transmission output.
The APC circuit is configured to protect over current of
the power module due to fluctuations of the load at the an-
tenna end and to stabilize transmission output at voltage
and temperature variations.

Memory Circuit
The transceiver has a 2M-bit (256k x 8) flash ROM
(IC501) and an 8k-bit EEPROM (IC505).  The flash ROM con-
tains firmware programs, data and user data which is pro-
grammed with the FPU.  The EEPROM contains adjustment
data.  The CPU (IC502) controls the flash ROM through an
external address bus and an external data bus.  The CPU
controls the EEPROM through two serial data lines.
Control Circuit
The CPU carries out the following tasks:
1) Controls the shift register (IC9, IC510) AF MUTE, WIDE/
NARROW, T/R KEY outputs.
2) Adjusts the AF signal level of the audio processor (IC508)
and turns the filter select compounder on or off.
3) Controls the DTMF decoder (IC511).
4) Controls the LCD assembly display data.
5) Controls the PLL (IC3).
6) Controls the D/A converter (IC6) and adjusts the volume,
modulation and transmission power.
Fig. 9 APC circuit
Fig. 10 Control circuit
Display Circuit
The CPU (IC502) controls the shift register (IC510) and
display LEDs.  When the LED1 line goes high when the
transceiver is busy, Q508 turns on and the green LED on
D521 lights.  In transmit mode, the LED0 line goes high,
Q504 turns on and the red light lights.  Backlighting LEDs for
the key operation unit (D509~D514) and LCD are provided.
When the MBL line goes high, Q506 turns on, then Q505
turns on, and the key illumination LED lights.  A voltage is
applied to the MBL line to turn on the LCD backlight.
Fig. 11 Memory circuit
CIRCUIT DESCRIPTION
RF
AMP Q22,25RF
AMPQ27POWER
AMP IC400
APC
DRIVERQ32 DB
+B
Q31
PRI
DRIVER
DC
AMPIC7
ANT
SW D30LPFANT
POWER
DET D35,36
IC15
APC
CONTROL
D16
PC
IC6
23pinQ33
TEMP
PROTECT
IC6
D/A
converter
IC3
PLL
IC9
Shift
registerIC510
Shift
register
OE
LCDCS
CNTCK
CNTDT
AFCLR
AFMSKE
AFSTB
IC508
Audio
processor
IC511
DTMF
DECO.
IC502
CPUTX-RX UNIT
LCD ASSY
AFREG2
AFREG1
DTMDAT
DTMCLK
DTMSTD
DAST
PLST
PLDT
PLCK
SCL
SDA IC502
CPU ADDRESS BUS
DATA BUS
IC501
FLASH
ROMIC505
EEPROM
Q506
SW
Q508
SW
Q504
SW
Q505
SWMBL
LED1
LED0 IC510
Shift
registerD521
GRN
RED
D509~514
MBL
MBL

Key Matrix Circuit
The TK-860G/862G front panel has function keys.  Each
of them is connected to a cross point of a matrix of the KIN0
to KOUT2 ports of the microprocessor.  The KOUT0 to
KOUT2 ports are always high, while the KIN0 to KIN2 ports
are always low.
The microprocessor monitors the status of the KIN0 to
KOUT2 ports.  If the state of one of the ports changes, the
microprocessor assumes that the key at the matrix point
corresponding to that port has been pressed.
IC502
CPU
KIN0
KIN1
KIN2
KOUT0
KOUT1
KOUT2D/A GRP
DN
CH
DNCH
UPGRP
UPA
VOL
DNVOLUP
Fig. 12 Display circuit
Fig. 13 Key matrix circuit 
						

							28
TK-860G/862G

Encode
The QT and DQT signals are output from TO of the CPU
(IC502) and summed with the external pin DI line by the
summing amplifier (IC2) and the resulting signal goes to the
D/A converter (IC6) of the TX-RX unit.  The DTMF and 2-
TONE signals are output from DTMF of the CPU and goes to
the audio processor (IC508).  The signal is summed with a
MIC signal by the audio processor (IC508), and the resulting
signal passes through an analog switch (IC509) and goes to
the TX-RX unit (MO).
The D/A converter (IC6) adjusts the MO level and the bal-
ance between the MO and TO levels.  Part of a TO signal is
summed with MO and the resulting signal goes to the MD
pin of the VCO.  This signal is applied to a varicap diode in
the VCO for direct FM modulation.

D/A Converter
The D/A converter (IC6) is used to adjust TONE and MO
modulation, AF volume, TV voltage, FC reference voltage,
and PC POWER CONTROL voltage level.
Adjustment values are sent from the CPU as serial data.
The D/A converter has a resolution of 256 and the following
relationship is valid:
D/A output = (Vin – VDAref) / 256 x n + VDAref
Vin: Analog input
VDAref: D/A reference voltage
n: Serial data value from the microprocessor (CPU)
Power Supply Circuit
When the POWER switch on the control unit is pressed,
the PSW signal goes low.  This signal is inverted by Q26 and
sent to a flip-flop IC (IC14).  This IC outputs a control signal
when the PSW goes low.  When the power turns on, pin 1
of IC14 outputs a low signal and Q20 turns on.  The base of
Q19 goes high, Q19 turns on, SB SW (Q23) turns on and
power (SB) is supplied to the set.
This circuit has an overvoltage protection circuit.  If a DC
voltage of 20 V or higher is applied to the power cable, D21
turns on and a voltage is applied to the base of Q21.  This
voltage turns Q21 on and turns Q19 and SBSW off.

Decode
• QT/DQT/DTMF
The signal (DEO) detected by the TX-RX unit passes
through two low-pass filters of IC513, goes to TOI of the
CPU (IC502) to decode QT, DQT.  The DTMF signal is de-
coded by a dedicated IC (IC511) and the resulting signal is
sent to the CPU (IC502) as serial data.
• 2-tone
The detected signal passes through audio processor
(IC508) RX OUT.  Then it is filtered through IC504 2-stage
low-pass filtered to enter CPU (IC502) to decode 2-tone sig-
nalling.
CIRCUIT DESCRIPTION
Fig. 14 Encode
Fig. 15 Decode
X1
VCXO
IC6
D/AA1
VCO
IC1
SUM
AMP
IC509
Analog
SW
IC508
Audio
processor
IC3
PLLMB
MD
MOTO
HT
DI
MICTX-RX UNIT
TO
DTMF IC502
CPU
IC502
CPU
IC513(2/2)LPFIC513(1/2)LPF
TOI
IC511
DTMF
DECO.
IC508
Audio
processor STD
DEO
IC514(2/2)LPFIC514(1/2)LPF 2TN
RXOUT
Q23
SW
Q19
SWQ20
SWQ26
INV.IC14
F. F.
Q21
SWD21
SW
R135
R134
IGN
SB+B
PSW
Fig. 16 Power supply circuit 
						

							29
TK-860G/862G
SEMICONDUCTOR DATA

Terminal function
Pin No. Name I/O Function
1 EMGT OExternal MIC control. Mobile MIC : H
2 DTMF O DTMF/2TONE/BEEP output.
3 2TN I 2TONE decode pulse input.
4 DTMSTD I DTMF decode detect. Detect : H
5 SIM I Destination select.
6 BYTE I +5V (5C).
7 CNVSS I GND.
8 AFSTB O Base band IC strobe/reset output.
9 AFFCLK O Base band IC frame detect reset/
system reset output.
10 RESET I Reset.
11 XOUT O Clock output.
12 VSS – GND.
13 XIN I Clock input.
14 VCC – +5V.
15 NC I Pull up.
16 MICDAT I/O MIC data input/output.
17 AUX3 I/O Option board port 3.
SmarTrunk : Clock output.
18 NC – NC.
19 OE I Output enable control sift register.
20 NC – NC.
21 EEPDAT I/O EEPROM data input/output.
22 TO O QT/DQT modulation output.
23 AUX1 I Option board port 1.
SmarTrunk : Req/Ack input.
24 SFTSTB1 O Shift register strobe output.
25 DACSTB O D/A converter enable output.
26 PTT I PTT. PTT on : L
27 NC – NC.
28 NC – NC.
29 AUX4 O Option board port 4.
SmarTrunk : Data output.
30 AUX2 I/O Option board port 2.
SmartTrunk : Data input.
31 PA O MIC audio line sw control. PA : H
32 KOUT2 O Key scan output 2.
33 TXD O Serial data. PTT on : L
34 HOOK I HOOK/RXD. On hook : L
35 KOUT1 O Key scan output 1.
36 KOUT0 O Key scan output 0.
Pin No. Name I/O Function
37 RDY I Pull up.
38 NC – NC.
39 HOLD I Not used.
40,41 NC – NC.
42 RD O READ signal.
43 NC – NC.
44 WR O WRITE signal.
45 LCDCS O LCD chip enable output.
46 CNTDAT O Common data output. (LCD,
SHIFT REG, VOL, Audio processor)
47 CNTCLK O Common clock output. (EEPROM,
LCD, SHIFT REG, VOL, Audio processor)
48 CSO – Chip select signal.
49 A19 – Not used.
50~59 A18~A9 – Flash memory address bus.
60 ACC – +5V.
61 A8 – Flash memory address bus.
62 VSS – GND.
63~70 A7~A0 – Flash memory address bus.
71~73 KIN0~KIN2 I Key scan input.
74 MON I [MON] key input. On : L
75 SCN I [SCN] key input. On : L
76 PLLUL IPLL unlock detect input. Unlock : L
77 PLLSTB O PLL strobe output. Latch : H
78 MUTE I RX audio mute. Mute : H
79~86 D7~D0 – Flash memory data bus.
87 PWR (EMG) I[PWR] key input (key interrupt). On : L
88 EMG/TXS IEmergency input (key interrupt). On : L
89 RFDAT O PLL data output.
90 RFCLK O PLL clock output.
91 NC – NC.
92 RSSQL IReceive signal strength indicator input.
93 ANLSQL I Analog squelch level input.
94 AVSS – GND.
95 TOI I QT/DQT signal input.
96 VREF – Reference voltage input.
97 AVCC – +5V.
98 DTMPD O DTMF IC power control.
Power down : H
99 DTMCLK O DTMF IC decode clock output.
100 DTMDAT I DTMF IC decode data input.
Microprocessor : 30622M4102GP (TX-RX Unit IC502) 
						

							30
TK-860G/862G
SEMICONDUCTOR DATA
Shift Register : BU4094BCFV

Terminal function (TX-RX unit IC510)
Pin No.Port Name Function
4 Q1 W/N Wide/Narrow SW. Narrow : H
5 Q2 MUTEMIC mute (M models only). Mute : H
6 Q3 MBL MIC/LCD backlight control.
Backlight on : H
7 Q4 LED0 Red LED. LED lights : H
11 Q8 BSHIFT Beat shift. Shift on : H
12 Q7 AFREG2 Base band IC inter register select 2.
13 Q6 AFREG1 Base band IC inter register select 1.
14 Q5 LED1 Green LED. LED lights : H

Terminal function (TX-RX unit IC9)
Pin No.Port Name Function
4 Q1 HNCHorn alert control. Horn alert on : H
5 Q2 8RC 8R control. RX : H
6 Q3 8TC 8T control. TX : H
7 Q4 SPMUTESpeaker mute control. Mute on : H
11 Q8 AUX6Option board port 6 (AUX6). AUX on : H
12 Q7 AUX5 Option board port 5 (AUX5).
13 Q6 PA/LIPA/LIGHT control. PA/LIGHT on : H
14 Q5 RX TX/RX VCO switch. RX : L
LCD Driver : LC75833W
(Display Unit IC801 : TK-862G only)

Block diagram
Common
driverSegment driver & latch
Clock
generatorShift register
Address
detector
COM3
COM2
COM1
S35
S34
S9
S8/P8
S2/P2
S1/P1
INH
OSC
VDD
VLCD
VLCD1
VLCD2
VSS
DI
CL
CE

Terminal function
Pin No. Name I/O Function
1~8
S1/P1~S8/P8O Segment output for displaying data
9~35 S9~S35 transferred from serial data.
36~38
COM1~COM3O Common driver output. Frame
frequency fo=(fosc/384)Hz
39 VDD – Power supply for logic section
(2.7V~6.0V).
40 VLCD – Power supply for LCD driver section
(2.7V~6.0V).
41 VLCD1 I Apply 2/3 the LCD drive bias voltage
from outside. If 1/2 the bias is
applied, connect to VLCD2.
42 VCLD2 I Apply 1/3 the LCD drive bias voltage
from outside. If 1/2 the bias is
applied, connect to VLCD1.
43 VSS – GND.
44 OSC I/O Oscillation terminal.
45 INH I
Force the display to turn off regardless
of internal data. Serial data can be input
regardless of whether it is H or L.
46 CE I Chip enable. Serial data transfer
terminal. Connected to the
microprocessor.
47 CL I Synchronizing clock. Serial data
transfer terminal. Connected to
the microprocessor.
48 DI I Transfer data. Serial data transfer
terminal. Connected to the
microprocessor.