HP 9000 Dclass Manual
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6GB(HP9000rp3410server),24GB(HP9000rp3440serverwith2GBDIMMsinstalled inall12slots),or — —32GB(HP9000rp3440serverwith4GBDIMMsinstalledinthefirsteightslots) •FortheHP9000rp3410server,DIMMsareasfollows: —256MB,512MB,and1GB —standard184pins2.5V —DDR266,CL2,registered,ECC •FortheHP9000rp3440server,DIMMsareasfollows: —256MB,512MB,and1GB,2GB,4GB —standard184pins2.5V —DDR266,CL2,registered,ECC •Onlyonesupportedconfigurationfor4GBDIMMs;2quads(8DIMMs);andnootherDIMMs canbeinstalled....
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•650Woutputpower. •Thepowersupplyissplitinafrontendblock(theactualpowersupplycase)thatconverts thelinevoltageintohighDCvoltageandbackendvoltageregulationmodules(onthe motherboard)thatstepdownthefrontendDCvoltagetotherequiredvoltages. •Redundantandhot-pluggablepowersupplies(frontendblockonly). SystemBoardManageability ThefollowingissupportedontheHP9000rp3410andrp3440servers: •BaseboardManagementController(BMC). •TemperaturemonitoringandfansregulationbyBMC....
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EventIDsforErrorsandEvents TheserverfirmwaregenerateseventIDssimilartochassiscodesforerrors,events,andforward progresstotheIntegratedLight-OutManagementProcessor(iLOMP)throughcommonshared memory.TheiLOMPinterpretsandstoreseventIDs.Reviewingtheseeventshelpsyoudiagnose andtroubleshootproblemswiththeserver. DimensionsandValues Table1-1liststhedimensionsandvaluesoftheHP9000rp3410andrp3440servers. Table1-1ServerDimensionsandValues ValuesDimensions 26.8in(67.9cm)max.x19.0in(48.3cm)x3.4in(8.6cm)...
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Figure1-5SystemBoardBlockDiagram SystemBoardComponents Thefollowingdescribesthemaincomponentsofthesystemboard: •DualPA-RISCprocessors: —OneortwoprocessorsenabledintheHP9000rp3410server —One,two,orfourprocessorsenabledintheHP9000rp3440server •ZX1I/Oandmemorycontroller •ZX1PCIbuscontroller •Processordependenthardwarecontroller •Fieldprocessorgatearraycontroller •BMC •SCSIcontroller •IDEcontroller •USBcontroller •10/100/1000LAN PARISCProcessor...
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mechanicalcompatibilityandsupportcircuitryexist.AprocessorCSRconsistsofadualprocessor modulewithheatsinkassembly. OneendoftheFSBisterminatedwithanI/OASIC.Theotherendofthebusisterminatedwith aCSR.AnadditionalCSRcanbeloadedinthemiddle.Forthesystemtofunctionproperly,the processorfarthestawayfromtheI/OASICmustbeloadedatalltimestoelectricallyterminate theFSB. Eachprocessormoduleplugsdirectlyintoandispoweredbyitsown12Vto1.2Vpower-pod. Otherpowerforthesystemboardcomesfrommultipleon-boardDC/DCconverters.Each...
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Figure1-6MemoryBlockDiagram MemoryArchitecture TheI/OASICmemoryinterfacesupportstwoDDRcells,eachofwhichis144databitswide. Thememorysubsystemphysicaldesignusesacomb-filterterminationschemeforboththedata andaddress/controlbuses.ThispartofthetopologyissimilartootherDDRdesignsinthe computerindustry.ClocksaredistributeddirectlyfromtheI/OASIC;eachclockpairdrivestwo DIMMs. MemorydataisprotectedbyECC.EightECCbitsperDIMMprotect64bitsofdata.Theuseof...
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Table1-2MemoryArrayCapacities DDRSDRAMCount,TypeandTechnologySingleDIMMSizeMinimumandMaximum MemorySize 18x32MBx4DDRSDRAMs(128MB)256MBDIMM0.5GB/3GB 36x32MBx4DDRSDRAMs(128MB)512MBDIMM2GB/6GB 36x64MBx4DDRSDRAMs(256MB)1024MBDIMM4GB/12GB 36x128MBx4DDRSDRAMs(512MB)2048MBDIMM8GB/24GB 36x256MBx4DDRSDRAMs(1024MB)4096MBDIMM16GB/32GB ChipSpareFunctionality ChipspareenablesanentireDDRSDRAMchiponaDIMMtobebypassedintheeventthata multi-biterrorisdetectedontheDDRSDRAM.Inordertousethechipsparefunctionalityon...
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•16-bitPDHbuswithreservedaddressspaceforthefollowing: —Flashmemory —Nonvolatilememory —ScratchRAM —Real-timeclock —UARTs —Externalregisters —Firmwareread/writableregisters —Twogeneralpurpose32-bitregisters —Semaphoreregisters —Monarchselectionregisters —Testandresetregister •ResetandINITgeneration FieldProgrammableGateArray TheFieldProgrammableGatearray(FPGA)providesACPIandLPCsupportforthePDHbus andprovidesthesefeatures: •ACPI2.0interface •LPCbusinterfacetosupportBMC •DecodinglogicforPDHdevices BMC...
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IDEInterface TheIDEcontroller(PCI649)supportstheATAPIzero(0)tofive(5)modes(from16to100MB/s). Theusablespeedonthissystemislimitedto16MHz(ATA-33mode,33MB/s)becausethe slimlineCD/DVDdevicesdonotsupporttheATA-66and100modes. TheprimaryIDEchannelistheonlychannelthatisimplemented.TheIDEcableprovidesonly onedriveconnector,ofthemastertype,fortheopticalstorageperipheral. 1GBSystemLAN The1GBSystemLANportprovides: •MainsystemLAN •10/100/1000MBcapable USBConnectors TheUSBconnectorsprovide:...
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Table1-4ExtendedCoreI/OPaths(continued) ACPIPathLocationFunctionAssociatedwithPathSlot 0/0/3/0Rearpanel(withLAN 10/100label) LAN100portCoreI/O 0/1/1/0SystemboardUltra3SCSIChannelACoreI/O 0/1/1/1SystemboardUltra3SCSIChannelBCoreI/O 0/1/1/1.x.yRearpanel(withSCSI LVD/SElabel) Ultra3SCSII/O—externalSCSICoreI/O 0/1/2/0Rearpanel(withLAN GVlabel) LAN1000portCoreI/O 0/7/1/1Rearpanel(accessible thruWcable) Interfacewithexternalconsole(ECI)Consoleport 0/7/1/0Rearpanel(accessible thruWcable)...