Daewoo Dtf 2950 Service Manual
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CP-850FX Service Manual Europe R&D 40 Block diagram TDA6108JF 4.9 24C16 - 16 KB EEPROM Features : ƒ 16 Kbit serial I2C bus EEPROM ƒ Single supply voltage : 4.5 V to 5.5 V ƒ 1 Million Erase/Write cycles (minimum) ƒ 40 year data retention (minimum) Pin description Pin No. Name Description 1, 2, 3 E0, E1, E2 Device address – not used 5 SDA Serial Data/Address Input/Output 6 SCL Serial clock 7 WC Write control 8 Vcc Supply voltage 4 Vss Ground The memory device is compatible with the I2C memory standard. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The memory carries a built-in 4-bit unique device type identifier code (1010) in accordance with the I2C bus definition. Serial Clock (SCL) The SCL input is used to strobe all data in and out of the memory. Serial Data (SDA) The SDA pin is bi-directional, and is used to transfer data in or out of the memory
CP-850FX Service Manual Europe R&D 41 4.10 STR – W6754 4.10.1 GENERAL DESCRIPTION The STR-W6700 series is a Hybrid IC (HIC) designed for Quasi-Resonant type Switching Mold Power Supply built-in a Power MOSFET and Control IC. 4.10.2 FEATURES ƒ operation mode turns blocking oscillation by reducing output voltage at stand-by mode. ƒ In addition to the existing Quasi-Resonant Operation, the Bottom-Skip Function is added in order to be efficient from light to medium load. ƒ Soft-Start Operation is provided at the SMPS start-up. ƒ Switching noise is reduced by Step-Drive Function. ƒ Avalanche energy of the MOSFET is guaranteed. ƒ Overcurrent Protection (OCP), Overvoltage Protection (OVP), Overload Protection (OLP), and Maximum ON-Time control circuits are incorporated. ƒ It is possible to save the SMPS design time by utilizing the present designs and evaluation processes. 4.10.3 BLOCK DIAGRAM D S/GND OC P/BD V CC ４４ ３３ FB ＋ －＋ － Start Stop BurstRSQ Reg& Ic on s t OV P DR IV E Re g１１ ７７ A bnorm al latch S RQFB－ ＋ ＋ － OCP ＋ － BSD ＋ －BD Bottom Selector C ounter ５５ SS/OLP － ＋ OLP Delay ６６ S R Q S R QSR QOSC MaxON Soft Start Bur st C ontr olBur st C ontr ol
CP-850FX Service Manual Europe R&D 42 4.10.4 PIN DESCRIPTION 4.10.5 MOSFET ELECTRICAL CHARACTERISTICS Ratings Parameters Terminal SymbolsM I NT Y PM A XUnits Conditions Drain-Source Voltage ※ 7 1 - 3 VDSS 650― ― V Drain Leakage Current1 - 3 IDSS ― ― 300 µA ON Resistance ※7 1 - 3 RDS(ON)― ― 0.73 Ω Switching Time 1 - 3 ｔf ― ― Nsec ※6 Thermal Resistance ※7― θch-F― ― ℃/Ｗ Channel – Internal Frame Pin No. Symbols Terminal Descriptions Functions 1 D Drain Terminal MOSFET Drain 2 － 3 S/GND Source/Grand Terminal MOSFET Source and Ground 4 VCC Power Supply Terminal Control Circuit Power Supply Input 5 SS/OLP Delay at Overload/Soft- Start set up Terminal Overload Protection and Soft- Start Operation Time set up 6 FB Feedback Terminal Constant Voltage Control Signal Input, Blocking Oscillation Control 7 OCP/BD Overcurrent Protection Input/Bottom Detection Terminal Overcurrent Detection Signal Input / Bottom Detection Signal Input
CP-850FX Service Manual Europe R&D 43 4.10.6 ELECTRICAL CHARACTERISTICS Ratings Parameters TerminalSymbols MIN T Y P M A X Units ower Supply Start-up Operation Operation Start-up Voltage 4 - 3 VCC(ON) 18.2 V Operation Stop Voltage 4 - 3 VCC(OFF) 9.6 V Operation Circuit Current 4 - 3 ICC(ON) ― ― 6 mA Non Operation Circuit Current 4 - 3 ICC(OFF) ― ― 100 µA Oscillation Frequency 1 - 3 fOSC 22 kHz Soft-Start Operation Stop Voltage 5 - 3 VSSOLP(SS) 1 V Soft-Start Operation Charging Current 5 - 3 ISSOLP(SS) -450 µA ormal Operation Overcurrent Detection Threshold Voltage 7 - 3 VOCPBD(LIM) -0.95 V Bottom-Skip Operation Threshold Voltage 1 7 - 3 VOCPBD(BS1) -0.66 V Bottom-Skip Operation Threshold Voltage 2 7 - 3 VOCPBD(BS2) -0.44 V OCP/BD Terminal Outflow Current 7 - 3 IOCPBD µA Quasi-Resonant Operation Threshold Voltage 1 7 - 3 VOCPBD(TH1) 0.4 V Quasi-Resonant Operation Threshold Voltage 2 7 - 3 VOCPBD(TH2) 0.8 V Minimum Quasi-Resonant Signal Input Time 7 - 3 TOFF(MIN) ― ― 1 µsec FB Terminal Threshold Voltage 6 - 3 VFB(OFF) 1.5 V FB Terminal Inflow Current (Normal Operation) 6 - 3 IFB(ON) mA tand-by Operation Stand-by Operation Start-up Power Supply Voltage 4 - 3 VCC(S) 11.2 V Stand-by Power Supply Voltage Interval 4 - 3 VCC(SK) 1.5 V Stand-by Non-Operational Circuit Current 4 - 3 ICC(S) 30 μA FB Stand-by Operation Threshold Voltage 6 - 3 VFB(S) V FB Terminal Inflow Current (Stand-by) 6 - 3 IFB(S) µA Minimum ON Time 1 - 3 TON(MIN) 1 µsec otection Operation Maximum ON Time 1 - 3 TON(MAX) 34 µS OLP Operation Threshold Voltage 5 - 3 VSSOLP(OLP) 5 V OLP Operation Charging Current 5 - 3 ISSOLP(OLP) -10 µA Normal Operation Discharging Current 5 - 3 ISSOLP(NOR) 40 µA OLP Delay Time 1 - 3 TOLP ms OVP Operational Voltage 4 - 3 VCC(OVP) 27.5 V Latch Circuit Holding Current ※10 4 - 3 ICC(H) ― ― 150 µA Latch Circuit Releasing Power Supply Voltage ※ 10 4 - 3 VCC(La.OFF) 7.3 V
CP-850FX Service Manual Europe R&D 44 5 CP-850FX CHASSIS DESCRIPTION 5.1 POWER SUPPLY BLOCK DIAGRAM
CP-850FX Service Manual Europe R&D 45 5.2 VIDEO & STEREO AUDIO BLOCK DIAGRAM
CP-850FX Service Manual Europe R&D 46 5.3 IF SECTION 5.3.1 BLOCK DIAGRAM
CP-850FX Service Manual Europe R&D 47 5.3.2 VISION IF AMPLIFIER The video IF signal (VIF) is fed through a SAW filter to the differential input (Pin 6-7) of the VIF amplifier. This amplifier consists of three AC-coupled amplifier stages. Each differential amplifier is gain controlled by the automatic gain control (VIF-AGC). The output signal of the VIF amplifier is applied to the FPLL carrier generation and the video demodulator. SAW filters Ref. Standard Features K3953M B/G - D/K - I - L/L’ ƒ IF filter for video application ƒ TV IF filter with Nyquist slopes at 33.9 MHz and 38.9 MHz ƒ Constant group delay K9650M B/G - D/K - I - L/L’ ƒ IF filter for audio application ƒ TV IF audio filter with two channels ƒ Channel 1 (L’) with one pass band for sound carrier at 40.40 MHz ƒ Channel 2 ( L, D/K, I, B/G) with one pass band for sound carriers between 32.40 MHz and 33.40 MHz 5.3.3 TUNER-AND VIF-AGC At Pin 8, the VIF-AGC charges/discharges the AGC capacitor to generate a control voltage for setting the gain of the VIF amplifier and tuner in order to keep the video output signal at a constant level. Therefore, in the case of all negative modulated signals (e.g., B/G standard) the sync. level of the demodulated video signal is the criterion for a fast charge/discharge of the AGC capacitor. For positive modulation (e.g., L standard) the peak white level of video signal controls the charge current. In order to reduce reaction time for positive modulation, where a large time constant is needed, an additional black level detector controls the discharge current in the event of decreasing VIF input signal. The control voltage (AGC voltage at Pin 8) is transferred to an internal control signal, and is fed to the tuner AGC to generate the tuner AGC current at Pin 11 (open collector output). The take over point of the tuner AGC is adjusted at Pin 10 by an external dc voltage from microprocessor. A PWM output from microcontroller is low pass filtered for this AGC control. See also “AGC” adjustment for details on how to align TOP in SERVICE mode. 5.3.4 FPLL, VCO AND AFC The FPLL circuit (frequency phase locked loop) consists of a frequency and phase detector to generate the control voltage for the VCO tuning. In the locked mode, the VCO is controlled by the phase detector and in unlocked mode, the frequency detector is superimposed. The VCO operates with an external resonance circuit (L and C parallel) and is controlled by internal varicaps. The VCO control voltage is also converted to a current and represents the AFC output signal at Pin 22. At the AFC switch (Pin 19) three operating conditions of the AFC are possible: AFC curve “rising” or “falling” and AFC “off”. A practicable VCO alignment of the external coil is the adjustment to zero AFC output current at Pin 22. At center frequency the AFC output current is equal to zero. Furthermore, at Pin 14, the VCO center frequency can be switched for setting to the required L’ value (L’ standard). The optional potentiometer at Pin 26 allows an offset compensation of the VCO phase for improved sound quality (fine adjustment). Without a potentiometer (open circuit at Pin 26), this offset compensation is not active. The oscillator signal passes a phase shifter and supplies the in-phase signal ( °) and the quadrature signal (9 °)of the generated picture carrier.
CP-850FX Service Manual Europe R&D 48 5.3.5 VIDEO DEMODULATION AND AMPLIFIER The video IF signal, which is applied from the gain controlled IF amplifier, is multiplied with the inphase component of the VCO signal. The video demodulator is designed for low distortion and large bandwidth. The demodulator output signal passes an integrated low pass filter for attenuation of the residual vision carrier and is fed to the video amplifier. The video amplifier is realised by an operational amplifier with internal feedback and 8 MHz bandwidth (–3 dB). A standard dependent dc level shift in this stage delivers the same sync. level for positive and negative modulation. An additional noise clipping is provided. The video signal is fed to VIF-AGC and to the video output buffer. This amplifier with a 6 dB gain offers easy adaptation of the sound trap. For nominal video IF modulation the video output signal at Pin 12 is 2 Vpp. 5.3.6 SOUND IF AMPLIFIER AND SIF-AGC The SIF amplifier is nearly identical with the 3-stage VIF amplifier. Only the first amplifier stage exists twice and is switchable by a control voltage at Pin 3. Therefore with a minimal external expense it is possible to switch between two different SAW filters. Both SIF inputs features excellent cross-talk attenuation and an input impedance which is independent from the switching condition. The SIF-AGC is related to the average level of AM- or FM-carrier and controls the SIF amplifier to provide a constant SIF signal to the AM demodulator and QPS mixer. 5.3.7 QUASI-PARALLEL-SOUND (QPS) MIXER The QPS mixer is realised by a multiplier. The SIF signal (FM or NICAM carrier) is converted to the intercarrier frequency by the regenerated picture carrier (quadrature signal) which is provided from the VCO. The intercarrier signal is fed via an output amplifier to Pin 24. 5.3.8 STANDARD SWITCH To have equal polarity of the video output signal the polarity can be switched in the demodulation stage in accordance with the TV standard. Additional a standard dependent dc level shift in the video amplifier delivers the same sync. level. In parallel to this, the correct VIF-AGC is selected for positive or negative modulated VIF signals. In the case of negative modulation (e.g., B/G standard) the AM output signal is switched off. For positive modulation (L standard) the AM demodulator and QPS mixer is active. This condition allows a parallel operation of the AM sound signal and the NICAM-L stereo sound. 5.3.9 L’ SWITCH With a control voltage at Pin 14 the VCO frequency can be switched for setting to the required L’ value (L’ standard). Also a fine adjustment of the L’-VCO center frequency is possible via a potentiometer. The L’ switch is only active for positive modulated video IF-signals (standard switch in L mode). 5.3.10 INTERNAL VOLTAGE STABILISER The internal bandgap reference ensures constant performance independent of supply voltage and temperature. 5.4 VIDEO / RGB 5.4.1 FRONT END 5.4.1.1 CVBS Front-End The CVBS front-end consists of the colour-decoding circuit itself, a sync processing circuit for generation of H/V signals out of the CVBS signal, and the luminance processing. The main task of the luminance processing is to remove the colour carrier by means of a notch filter. For PAL
CP-850FX Service Manual Europe R&D 49 and SECAM operation a baseband delay line is used for U and V signals. This can be used as comb filter in NTSC operation (only for chrominance). The RGB input from SCART is used as an overlay for the CVBS channel (RGB+FBL). This block contains a matrix (for RGB signals). 5.4.1.2 Input Selector The analog CVBS or SVHS luma signal are fed to the inputs CVBS1...7 of VSP94x2A (amplitude 0.5...1.5 V pp ). One signal is selected and fed to the first ADC. A second signal (SVHS Chroma) can be selected and fed to the other ADC. After clamping to the back porch both signals are AD-converted with an amplitude resolution of 9 bit. The AD conversion is done using a 20.25 MHz free-running stable crystal clock. Before the A to D conversion the signals are lowpass filtered to avoid antialias effects. One input is looped back to output CVBSO1(#63). A signal addition is performed to output a CVBS signal even when separate Y/C signals are used at input. 5.4.1.3 Signal Levels And Gain Control To adjust to different CVBS input voltages a digitally working automatic gain control is implemented. Input voltages in the range between 0.6 to 1.8 V pp can be applied to the CVBS inputs. 5.4.1.4 Synchronization After elimination of the high frequent components of the CVBS signal by a low pass filter, horizontal and vertical sync pulses are separated. Horizontal sync pulses are generated by a digital phase locked loop. The time constant is adjusted between fast and slow behaviour to accommodate different input sources (e.g. VCR). 5.4.1.5 Chroma Decoder The digital multistandard chroma decoder is able to decode NTSC and PAL signals with a subcarrier frequency of 3.58 MHz and 4.43 MHz as well as SECAM signals with automatic standard detection. The TV controller software has configured the colour decoder to operate in automatic detection mode. When the signal source comes from the tuner, only SECAM and PAL (50Hz) standard are enabled. In AV mode or when program number 0 is selected the following standards are also enabled : NTSC M, NTSC 4.43 and PAL 60. The demodulation is done with a regenerated colour-carrier. 5.4.1.6 Luminance Processing A luminance notch filter is implemented to separate the chroma information from the luminance. Depending on the colour standard, one out of three different notch characteristics is chosen (’PAL’, ’NTSC’, ’SECAM’) automatically. 5.4.1.7 RGB Front-End An analogue RGB input port for an external RGB source is available. The incoming signal is clamped to the back porch by a clamping pulse. This input as an overlay input (soft mix). The RGB signal must then be synchronised to the main CVBS/YC signal. 5.4.1.8 Signal Processing 5.3.1.8.1 Horizontal Prescaler The main application of the horizontal prescaler is the conversion of the number of pixels coming form the 40.5/20.25 MHz pixel clock domain down to the number of pixels stored in the memory (factor 2/3). Generally the number of incoming pixels can be decimated by a factor between 1 and 64 in a granularity of 2 output pixels. The horizontal scaler reduces the number of incoming