Daewoo Dtf 2950 Service Manual
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CP-850FX Service Manual Europe R&D 20 23 IR IN Remote control signal input 24 INT IN Interrupt input from audio processor 25 n.c. 26 n.c. 27 n.c. 28 n.c. 29 VSS IN Ground (0V) 30 VDD3.3 IN Input/Output 3.3V 31 n.c. 32 n.c. 33 RESET IN A low level on this pin resets the device. 34 XTAL2 OUT Output of the inverting oscillator amplifier 35 XTAL1 IN Input of the inverting oscillator amplifier 36 VSSA IN Ground for analog components 37 VDDA2.5 IN Supply voltage for analog components 38 R OUT OUT Red output 39 G OUT OUT Green output 40 B OUT OUT Blue output 41 BK OUT OUT Blanking 42 VDD2.5 IN Supply voltage 2.5V 43 VSS IN Ground (0V) 44 VDD3.3 IN Input / Output 3.3V 45 n.c. 46 n.c. 47 n.c. 48 AGC OUT Tuner TOP adjustment 49 n.c. 50 n.c. 51 LED OUT High : Green LED, Low : Red LED 52 POWER OUT High : SMPS ON, Low : SMPS in stand by
CP-850FX Service Manual Europe R&D 21 4.2 VSP94x5B (version C4)– OPTIMUS Color Decoder and Scan-Rate Converter The VSPB family supports 15/32kHz systems and is available with different options. VSP 94x5B has one channel only. 4.2.1 BLOCK DIAGRAM OF THE VSP94x5B
CP-850FX Service Manual Europe R&D 22 4.2.2 Feature Overview - Different application modes z FSM : Frame based high performance master with PIP z SSC : Split screen (Double Window) - Data acquisition connectivity z Up to seven (VSP 9425B/9427B: nine) CVBS inputs, up to two Y/C inputs z Up to three CVBS outputs (even when Y/C input) z ITU-R 656 compatible digital input z RGB/FBL or YUV or YUV-H-V input z 9 bit amplitude resolution for CVBS/Y/C A/D converter z 8 bit amplitude resolution for RGB/FBL A/D converter - Multi-standard color decoder with 4H comb-filter z PAL/NTSC/SECAM including all substandard z Automatic recognition of chroma standard z AGC (Automatic Gain Control) - Temporal noise reduction for master and slave channel z Field or frame based temporal noise reduction for luminance and chrominance - Pre-scaling of the 1f H signal z Horizontal scaling factors: 3/2...1...1/28 z Vertical scaling factors: 1...1/30 - Horizontal and vertical scaling of the 2f H signal z Horizontal Scaling factors: 3...0.75 z 5 zone horizontal panorama generator - Vertical scaling of the 2f H signal z Vertical scaling factors: 8...0.92 z 5 zone vertical panorama generator - Detection circuits z Global motion and global still detection z Film mode and phase detection (PAL, NTSC; 2-2, 3-2 pull down) z Measurement of the noise level (blanking) z Detection of letter box formats - Embedded memory z On-chip memory controller z Embedded DRAM core for field memory z SRAM for delay lines - Data format 4:2:2 - Data slicer for closed caption (V-chip) and WSS - Flexible clock and synchronization concept z Horizontal line-locked or free-running mode z Vertical locked or free-running mode - Scan-rate-conversion z Motion adaptive frame based 100/120 Hz interlaced scan-rate conversion z Motion adaptive frame based 50/60 Hz progressive scan-rate conversion z Special treatment for film material (Inverse 3-2 pull down) z Large area and line flicker reduction z Simple progressive modes: AB, AA* z Simple interlaced modes (100/120 Hz): ABAB, AABB, AAAA, BBBB z No scan-rate-conversion modes (50/60 Hz): AB, AA, BB - Signal manipulations z Still field or still frame z Insertion of colored background
CP-850FX Service Manual Europe R&D 23 z 2D and 3D frames for master and slave channel z Vertical chrominance shift for improved VCR picture quality z Contrast, brightness and saturation control - Sharpness improvement z Digital color transition improvement (DCTI) z Adaptive horizontal and vertical peaking (luminance) z Digital luminance transition improvement (DLTI) z Digital contrast improvement (DCI, master channel only) - Three D/A converters - 9 bit amplitude resolution for YUV, RGB output - (Nominal) 72 MHz clock frequency with two-fold oversampling - I2C bus control (400 kHz) - 1.8 V± 5% and 3.3 V ± 5% supply voltages - PMQFP80-1 or PMQFP144-1 packages - Only one crystal necessary for whole IC and all color standards 4.2.3 PINNING Pin Name I/O Description 1 VDDDACY S DAC(Y) 2 AYOUT O Y output 3 VSSDACY S DAC(Y) 4 VSSD2 S Supply voltage for digital (0V digital) 5 VDDD2 S Supply voltage for digital(1.8V digital) 6 SDA I/O I2C-Bus data 7 TMS I Testmode select (Connected to vdd33) 8 656VIN/BLANK I/O Separate V input for 656 / BLANK output 9 656CLK I/O Digital input / output clock 10 656IO7 I/O Digital input / output (MSB) 11 VSSP2 S Supply voltage for digital (0 V pad) 12 VDDP2 S Supply voltage for digital (3.3 V pad) 13 SCL I I2C-Bus clk 14 V I Vertical pulse for RGB input 15 656IO6 I/O Digital input / output 16 656IO5 I/O Digital input / output 17 HOUT O Horizontal output 18 H50 O Hout 50 Hz 19 ADR / TDI I I2C address / test data in 20 V50 O Vout 50 Hz 21 656IO4 I/O Digital input / output 22 656IO3 I/O Digital input / output 23 VOUT O Vertical output 24 RESET I Reset input (Reset active low) 25 VDDP3 S Supply voltage for digital (3.3 V pad) 26 VSSP3 S Supply voltage for digital (0 V pad) 27 CLKOUT O Output clock (27 MHz nom.) 28 VDDD3 S Supply voltage for DRAM (1.8 V digital) 29 VSSD3 S Supply voltage for digital (0 V digital) 30 656IO2 I/O Digital input / output 31 656IO1 I/O Digital input / output 32 656IO0 I/O Digital input / output (LSB)
CP-850FX Service Manual Europe R&D 24 33 VSSD4 S Supply voltage for digital (0 V digital) 34 VDDD4 S Supply voltage for digital 1.8 V digital 35 VDDAFBL S Supply voltage for FBL (1.8 V) 36 VSSAFBL S Supply voltage for FBL (0 V) 37 FBL1 I Fast Blank input 1 (H1) (Analog input) 38 FBL2 I Fast Blank input 2 (H2) (Analog input) 39 RIN1 I R or V in1 (Analog input) 40 GIN1 I G or Y in1 (Analog input) 41 BIN1 I B of U in1 (Analog input) 42 VDDARGB S Supply voltage for RGB (1.8 V) 43 VDDARGB S Supply voltage for RGB (0 V) 44 VDD33RGB S Supply voltage RGB (3.3 V) 45 VDD33RGB S Supply voltage RGB (0 V) 46 RIN2 I R or V in2 (Analog input) 47 GIN2 I G or Y in2 (Analog input) 48 BIN2 I B of U in2 (Analog inpu) 49 VSSD5 S Supply voltage for digital (0 V) 50 VDDAC1 S Supply voltage CVBS1 (1.8 V) and digital core supply 51 VSSAC1 S Supply voltage CVBS1 (0 V) 52 CVBS1 I CVBS input (Analog input) 53 CVBS2 I CVBS input (Analog input) 54 CVBS3 I CVBS input (Analog input) 55 CVBS4 I CVBS input or Y1 (Analog input) 56 CVBS5 I CVBS input or C1 (Analog input) 57 CVBS6 I CVBS input or Y2 (Analog input) 58 CVBS7 I CVBS input or C2 (Analog input) 59 VDD33C S Supply voltage CVBS (3.3 V) 60 VSS33C S Supply voltage CVBS (0 V) 61 CVBSO3 O CVBS output 3 (Analog output) 62 CVBSO2 O CVBS output 2 (Analog output) 63 CVBSO1 O CVBS output 1 (Analog output 64 VDDAC2 S Supply voltage CVBS2 (1.8 V) 65 VSSAC2 S Supply voltage CVBS2 (0 V) 66 VDDD1 S Supply voltage for digital (1.8 V digital) 67 VSSD1 S Supply voltage for digital (0 V digital) 68 VDDAPLL S Supply voltage for PLL (1.8 V) 69 XOUT O Crystal connection 2 70 XIN I Crystal connection 1 71 TCLK I Testclock 72 VDDP1 S Supply voltage for digital (3.3 V pad) 73 VSSP1 S Supply voltage for digital (0 V pad) 74 656HIN/CLKF20 I/O Separate H input for 656 / 20.25 clock output 75 VDDDACV S DAC (V) 76 AVOUT O V output 77 VSSDACV S DAC (V) 78 VDDDACU S DAC (U) 79 AUOUT O U output 80 VSSDACU S DAC (U)
CP-850FX Service Manual Europe R&D 25 4.3 DDP 3315C – DISPLAY AND DEFLECTION PROCESSOR The DDP 3315C is a mixed-signal single-chip digital display and deflection processor, designed for high-quality backend applications in double scan and HDTV TV sets with 4:3 or 16:9 picture tubes. The interfaces qualify the IC to be combined with state of the art digital scan rate converters, as well as analog HDTV sources. The DDP 3315C contains the entire digital video component, deflection processing, and all analog interfaces to display the picture on a CRT. 4.3.1 BLOCK DIAGRAM OF THE DDP 3315C 4.3.2 DESCRIPTION Video Processing – linear horizontal scaling (0.25 ... 4), as well as nonlinear horizontal scaling “panorama vision” – dynamic black level expander – luma sharpness enhancement by dynamic peaking and luma transient improvement (LTI) – color transient improvement (CTI) – programmable RGB matrix – black stretch, blue stretch, gamma correction via programmable Non-linear Colorspace Enhancer (NCE) on RGB – two analog double scan inputs with fast blank (one RGB and one RGB/YC r C b /YP r P b selectable) – average and peak beam current limiter – automatic picture tube adjustment (cutoff, drive) – histogram calculation Deflection Processing – scan velocity modulation output – digital EHT compensation for vertical / east-west – soft start/stop of horizontal-drive – vertical angle and bow correction – differential vertical outputs – vertical zoom via deflection adjustment – horizontal and vertical protection circuit
CP-850FX Service Manual Europe R&D 26 – horizontal frequency for VGA/SVGA/1080I – black switch off procedure – supports horizontal and vertical dynamic focus Miscellaneous – selectable ITU-R 601 4:1:1 / 4:2:2 YC r C b input at 27/32 MHz or double scan ITU-R 656 input at 54 MHz line-locked clock – crystal oscillator for horizontal safety – picture frame generator – hardware for simple 50/60 Hz to 100/120 Hz conversion (display frequency doubling) – PQFP80 package, 5 V analog and 3.3 V digital supply IC architecture A clock generator converts different external line locked clock rates to a common internal sample rate of ~40 MHz, in order to provide a higher horizontal resolution. The input interface accepts ITU-R 601 at 27 or 32 MHz and ITU-R 656 with encoded or external sync at 54 MHz. The horizontal scaler is used for the scan rate conversion and for the nonlinear aspect ratio con- version as well. For the picture improvement, luma and chroma are processed separately. The luminance contrast ratio can be extended with a dynamic black level expander. In addition the frequency characteristic is improved by a transient improvement (LTI) and an adaptive dynamic peaking circuit. The peaking adapts to small AC amplitudes of high frequency parts, while large AC amplitudes are processed by the LTI. The chroma signal is enhanced with a transient improvement (CTI) with proper limitation to avoid wrong colours. The full programmable RGB matrix covers control of colour saturation and temperature. A digital white drive control is used to adjust the white balance and for the beam current limitation to prevent the CRT from over-load. A non-linear colorspace enhancer (NCE) for RGB gives full flexibility for any amplitude characteristic. High speed10-bit D/A converters are used to convert digital RGB to analog signals. Separate 9- bit D/A converters control brightness and cutoff. For picture tubes equipped with an appropriate yoke a scan velocity modulation (SVM) signal is calculated using a differentiated luminance signal. Two analog sources can be inserted in the main RGB, controlled by separate fastblank (FBL) signals. Contrast and brightness are adjusted separately from main RGB. One input is dedicated to RGB for on screen display (OSD). The second input is processed with an analog RGB matrix to insert YC bCr/YpbPr or RGB with control of colour saturation and programmable half contrast. The bandwidth of ~30MHz guarantees pixel based graphics to be displayed with full accuracy. All previously mentioned features are implemented in dedicated hardware. An integrated processor controls the horizontal and vertical deflection, tube measurement loops and beam current limitation. It is also used to calculate an amplitude histogram of the displayed image. The horizontal deflection is synchronized with two numeric phase-locked loops (PLL) to the incoming sync. One PLL generates the horizontal timing signals, e.g. blanking and key-clamping. The second PLL adjusts the phase of the horizontal drive pulse with a subpixel accuracy less than 1 ns. Vertical deflection and east/west correction waveforms are calculated as 6th order polynomials. This allows adjustment of an east/west parabola with trapezoidal, pincushion and an upper/lower corner correction (even for real flat CRT’s), as well as a vertical sawtooth with linearity and S- correction. Scaling both waveforms, and limiting to fix amplitudes, performs a vertical zoom or compression of the displayed image. A field and line frequent control loop compensates picture content depending EHT distortions.
CP-850FX Service Manual Europe R&D 27 4.3.3 PINNING Pin No. Pin Name I/O Description Remarks 1 Y6 I Picture bus Luma 2 Y7 I Picture bus Luma (MSB) 3 656EN I Enable 656 input mode 4 LLC2 I System clock input 5 HS I Horizontal Sync Input 6 VS I Vertical Sync Input 7 FREQSEL I Selection of H-Drive Frequency Range 8 CM1 I Clock select 1 9 CM0 I Clock select 0 10 VS2 I Additionnal VSYNC input 11 XTAL2 O Analog Crystal Output 12 XTAL1 I Analog Crystal Input 13 NC 14 GNDP S Ground, Output Pin Driver 15 VSUPP S Supply voltage, Output Pin Driver 16 FIFORRD O FIFO Read Counter Reset 17 FIFORD O FIFO Read Enable 18 FIFOWR O FIFO Write Enable 19 FIFORWR O FIFO Write Counter Reset 20 PWM1 O I2C controlled DAC 21 PWM2 O I2C controlled DAC / Tilt output 22 PWMV O I2C controlled DAC 23 HOUT O Horizontal drive output 24 VSTBY S Standby supply voltage, Hout generation 25 DFVBL O Dynamic focus blanking / horizontal DAF pulse 26 HSYNC O Horizontal sync output 27 VSYNC O Vertical sync output 28 NC 29 ASG1 S Analog Shield Ground 30 HFBL I Horizontal flyback input 31 SAFETY I Safety input 32 VPROT I Vertical protection input 33 RSW2 O Range Switch2, measurement ADC 34 RSW1 I/O Range Switch1, measurement ADC 35 SENSE I Sense ADC input 36 GNDM S Ground, MADC input 37 VERT+ O Differential Vertical Sawtooth Output 38 VERT- O Differential Vertical Sawtooth Output 39 EW O East / West Correction Output 40 NC 41 SVM O Scan Velocity Modulator 42 ROUT O Analog Output Red 43 GOUT O Analog Output Green 44 BUT O Analog Output Blue 45 GNDO S Ground, analog Back End 46 XREF I Reference Input for RGB DAC’s 47 VSUPO S Supply voltage, Analog Back End
CP-850FX Service Manual Europe R&D 28 48 VRD/BCS I DAC Reference, Beam current safety 49 AGND S Analog Ground for Analog Matrix 50 FBLIN1 I Fast Blank1input 51 RIN1 I Analog Red1input 52 GIN1 I Analog Green1 input 53 BIN1 I Analog Blue1input 54 FBLIN2 I Fast Blank2 input 55 RIN2 / PR I Analog Red2 input / PR Input 56 GIN2 / Y I Analog Green2 input / Y Input 57 BIN2/ PB I Analog Blue2 input / PB Input 58 ASG2 S Analog Shield Ground 59 HCS I Half Contrast 60 NC 61 TEST I 62 RESQ I Reset Input, active low 63 SCL I/O I2C Bus clock 64 SDA I/O I2C Bus data 65 C0 I Picture Bus Chroma (LSB) 66 C1 I Picture Bus Chroma 67 C2 I Picture Bus Chroma 68 C3 I Picture Bus Chroma 69 C4 I Picture Bus Chroma 70 C5 I Picture Bus Chroma 71 C6 I Picture Bus Chroma 72 C7 I Picture Bus Chroma (MSB) 73 VSUPD S Supply voltage, Digital Circuitry 74 GNDD S Ground, Digital Circuitry 75 Y0 I Picture Bus Luma (LSB) 76 Y1 I Picture Bus Luma 77 Y2 I Picture Bus Luma 78 Y3 I Picture Bus Luma 79 Y4 I Picture Bus Luma 80 Y5 I Picture Bus Luma
CP-850FX Service Manual Europe R&D 29 4.4 MSP341X MULTISTANDARD SOUND PROCESSOR The MSP 341x is designed as a single-chip Multistandard Sound Processor for applications in analogue and digital TV sets, video recorders, and PC cards. The MSP3411 has all functions of MSP3410 with the addition of a virtual surround sound features. Surround sound can be reproduced to a certain extent with two loudspeakers. The MSP3411 includes virtualizer algorithm “3D Panorama” which has been approved by the Dolby laboratories for compliance with the “Virtual Dolby Surround” technology. In addition, the MSP3411 includes Micronas “Panorama” algorithm. MSP 341x features: ƒ sound IF input ƒ No external filters required ƒ Stereo baseband input via integrated AD converters ƒ Two pairs of DA converters ƒ Two carrier FM or NICAM processing ƒ AVC : Automatic Volume Correction ƒ Bass, treble, volume processing ƒ Full SCART in/out matrix without restrictions ƒ Improved FM-identification ƒ Demodulator short programming ƒ Auto-detection for terrestrial TV - sound standards ƒ Precise bit-error rate indication ƒ Automatic switching from NICAM to FM/AM or vice versa ƒ Improved NICAM synchronisation algorithm ƒ Improved carrier mute algorithm ƒ Improved AM-demodulation ƒ Reduction of necessary controlling ƒ Less external components 4.4.1 BASIC FEATURES OF THE MSP 341X 4.4.1.1 Demodulator & NICAM Decoder Section The MSP 341x is designed to simultaneously perform digital demodulation and decoding of NICAM-coded TV stereo sound, as well as demodulation of FM or AM mono TV sound. Alternatively, two carrier FM systems according to the German terrestrial specs can be processed with the MSP 341x. The MSP 341x facilitates profitable multistandard capability, offering the following advantages: ƒ Automatic Gain Control (AGC) for analogue input: input range: 0.10 - 3 Vpp ƒ integrated A/D converter for sound-IF input ƒ all demodulation and filtering is performed on chip and is individually programmable ƒ easy realisation of all digital NICAM standards (B/G, I, L and D/K) ƒ FM-demodulation of all terrestrial standards (include identification decoding) ƒ no external filter hardware is required ƒ only one crystal clock (18.432 MHz) is necessary ƒ high deviation FM-mono mode (max. deviation: approx. ±360 kHz)