Asus S62 Service Guide
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BIOS SPECIFICATION 6-7 4. BIOS Features 4.1 SYSTEM SECURITY The functions of all passwords are listed in following table. Table 4-1 Password Function Password Function UserSupervisorHard Disk Access all setup items V Access only part of setup items V Enter system V Unlock a hard disk V Disable “lock” of a hard disk V Here are some other rules should be followed: If supervisor password is enabled, BIOS...
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BIOS SPECIFICATION 6-8 The configuration index/data I/O ports are 2Eh/2Fh. And only Parallel Port function is enabled by BIOS. The Parallel Port Mode can be adjusted in BIOS SETUP MENU during POST. Table 4.4 shows all modes supported by BIOS. Table 4.4 Parallel Port Mode supported by BIOS Parallel Port Mode 1 SPP/Bi-Directional 2 EPP/SPP 3 ECP 4 ECP/EPP 4.5 RESOURCE ALLOCATION The system resources are allocated as follows at...
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BIOS SPECIFICATION 6-9 LAN Controller Dynamic D800~D8FF IRQ16 FE8FEC00~ FE8FECFF Wireless (802.11abg) Static IRQ17 FDFFF000~ FDFFFFFF Ricoh MS Dynamic IRQ19 FE8FF000~ FE8FF0FF Ricoh SD Dynamic IRQ19 FE8FF400~ FE8FF4FF Note: The resources of dynamic devices will be changed if users change the settings. The IRQ 9 is reserved for SCI of ACPI O.S. 4.6 POWER MANAGEMENT In addition to C1, C2/C2E, C3 and C4/C4E states...
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BIOS SPECIFICATION 6-10 Power Scheme AC Power DC Power Home/office Desk None Adaptive Portable/Laptop Adaptive Adaptive Presentation Adaptive Degrade Always On None None Minimal Power Management Adaptive Adaptive Max Battery Adaptive Degrade Three control methods that are implemented to support Windows XP Native Processor Performance Control. _PCT Processor performance control object. _PSS The number of supported processor...
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BIOS SPECIFICATION 6-11 THRM Throttle On Threshold 95 CPU THRM_ON THRM Throttle Off Threshold 90 CPU THRM_OFF Fan Failure Temp Point 65 CPU FANERR Fan Stop Threshold 50 CPU FSP STEP Trip Point 1 55 CPU TS1 STEP Trip Point 2 60 CPU TS2 STEP Trip Point 3 65 CPU TS3 STEP Trip Point 4 70 CPU TS4 STEP Trip Point 5 75 CPU TS5 STEP Trip Point 6 80 CPU TS6 STEP Trip Point 7 85 CPU TS7 STEP Trip Point 8 90 CPU...
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BIOS SPECIFICATION 6-12 4.8 NUMERIC PAD CONTROL There is a control switch in setup menu item for enabling or disabling numeric pad lock of an internal keyboard. 4.9 TOUCH PAD CONTROL In ACPI environment, BIOS will notify ATK0100 to enable/disable Touch Pad when the Touch Pad Enable/Disable instant key is pressed. 4.10 HOTKEY USAGE DURING POST The hot keys used during POST are: Hotkey Description 1 TAB Switch from “LOGO”...
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BIOS SPECIFICATION 6-13 5. GPIO Pin Assignment The following tables are the definition of GPIO pins. Some of GPIO pins need to be initialized by system BIOS and some of them need the driver to support. Please check the Description column for reference. Table 5-1. ICH7-M GPIO Definition GPIO Ty p e Name Usage PowerDescription 0 I GPIO00/BM_BUSY# BM_BUSY# M Native Function 1 I GPIO01/REQ5# REQ5# M Native Function 2 I GPIO02/PIRQE#...
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BIOS SPECIFICATION 6-14 41 N/A GPIO41 N/A N/A N/A 42 N/A GPIO42 N/A N/A N/A 43 N/A GPIO43 N/A N/A N/A 44 N/A GPIO44 N/A N/A N/A 45 N/A GPIO45 N/A N/A N/A 46 N/A GPIO46 N/A N/A N/A 47 N/A GPIO47 N/A N/A N/A 48 O GPIO48/GNT4# GNT4# M Native Function 49 O CPUPWRGD H_PWRGD M Processor I/F power well 1. Power field: M -> main power will, R-> resume power well 2. pins in light gray: used as Native Function pins 3. pins in gray: no function...
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BIOS SPECIFICATION 6-15 Table 5-2. KBC GPIO Definition Port I/O Ty p e Input Pin Pull-up/down Name Output Pin Default Value Description A.0 O BRIGHT_PWM Low Used to adjust LCD backlight A.1 NC A.2 O BAT1_CNT1# High BAT1_CNT1# signal to battery A.3 NC A.4 O CHG_LED_UP# High When battery is charging, charging LED will be turned on by this pin A.5 O PWR_LED_UP# High When system is powered on, power LED...
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BIOS SPECIFICATION 6-16 G. 0 A FA16 To FLASH I/F G. 1 A FA17 To FLASH I/F G. 2 A FA18 To FLASH I/F G. 3 NC G. 4 O THRM_CPU# Low THRM_CPU# signal from external thermal sensor G. 5 NC G. 6 I PMTHERM# Low PMTHERM# signal to ICH7-M G. 7 NC H.0 O VSUS_ON Low VSUS_ON signal to power circuit H.1 I VSUS_GD# VSUS_GD# signal from power circuit H.2 I IMVPOK# IMVPOK# signal from power circuit...