Acer Extensa 900 Maintenance Manual

							                                                                                                            Theory of Operation  4-15  
functions. All popular 5.25-inch and 3.5-inch floppy disk drives, including the 2.88 MB, 
3.5-inch floppy disk drive, are supported. In addition, automatic media sense and 
2 Mbps tape drive support are provided by the FDC.
The two UAR Ts are fully NS16450 and NS16550 compatible. Both ports support MIDI 
baud rates and one port also supports IrDA 1.0 SIR (with data rate of 115.2 Kbps), IrDA 
1.1 MIR and FIR (with data rate of 1.152 Mbps and 4.0 Mbps respectively), and Sharp 
SIR (with data rate of 38.4 Kbps respectively) compliant signaling protocol.
The parallel port is fully IEEE 1284 level 2 compatible. The SPP (Standard Parallel Port) 
is fully compatible with ISA and EISA parallel ports. In addition to the SPP, EPP 
(Enhanced Parallel Port) and ECP (Extended Capabilities Port) modes are supported by 
the parallel port.
A set of configuration registers are provided to control the Plug and Play and other 
various functions of the PC87338. These registers are accessed using two 8-bit wide 
index and data registers. The ISA I/O address of the register pair can be relocated using 
a power -up strapping option and the software configuration after power -up.
When idle, advanced power management features allows the PC87338 to enter 
extremely low power modes under software control. The PC87338 operates at a 3.3/5V 
power supply.
4.2.7.1.1 PC87338 Features
¨100% compatible with ISA, and EISA architectures
¨Floppy Disk Controller
¨Software compatible with the DP8473, the 765A and the N82077
¨16-byte FlFO (disabled by default)
¨Burst and Non-Burst modes
¨Perpendicular Recording drive support
¨New high-performance internal digital data separator (no external filter 
components required)
¨Low-power CMOS with enhanced power-down mode
¨Automatic media-sense support, with full IBM TDR (Tape Drive Register) 
implementation
¨Supports fast 2 Mbps and standard 1 Mbps/500 kbps/250 kbps tape drives
¨Bidirectional Parallel Port
¨Enhanced Parallel Port (EPP) compatible 
						

							4-16   Theory of Operation
¨Extended Capabilities Port (ECP) compatible, including level 2 support
¨Bidirectional under either software or hardware control
¨Compatible with ISA, and EISA, architectures
¨Ability to multiplex FDC signals on parallel port pins allows use of an external 
Floppy Disk Drive (FDD)
¨Includes protection circuit to prevent damage to the parallel port when a 
connected printer is powered up or is operated at a higher voltage
¨UARTs
¨Software compatible with the PC16550A and PC16450
¨MIDI baud rate support
¨Infrared support on UART2 (IrDA 1.0 SIR, IrDA 1.1 MIR and FIR, and Sharp SIR) 
¨Address Decoder
¨6 bit or 10 bit decoding
¨External Chip Select capability when 10 bit decoding
¨Full relocation capability (no limitation)
¨Enhanced Power Management
¨Special configuration registers for power-down
¨Enhanced programmable power-down FDC command
¨Auto power-down and wake-up modes
¨2 special pins for power management
¨Typical current consumption during power-down is less than 10 mA
¨Reduced pin leakage current
¨Voltage support
¨3.3/5V operation
¨General Purpose Pins
¨1 pin, for 2 separate programmable chip select decoders, can be programmed 
for game port control
¨Plug and Play Compatible 
						

							                                                                                                            Theory of Operation  4-17  
¨16 bit addressing (full programmable)
¨10 selectable IRQs
¨4 selectable DMA Channels
¨3 SIRQ Inputs allows external devices to mapping IRQs
¨100-pin TQFP package - PC87338VJG
4.2.8 Hard Disk Drive Subsystem
The Hard Disk Drive Subsystem, implemented on the Main Board Board and on the 
associated hard disk drive module(s), provides disk storage for all system software and 
user files.
The notebook is equipped with a high-capacity hard disk drive. The hard disk drive also 
features built-in power conservation features configured from the standard CMOS 
Setup Routine. An Automatic Power Down mode can be selected which powers down 
the drive motor during periods of inactivity. An additional level of power conservation 
may also be selected which powers down the motor plus all control circuits.
The hard disk drives are factory formatted as a single drive (Drive C:) and are preloaded 
with installation versions of Windows 95 or Windows for Workgroups (in dual load 
versions, the user selects operating system during software installation).
The Hard Disk Controller is implemented with the PCIO643 Controller Chip described 
in greater detail in the following paragraph.
4.2.8.1 PCI0643 Features
¨
Capable of 16 MB/second transfer rates in DMA mode - up to 20 MB/second 
in PIO mode
¨Supports bus master DMA at 133 MB/second PCI burst rate
¨Support PCI DMA transfers for both DMA-capable and PIO-only drives
¨Fully supports ATAPI DMA/PIO transfers
¨2 channels - supports up to 4 IDE drives
¨Surpasses and supports Enhanced IDE Mode 3, Mode 4 and propose Mode 5 
timing from the widest range of disk drive manufacturers
¨Supports multi-word and single-word DMA modes 0, 1 and 2
¨Fully supports the latest PCI-IDE specification and all the Plug-and-Play (PnP) 
specifications.
¨Supports Windows 95, Windows NT 3.1 and 3.5 (Daytona), and OS/2™ 
						

							4-18   Theory of Operation
¨CMDs complete set of 32-bit drivers handle both DMA and PIO
¨Fully compatible with the latest PCI, PCI IDE, ATA-2, Enhanced IDE, Fast IDE, 
ATAPI, plug and play, and ATA-2 Power Management Feature Set
¨Fully supports all ATAPI-compatible devices, including CD-ROM, tape, MO, and 
other devices
¨Fully supports legacy (IRQ 14 and 15)
¨Hardware and software mode switching and chip enable/disable capabilities
¨Programmable read-ahead and write-back buffers enhance transfer rates
¨Fully compatible with all major operating systems
¨100-pin PQFP
4.2.9 Floppy Disk Drive Subsystem
The Extensa 900 is equipped with a 3.5-inch floppy disk drive that can read/write 
standard 3.5-inch disks (either1.44 MB or 2 MB capacity). The drive can also read a 
720 KB disk (for interchange of data with other computers).
The data transfer rate for the floppy disk drive is 500 Kbits per second for high-density 
disks and 250 Kbits per second for double-density disks.
The floppy drive controller is implemented on the PC87338 Super I/O Controller chip 
described in the previous paragraphs.
4.2.10 PCMCIA Subsystem
The notebook is equipped with a PCMCIA subsystem that accomodates either two 
Type I or Type II PCMCIA cards or one Type III card. The heart of the PCMCIA Subsystem 
is the TI PCI 1130 high-performance PCI-to-PC Card controller that supports two 
independent PC Card sockets compliant with the 1995 PC card standard. The PCI 1130 
provides a set of features that make it ideal for bridging between PCI and PC Cards in 
both notebook and desktop computers. The 1995 PC Card standard retains the 16-bit 
PC Card specification defined in PCMCIA release 2.1 and defines the new 32-bit PC 
Card, called CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI 1130 
supports any combination of 16-bit and CardBus PC Cards in its two sockets, powered 
at 3.3V or 5V as required.
The PCI 1130 is compliant with the PCI local bus specification revision 2.1, and its PCI 
interface can act as either a PCI master device or a PCI slave device. The PCI bus 
mastering is initiated during 16-bit PC Card DMA transfers or CardBus PC Card bus 
mastering cycles.
All card signals are internally buffered to allow hot insertion and removal without 
external buffering. The PCI 1130 internal data path logic allows the host to access  
						

							                                                                                                            Theory of Operation  4-19  
8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. 
Independent 32-bit write buffers allow fast-posted writes to improve system-bus 
utilization.
An advanced CMOS process is used to achieve low system-power consumption while 
operating at PCI clock rates up to 33 MHz. Several low-power modes allow the host 
power -management system to further reduce power consumption.
4.2.10.1 PCI 1130 Features
¨
3.3V core logic with universal PCI interface compatible with 3.3V or 5V PCI 
signaling environments
¨Supports PCI Local Bus specification 2.1
¨Mix and match 3.3V/5V PC card 16 cards and 3.3V CardBus cards
¨Supports two PC card or CardBus slots with hot insertion and removal
¨1995 PC Card standard compliant
¨Low-Power advanced submicron CMOS technology
¨Uses serial interface to Texas Instruments (TI) tps2202a dual power switch
¨System interrupts can be programmed as PCI-Style or ISA IRQ-Style interrupts
¨ISA IRQ interrupts can be serialized onto a single IRQSER pin
¨Independent read and write buffers for each direction
¨Supports burst transfers to maximize data throughput on the PCI and CardBus 
bus
¨Multifunction PCI device with separate five PCI Memory Windows and two I/O 
Windows available to each PC Card 16 socket
¨Two l/O Windows and two memory windows available to each CardBus socket
¨CardBus Memory Windows can be individually selected prefetchable or non-
PREFETCHABLE
¨ExchangeableCard (ExCAT)-compatible registers are mapped in memory and 
I/O space
¨TI extension registers are mapped in the PCI configuration space
¨Intel 82365SL DF register compatible
¨Supports 16-bit distributed Direct Memory Access (DMA) on both PC Card 
sockets 
						

							4-20   Theory of Operation
¨Supports PC/PCI DMA on both PC Card sockets
¨Supports Zoom Video Mode
¨Supports Ring Indicate
¨Packaged in 208-pin Thin Plastic Quad Flatpack (PDV)
4.2.11   Power Subsystem
The notebook is equipped with a software/hardware monitored/controlled Power 
Subsystem that minimizes battery usage for prolonged battery operation and 
automatically recharges the batteries when the notebook is used with an AC adapter.
The control for the power subsystem is implemented with the ALI M6377 Power 
Management Unit chip as described below.
A simplified block diagram of the power subsystem is shown in Figure 4-3. 
						

							                                                                                                            Theory of Operation  4-21  
Figure 4-3  Power Subsystem Simplified Block Diagram
UMA
DC/DC CONVERTER
DCBATOUT
CHARGER
8MB
DRAM/
DIMM*1
M+5V
M+3.3V
HDD/
CD
FDD
PCI1130SW
SWM1521
M1523
9088MAL
CPU
+3.3V
SW M+5V
SW
+2.9VM+2.9V
SW M+7V
AUDIO_VDDES1878S
SW
FLASH
ROM
+12V M+12V
+3.3V
+5V
+3.3V
+5V
+5V VGA_VDD M+5V
M+3.3V
M+5V
M+5V
L2 CACHE
HDD
PCI064387338
+5V
M6375
M38813
65550/S3VRAMRESUME
GLUE
LOGIC
M+5V
MAX213
SW
PCI0643
+3.3V +12V+5V SW
AD +
BAT+AD +
BAT+
SW
LCD
CD/DC2
CD_5V
NotebookMPB
CHARGER
ADVANCED
PCI CARD 
						

							4-22   Theory of Operation
4.2.11.1 ALI M6377 Power Management Unit
The major features of the ALI M6377 Power Management Unit include:
¨Three operation states
— ON state
— DOZE state
— SLEEP state
¨Programmable DOZE and SLEEP timers
¨Programmable EL timer for backlight control
¨Three output pins depending on operation state, each pin is programmable and 
power configurable.
¨Provide system activity monitoring, including:
¨Video
¨Hard disk drive
¨Floppy disk drive
¨Serial port
¨Keyboard
¨Parallel port
¨Two programmable I/O groups activity monitor, each group contains 16/8
I/O addresses.
¨One predefined I/O group activity monitor
¨Multiple external wake up events from DOZE and SLEEP states
¨External push button
¨RTC alarm
¨Two levels battery warning monitor
Port definitions for the M6377 Chip are provided in Table 4-5. 
						

							                                                                                                            Theory of Operation  4-23  
         Table 4-5  M6377 GPIO Port Definitions
ItemDescription
GPIO17
(W/R)1:  Connect serial BUS with charger ROM.
0:  Disconnect serial BUS with charger ROM.
GPIO20 is the CLK and GPIO21 is the DATA for the serial BUS.
GPIO16Reserved
GPIO15
(W/R)1:  CPU high temperature SMI is allowed.
0:  CPU low temperature SMI is allowed.
GPIO14
(W/R)1:  Connect the ZV BUS with PCMCIA card.
0:  Connect the ZV BUS with Feature board.
GPIO13
(W)1:  Force the system to enter 0V suspend or power down mode, and then could press power
     button to turn on system again.
0:  Normal
GPIO12
(W/R)1:  Force FAN on
0:  Normally
GPIO11
(W/R)1:  Enable+12V power foor FLASH ROM.
0:  Disable+12V power.
GPIO10
(W/R)1:  Disable FIR VCC.
0:  Enable FIR VCC.
GPIO27
(R)1:  CPU high temperature.
0:  CPU low temperature.
GPIO26
(W/R)1:  notebook’s SMBUS is accessible.
0:  MPB’s SMBUS is accessible.
GPIO25
(W/R)1:  Brightness level is fixed
0:  Brightness is trimable via  GPIO22 & GPIO20.
The current brightness level is stored when PIO25 low to high transations.
GPIO24
(W/R)For DSTN LCD only.
1:  Contrast level is fixed.
0:  Contrast is trimable via GPIO22 & GPIO20.
The current brightness level is stored when PIO25 low to high transations.
GPIO231:  Normally
0:  Ready to transations.
GPIO22
(W/R)The Brightness & Contrast for LCD system is devided into 32 scale by programing GPIO22 &
GPIO20.
1:  Brightness is incremented with GPIO23 “L” and GPIO20 high to low transations.
     Contrast is incremented with GPIO24 :L” and GPIO20 high to low transations.
0:  Brightness is decremented with GPIO24 “L” and GPIO20 high to low transations.
     Contrast is decremented with GPIO23 “L” and GPIO20 high to low transations.
GPIO21
(W/R)The system provide a serial BUS while wired to Inverter ROM, notebook’s Charger ROM, MPB’s
Charger ROM and Uma’s dock ROM.
GPIO21 is the serial DAT and GPIO20 is the serial CLK. 
						

							4-24   Theory of Operation
Table 4-5  M6377 GPIO Port Definitions (Continued)
ItemDescription
GPIO20
(W/R)GPIO20 is the common CLK for below serial BUS:
A.  For Charger ROM, Inverter ROM, MPB ROM serial BUS.
B.  For Brightness & Contrast control.
C.  For Feature board.
GPIO37
(W/R)GPIO37 is serial DATA for Feature board serial BUS, and GPIO20 is the serial CLK.
GPIO36
(W/R)1:  Normally
0:  Disable MPB power.
GPIO35
GPIO34
GPIO33
(W/R)The system use 3-wire BUS to communicate with thermal sensor (DS1620). These functions are
shown as below:
GPIO35     1:  Enable DS1620.
                  0:  Disable DS1620.
GPIO34 is CLK for 3-wire BUS .
GPIO33 is DATA, must be valid during the rising edge of CLK(GPIO34).
GPIO32
(W/R)1:  Normally
0:  System into STANDBY mode.
GPIO31
(W/R)1:  Enable 1394 power.
0:  Disable 1394 power.
GPIO30
(W/R)1:  Go to 5V suspend.
0:  Normally
SE12
(W)1:  Normally
0:  Disable notebook’s OP amplify.
SE11(W)
SE10(W)Reserved
GPIO7 1:  Media bay switch is unlocked.
0:  Media bay switch is locked.
GPIO6 1:  MPB is connected.
0:  MPB is disconnected.
GPIO5 received
GPIO2 1:  No FDD connected.
0:  FDD connected.
GPIO1 0:  No 2nd channel IDE device connected
1:  2nd channel IDE device connected.
GPI00 1:  Parallel port connected with FDD while the parallel port SMI occured.
0:  Parallel port connect with printer.