Acer Extensa 900 Maintenance Manual
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Theory of Operation 4-5
4.2.2 Memory Subsystem
The memory subsystem comprises the following components:
¨Main memory
¨L2 Secondary Memory (cache)
¨Flash ROM
The Extensa Series uses fast Extended Data Out (EDO) DRAM for main and video
memory and high-speed synchronous, pipelined burst SRAM for L2 cache memory.
Main BIOS and Video BIOS are stored in Flash ROM.
The Extensa 900 Series Memory Address Map is shown in Table 4-2.
Table 4-2 Memory Address Map
The DMA Channel Map is listed in Table 4-3.
Table 4-3 DMA Channel Map
4.2.2.1 Main Memory
The standard 900 Series notebook comes with 16 MB of Main memory installed on the
Main Board. Memory expansion accommodations are provided via a standard soDIMM
connector on the bottom of the Main Board Assembly. By installing a 64 MB soDIMM
module, the basic memory size can be expanded to a maximum of 80 MB.
Address RangeDefinitionFunction
000000 - 09FFFF640 KB memory Base memory
0A0000 - 0BFFFF128 KB video RAM Reserved for graphics display buffer
0C0000 - 0CBFFFVideo BIOS Video BIOS
0E0000 - 0EFFFF
0F0000 - 0FFFFF128 KB system BIOS System BIOS
System BIOS
100000 - FFFFFFExtended memory Onboard memory
FE0000 - FFFFFF256 KB system ROM Duplicate of code assignment at 0E0000-0FFFFF
ControllerChannelAddressFunction
1
1
1
1
2
2
2
2
0
1
2
3
4
5
6
7
0087
0083
0081
0082
Cascade
008B
0089
008A
Audio (option)
ECP/FIR/Audio
Diskette
ECP/FIR/Audio
Cascade
Spare
Spare
Spare
4-6 Theory of Operation 4.2.2.2 Flash ROM All versions of the Extensa notebook family use a Flash ROM that contains both the main system BIOS and the VGA BIOS. The Flash ROM contains Boot Block logic that allows downloading new versions of BIOS without destroying the Boot Load area. The Flash ROM execution is 8 bits wide. However, better performance can be attained by enabling the Shadow ROM in the CMOS setup routine or by selecting the Windows Control Panel Applet. When the Shadow ROM is enabled, BIOS is copied into a 32-bit, high-speed system. 4.2.3 System Controller Function The Extensa 900 Series notebook design uses two chips, the ALI M1521 (memory, Cache and DRAM Controller for the Pentium System and the M1523 (PCI to ISA Bridge chip) combine to provide the 586 system controller function for the new multimedia/ multithreading operating system, Windows 95. The notebook utilizes the BGA package to improve the AC characterization, resolves system bottleneck and make the system manufacturing easier. The system architecture includes the UMA, ECC, PBSRAM, SDRAM/BEDO, and multi-bus with highly efficient, deep FIFO between the buses, such as the HOST/PCI/ISA dedicated IDE bus. The I/O Address Map for the 900 Series Notebook is provided in Table 4-4.
Theory of Operation 4-7 Table 4-4 I/O Address Map Address RangeDevice 000 - 00F 020 - 021 022 - 023 040 - 043 048 - 04B 060 - 06E 070 - 071 080 - 08F 0A0 - 0A1 0C0 - 0DF 178 - 17A 1F0 - 1F7 170 - 177 3F6, 3F7 220 - 22F 240 - 24F 260 - 26F 280 - 28F 278 - 27F 2E8 - 2EF 2F8 - 2FF 378 - 37A 3B4, 3B5, 3BA 3C0 - 3C5 3C6 - 3C9 3C0 - 3CF 3D0 - 3DF 3E0 - 3E1 3E8 - 3EF 3F0 - 3F7 3F8 - 3FF CF8 - CFFDMA controller-1 Interrupt controller-1 M1523 registers Timer 1 Timer 2 Keyboard controller Real-time clock and NMI mask DMA page register Interrupt controller-2 DMA controller-2 6377 registers Hard disk select CD-ROM Audio (option) Audio (option) - default Audio (option) Audio (option) Parallel port 1 COM 4 COM 2 Parallel port 2 Video subsystem Video DAC Enhanced graphics display Color graphics adapter PCMCIA controller COM3 Floppy disk controller COM 1 PCI configuration register
4-8 Theory of Operation 4.2.3.1 ALI M1521 (Memory, Cache and DRAM Controller) The M1521 provides the system controller and data path components for the Extensa 900 Pentium-based system. It provides 64-bit CPU bus interface, 32-bit PCI bus interface, 64/72 DRAM data bus with ECC or parity, secondary cache interface including pipeline burst SRAM or asynchronous SRAM, PCI master to DRAM interface, four PCI master arbiters, and a UMA arbiter. The M1521 bus interfaces are designed to interface with 3V and 5V buses. It directly connects to 3V CPU bus, 3V or 5V tag, 3V or 5V DRAM bus, and 5V PCI bus. 4.2.3.1.1 Features of the ALI M1521 ¨Supports all Intel/Cyrix®/AMD 586-class processors (with host bus of 66 MHz, 60 MHz and 50 MHz at 3V) ¨Supports M1/K5/Dakota™ CPUs ¨Supports linear wrap mode for M1 ¨Supports asynchronous/pipeline-burst SRAM ¨Write-back/dynamic write-back cache policy ¨Built-in 8K* 2-bit SRAM for MESI protocol to cost and enhance performance ¨Cacheable memory up to 512 MB with 11-bit tag SRAM ¨Supports 3V/5V SRAMs for tag address ¨Supports FPM/EDO/BEDO/SDRAM DRAMs ¨RAS lines ¨64-bit data path to memory ¨Symmetrical/asymmetrical DRAMs ¨3V or 5V DRAMs ¨Duplicated MA[1:0] driving pins for burst access ¨No buffer needed for RASJ and CASJ and MA[1:0] ¨CBR and RAS-only refresh ¨Supports 64M-bit (16M* 4, 8M* 8, 4M*16) technology DRAMs ¨Supports programmable-strength MA buffer ¨Supports error checking and correction (ECC) and parity for DRAM
Theory of Operation 4-9 ¨Supports the most flexible six 32-bit populated banks of DRAM (to spare 12 MB for Windows 95) ¨Supports SIMM and DIMM ¨UMA (unified memory architecture) ¨Dedicated UMA arbiter pins ¨Supports several protocols from major graphics vendors ¨SFB size : 512 KB/1 MB/2 MB/3 MB/4 MB ¨CPU could access frame buffer memory through system memory controller ¨Alias address for frame buffer memory ¨Fully synchronous 25/30/33 MHz 5V PCI interface ¨PCI bus arbiter: five PCI masters and M1523 supported ¨DWORDs for CPU-to-PCI Memory write posted buffers ¨Convert back-to-back CPU to PCI memory write to PCI burst cycle ¨DWORDS for PCI-to-DRAM write-posted/Read-prefetching buffers ¨PCI-to-DRAM up to 133 MB/sec bandwidth (even when L1/L2 write-back) ¨L1/L2 pipelined snoop ahead for PCI-to-DRAM cycle ¨Supports PCI mechanism #1 only ¨PCI spec. 2.1 support (N(16/8)+8 rule, passive release, fair arbitration) ¨Enhanced performance for memory-read-line, memory-read-multiple, and memory-write-multiple ¨Invalidates PCI commands ¨DRAM refresh during 5V system suspend ¨I/O leakage stopper for power saving during system suspend 4.2.3.2 ALI M1523 (PCI-ISA Bridge) The M1523 provides a bridge between the PCI bus and the ISA bus and ensures full compatibility between the PCI and ISA functions. The M1523 has an Integrated System Peripherals (ISP) chip that provides advanced DMA controller features. This chip contains the keyboard controller, real time clock and IDE master controller. This chip also supports the Advanced Programmable Interrupt controller (APIC) interface.
4-10 Theory of Operation One eight-byte bidirectional line buffer is provided for ISA/DMA master memory read/ writes. One 32-bit wide posted-write buffer is provided for PCI memory write cycles to the ISA bus. It also supports a PCI to ISA IRQ routing table and level-to-edge trigger transfer. The chip has two extra IRQ lines and one programmable chip select for motherboard Plug-and-Play functions. The interrupt lines can be routed to any of the available ISA interrupts. The on-chip IDE controller supports two IDE connectors for up to four IDE devices providing an interface for IDE hard disks and CD-ROMs. The ATA bus pins are dedicated to improve the performance of IDE master. The M1523 supports the Super Green feature for Intel and Intel compatible CPUs. It implements programmable hardware events, software event and external switches (for suspend/turbo/ring-in). The M1523 provides CPU clock control (STPCLKJ). The STPCLKJ can be active (low) or inactive (high) in turn by throttling control. 4.2.3.2.1 M1523 Features Summary ¨Provides a bridge between the PCI bus and ISA bus ¨PCI interface ¨Supports PCI master and slave interface ¨Supports PCI master and slave initiated termination ¨PCI spec. 2.1 compliant (delay transaction support) ¨Buffers ¨8-byte bidirectional line buffers for DMA/ISA memory read/write cycles to PCI bus ¨32-bit posted-write buffer for PCI memory write and I/O data write (for sound card) to ISA bus ¨Provides steerable PCI interrupts for PnP PCI devices ¨Up to eight PCI interrupts routing ¨Level-to-edge trigger transfer ¨Enhanced DMA controller ¨Provides seven programmable channels (four for 8-bit data size, three for 16-bit data size) ¨32-bit addressability ¨Provides compatible DMA transfers
Theory of Operation 4-11 ¨Provides type F transfers ¨Interrupt controller ¨Provides 14 interrupt channels ¨Independently programmable level/edge triggered channels ¨Counter/Timers ¨Provides 8254 compatible timers for system timer, refresh request, speaker output use ¨Keyboard controller ¨Built-in PS2/AT keyboard controller ¨The specific I/O is used to save the external TTL buffer ¨Real time clock ¨Built-in real time clock ¨128-byte CMOS RAM with 2 ¨Plug-and-Play port support ¨Programmable chip select ¨Steerable interrupt request lines ¨PMU interface ¨Supports CPU SMM mode, SMI feature ¨Supports programmable stop clock throttle ¨Supports the APM control ¨Provides external suspend mode switch/turbo switch/ring-in switch ¨Provides four system states for power saving (on, doze, standby, suspend) ¨Provides three timers from 1 second to 300 minutes to individually monitor VGA, MODE, IN status ¨Supports RTC alarm wake up control ¨IDE interface ¨Built-in PCI IDE master controller
4-12 Theory of Operation ¨Supports PIO modes up to mode 5 timings, and multiword DMA mode 0, 1, 2 ¨8 x 32-bit pre-read and posted-write buffers ¨Dedicated pins for ATA interface ¨Supports up to 256 KB ROM size decode ¨Reserved USB interface ¨208-pin PQFP package 4.2.4 Video Subsystem The video subsystem is implemented on the VGA Video Board and on the Main Board Assemblies. The notebook contains a built-in LCD and features simultaneous LCD and external VGA display. The video subsystem includes a 1.5 MB DRAM memory, 32-bit DRAM bus, and separate display and memory clocks. An additional frame buffer/accelerator DRAM increases the available memory band width for CPU accesses. The video section also uses additional levels of write FIFOs, a read cache, page mode DRAM. Control of the video subsystem is provided by the C&T 65550 High Performance Flat Panel/CR T VGA Controller chip. The C&T65550 multimedia flat panel/CR T GUI accelerators provide 64-bit high performance and new hardware multimedia support features as described in the following paragraphs. 4.2.4.1 C&T 65550 Features The C&T65550 integrates a powerful 64-bit graphics accelerator engine for Bit Block Transfer (BitBLT), hardware cursor, and other functions intensively used in graphical User Interfaces (GUls) such as Microsoft Windows. Superior performance is also achieved through a direct 32-bit interface to the PCI Local Bus. 4.2.4.1.1 Hardware MultiMedia Support The C&T65550 implements independent multimedia capture (and display systems) on- chip. The capture system places data in display memory (usually off screen) and the display system places it in a window on the screen. The capture system can receive data from either the system bus or from the ZV enabled video port in either RGB or YUV format. The input data can also scaled down before storage in display memory (e.g., from any size larger than 320 x 240 down to 352 x 248). Capture of input data may also be double-buffered for smoothing and to prevent image tearing. The display system can independently place either RGB or YUV data from anywhere in display memory into an on-screen window which can be any size and located at any
Theory of Operation 4-13 pixel boundary (YUV data is converted to RGB on-the-fly on output). Non-rectangular windows are supported via color keying. The data can be functionally zoomed on output up to 8x to fit the onscreen window and can be horizontally and vertically interpolated to scale or zoom artifacts. Interlaced and non-interlaced data are supported in both capture and display systems. 4.2.4.2 Versatile Panel Support The C&T65550 supports a wide variety of monochrome and color Single-Panel, Single-Drive (SS) and Dual-Panel, Dual Drive (DD) standard and high-resolution passive STN and active matrix TFT/MIM LCD, and EL panels. For monochrome panels, up to 64 gray scales are supported. Up to 4096 different colors can be displayed on passive STN LCDs and up to 16M colors on 24-bit active matrix LCDs. The C&T65550 offers a variety of programmable features to optimize display quality. Vertical centering and stretching are provided for handling modes with less than 480 lines on 480-line panels. Horizontal and vertical stretching capabilities are also available for both text and graphics modes for optimal display of VGA text and graphics modes on 800 x 600 and 1024 x 768 panels. Three selectable color -to-gray scale reduction techniques and SMAR TMAP© are available for improving the ability to view color applications on monochrome panels. CHIPS ® polynomial FRC algorithm reduces panel flicker on a wider range of panel types with a single setting for a particular panel type. 4.2.4.3 Low Power Consumption The C&T65550 employs a variety of advanced power management features to reduce power consumption of the display sub-system and extend battery life. Although optimized for 3.3V operation, the C&T65550 controllers internal logic, memory interface, bus interface, and panel interfaces can he independently configured to operate at either 3.3V or 5V. 4.2.4.4 Software Compatibility/Flexibility The C&T65550 are fully compatible with VGA at the register and BIOS levels. CHIPS and third-party vendors supply fully VGA-compatible BIOS, end-user utilities and drivers for common application programs. 4.2.5 Sound Subsystem The Extensa Series Notebook is equipped with an ESS1878 sound chip that is Sound BlasterTM and Sound Blaster Pro compatible. Internal stereo speakers provide the Notebook with sound generation capabilities. A set of 3.5 mm connectors allow for external microphone and line inputs and headphone/speaker outputs. The sound subsystem also includes a variety of sound utilities that combine to provide additional multi-media functions. 4.2.5.1 ESS1878 Audio Controller with Interface to Expansion Audio Mixer The ES1878 is a member of the ESS family of audio controllers that includes the ES1868. It shares most of the features of the ES1868 and includes new features, such
4-14 Theory of Operation as support for the expansion audio mixer chip, the ES978, and a new IIS serial port and stereo D/A converter. A 4-wire expansion analog bus and 2-wire serial control bus connect the ES1878 and the ES978. 4.2.5.2 ES1878 Features ¨ Hot-dock interface to expansion audio mixer (ES978) ¨Plug-and-Play support using internal resource ROM ¨Monophonic full-duplex using two DMA channels ¨Self-timed joystick port (digital joystick) ¨Support for up to 7 general purpose outputs and 7 general purpose inputs that can be slaved with corresponding pins of ES978 in expansion unit ¨IIS interface to intemal stereo D/A for external ZV port or MPEG audio ¨Completely general interrupt mapping, including sharing all interrupts 4.2.6 Keyboard Subsystem The keyboard subsystem, implemented on the Keyboard Assembly and the Main Board Assemblies Board, consists of the following major sections: ¨Keyboard Assembly ¨Keyboard Scanner ¨Status LED Interface 4.2.7 I/O Subsystem The I/O subsystem is implemented with an NS87338VJG Super I/O Controller and the associated peripherals. 4.2.7.1 NS87338VJG Super I/O Controller The PC87338VJG is a single chip solution for most commonly used I/O peripherals in ISA, and EISA based computers. It incorporates a Floppy Disk Controller (FDC), two full featured UAR Ts, and an IEEE 1284-compatible parallel port Standard PC-AT address decoding for all the peripherals and a set of configuration registers are also implemented in this highly integrated member of the Super I/O family. Advanced power management features, mixed voltage operation and integrated Serial-lnfrared (both IrDA and Sharp) support makes the PC87338 an ideal choice for low-power and/or portable personal computer applications. The PC87338 FDC uses a high performance digital data separator eliminating the need for any external filter components. It is fully compatible with the PC8477 and incorporates a superset of DP8473, NEC PD765 and N82077 floppy disk controller