Acer Extensa 900 Maintenance Manual

                                                                                                            Theory of Operation  4-5  
4.2.2 Memory Subsystem
The memory subsystem comprises the following components:
¨Main memory
¨L2 Secondary Memory (cache)
¨Flash ROM
The Extensa Series uses fast Extended Data Out (EDO) DRAM for main and video 
memory and high-speed synchronous, pipelined burst SRAM  for L2 cache memory. 
Main BIOS and Video BIOS are stored in Flash ROM.
The Extensa 900 Series Memory...

4-6   Theory of Operation
4.2.2.2 Flash ROM
All versions of the Extensa notebook family use a Flash ROM that contains both the 
main system BIOS and the VGA BIOS.  The Flash ROM contains Boot Block logic that 
allows downloading new versions of BIOS without destroying the Boot Load area.
The Flash ROM execution is 8 bits wide. However, better performance can be attained 
by enabling the Shadow ROM in the CMOS setup routine or by selecting the Windows 
Control Panel Applet. When the Shadow ROM is enabled,...

                                                                                                            Theory of Operation  4-7  
Table 4-4  I/O Address Map
Address RangeDevice
000 - 00F
020 - 021
022 - 023
040 - 043
048 - 04B
060 - 06E
070 - 071
080 - 08F
0A0 - 0A1
0C0 - 0DF
178 - 17A
1F0 - 1F7
170 - 177
3F6, 3F7
220 - 22F
240 - 24F
260 - 26F
280 - 28F
278 - 27F
2E8 - 2EF
2F8 - 2FF
378 - 37A
3B4, 3B5, 3BA
3C0 - 3C5
3C6 - 3C9
3C0 - 3CF
3D0 - 3DF
3E0 - 3E1
3E8 - 3EF
3F0 - 3F7
3F8 - 3FF
CF8 - CFFDMA...

4-8   Theory of Operation
4.2.3.1 ALI M1521 (Memory, Cache and DRAM Controller)
The M1521 provides the system controller and data path components for the Extensa 
900  Pentium-based system. It provides 64-bit CPU bus interface, 32-bit PCI bus 
interface, 64/72 DRAM data bus with ECC or parity, secondary cache interface 
including pipeline burst SRAM or asynchronous SRAM, PCI master to DRAM interface, 
four PCI master arbiters, and a UMA arbiter. The M1521 bus interfaces are designed 
to interface with 3V...

                                                                                                            Theory of Operation  4-9  
¨Supports the most flexible six 32-bit populated banks of DRAM (to spare 
12 MB for Windows 95)
¨Supports SIMM and DIMM
¨UMA (unified memory architecture)
¨Dedicated UMA arbiter pins
¨Supports several protocols from major graphics vendors
¨SFB size : 512 KB/1 MB/2 MB/3 MB/4 MB
¨CPU could access frame buffer memory through system memory controller
¨Alias address for frame...

4-10   Theory of Operation
One eight-byte bidirectional line buffer is provided for ISA/DMA master memory read/
writes. One 32-bit wide posted-write buffer is provided for PCI memory write cycles to 
the ISA bus. It also supports a PCI to ISA IRQ routing table and level-to-edge trigger 
transfer.
The chip has two extra IRQ lines and one programmable chip select for motherboard 
Plug-and-Play functions. The interrupt lines can be routed to any of the available ISA 
interrupts.
The on-chip IDE controller...

                                                                                                            Theory of Operation  4-11  
¨Provides type F transfers
¨Interrupt controller
¨Provides 14 interrupt channels
¨Independently programmable level/edge triggered channels
¨Counter/Timers 
¨Provides 8254 compatible timers for system timer, refresh request, speaker 
output use
¨Keyboard controller
¨Built-in PS2/AT keyboard controller
¨The specific I/O is used to save the external TTL buffer
¨Real time...

4-12   Theory of Operation
¨Supports PIO modes up to mode 5 timings, and multiword DMA mode 0, 1, 2
¨8 x 32-bit pre-read and posted-write buffers
¨Dedicated pins for ATA interface
¨Supports up to 256 KB ROM size decode
¨Reserved USB interface
¨208-pin PQFP package
4.2.4 Video Subsystem
The video subsystem is implemented on the VGA Video Board and on the Main Board 
Assemblies.
The notebook contains a built-in LCD and features simultaneous LCD and external 
VGA display.
The video subsystem includes a 1.5...

                                                                                                            Theory of Operation  4-13  
pixel boundary (YUV data is converted to RGB on-the-fly on output). Non-rectangular 
windows are supported via color keying. The data can be functionally zoomed on output 
up to 8x to fit the onscreen window and can be horizontally and vertically interpolated 
to scale or zoom artifacts. Interlaced and non-interlaced data are supported in both 
capture and display...

4-14   Theory of Operation
as support for the expansion audio mixer chip, the ES978, and a new IIS serial port 
and stereo D/A converter. A 4-wire expansion analog bus and 2-wire serial control bus 
connect the ES1878 and the ES978.
4.2.5.2 ES1878 Features
¨
Hot-dock interface to expansion audio mixer (ES978)
¨Plug-and-Play support using internal resource ROM
¨Monophonic full-duplex using two DMA channels
¨Self-timed joystick port (digital joystick)
¨Support for up to 7 general purpose outputs and 7...