Acer Extensa 650 Maintenance Manual
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Theory of Operation 4-5 implement power savings features. From the CMOS setup routine, an automatic power down mode can be selected which enables the drive to turn off its motor after a specified period of inactivity. Additional Sleep modes can direct additional power savings during inactive periods by powering down the control circuitry. 4.2.7 Floppy Disk Drive Subsystem The Extensa 60x...
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4-6 Theory of Operation 4.3.1 Major Components Table 4-1 shows a listing the of the major components used in the Extensa Series Notebooks. 4.3.2 System Architecture Figure 4-2 shows the Extensa system architecture. The remainder of this section provides a detailed description of the major chips used in the Extensa Notebooks. Table 4-1 Major Chips List ComponentVendor Description M1521Acer System data buffer M1523Acer System controller chip M6377Acer Power management unit 65550C&T (Chips & Technology)...
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Theory of Operation 4-7 Figure 4-2 Extensa Series System Architecture Diagram M1521 M1523 SYSTEM ARCHITECTURE ta g 8/11-b it TT LSRAM 208-PQFP/RTC/KBC328-BGA 586 CPU addrdata PCI ISA DRAM MD GC MA CTLR IDE busHDD 128K/256K FlashXD - TTL USB conn
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4-8 Theory of Operation The signal descriptions for the M1521 are provided in Table 4-2. The chip pinouts are provided in Figure 4-3. ALI M1521 (PCI, Cache, and Memory Controller) The ALADDIN-III consists of two chips, ALI M1521 and M1523 to give a 586 class system the complete solution with the most up-to-date feature and architecture for the new multimedia/multithreading operating system. It utilizes the BGA package to improve the AC characterization, resolves system bottleneck and make the system...
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Theory of Operation 4-9 Figure 4-3 M1521 Pin Assignments
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4-10 Theory of Operation A simplified block diagram of the M1523 chip is shown in Figure 4-4 and the associated pinouts are provided in Figure 4-5. 4.3.2.1 ALI M1523 (PCI-ISA Bridge) The M1523 is a bridge between PCI and ISA bus, providing full PCI and ISA compatible functions. The M1523 has Integrated System Peripherals (ISP) on-chip and provides advanced features in the DMA controller. This chip contains the keyboard controller, real-time clock and IDE master controller. This chip also supports...
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Theory of Operation 4-11 Figure 4-4 M1523 Chip Simplified Block Diagram M 1523 Block Diagram DATA Buffer Control Address Buffer Decoder Clock & Reset PCI BUS Interface UNIT PCI Arbiter Interface ISA Interrupt UNIT PCI Interrupt UNIT CPU Interface USB Interface (reserved) PCI IDE Master Interface ISA BUS Interface UNIT DMA Refresh UNIT PMU or APIC Interface PS2/AT Keyboard Controller Timer...
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4-12 Theory of Operation
Figure 4-5 M1523 Pinouts
VDD
IRQ12
MSCLK
KBDATA
KBCLK/KBCSJ
KBINH/IRQ1
IDE SCS3J
IDE SCS1J
IDE PCS3J
IDE PCS1J
IDE _A0
IDE _A2
IDE _A1
IDA KJ 1
IDA KJ 0
IDE RDY
IDE IORJ
IDE IOW J
IDRQ1
IDRQ0
IDE_D0
IDE_D15
Vss
IDE_D1
IDE_D14
IDE_D2
IDE_D13
IDE_D3
IDE_D12
IDE_D4
IDE_D11
IDE_D5
IDE_D10
IDE_D6
IDE_D9
IDE_D7
VDD
IDE_D8
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
CBEJ0
AD8
AD9
AD10
AD11
VDD Vss
BALE
SA2
SA1
SA0
SBHEJ
M16J
LA23
IO16J...
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Theory of Operation 4-13 A simplified block diagram of the M6377 Power Management Unit is provided in Figure 4-6. The chip pinouts are provided in Figure 4-7. 4.3.2.2 ALI M6377 (Power Management Unit) · Three operation states · ON state · DOZE state · SLEEP state · Programmable DOZE and SLEEP timers · Programmable EL timer for backlight control · Three output pins depending on operation...
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4-14 Theory of Operation Figure 4-6 M6377 Simplified Block Diagram ACTIVITY MONITOR EL TIMER PROGRAMABLE APM TIMER x 2 BATTERY MONITOR GPIO SMI HANDLER STATE CONTROLLER WAKEUP EVENT HANDLER BUS INTERF ACE Timebase OTHER