Yamaha Cdx9 Service Manual

							CDX-497/CDX-397
11
CDX-497/CDX-397
Front Panel Assy
•Cable Connections
Mounting
Dismounting Top Cabinet [25]
→Remove 2 screws. [61] (2 on side)
→Remove 4 screws. [60]
(4 on rear side)
→Lift top cabinet from rear side to remove.
→Remove CN42, CN52 and CN71. →Unlock tray lid and close tray. →Open tray. (See 
HOW TO MANUALLY
EJECT THE TRAY)
→Remove 2 screws. [52]
(Front panel assy to side frame)
→Remove 4 screws. [51]
(Front panel assy to bottom frame)
→Remove front panel assy. →Unlock front panel assy from frame
by releasing successively 2 snaps.
(2 on the side)→Remove CN21-23, CN41
(MAIN (1) P.C.B.) and CN44.→Remove 2 screws. [56]
(P.C.B. to bottom frame)
→Remove 1 screw. [59]
(P.C.B. to rear panel)
→
Remove 3 screws (CDX-497),
2 screws (CDX-397). [58]
(P.C.B. to rear panel)
→Remove MAIN (1) P.C.B.. MAIN (1) P.C.B. [35 (1)] →Remove 1 screw. [59]
(P.C.B. to rear panel)
→Remove MAIN (2) P.C.B.
which is connected directly
to the lower P.C.B. with
connectors. MAIN (2) P.C.B. [35 (2)]
→Remove CN43.
→Remove 2 screws. [53]
(P.C.B. to rear panel)
→Remove FRONT (5) P.C.B.. FRONT (5) P.C.B. [31 (5)]
(R model)
→Remove CN41 (FRONT (2)
P.C.B.), CN41(MAIN P.C.B.)
and CN44.
→Remove CN43. (R model)
(P.C.B. to rear panel)
→Remove 1 screws. [56]
(P.C.B. to bottom frame)
→Remove 3 screws. [55]
(P.C.B. to bottom frame) FRONT (2) P.C.B. [31 (2)]
→Remove 2 screws. [53]
(P.C.B. to front panel assy)
→Remove FRONT (4) P.C.B.. FRONT (4) P.C.B. [31 (4)]
→Remove 1 screws. [53]
(P.C.B. to front panel assy)
→Remove FRONT (1) P.C.B.. FRONT (1) P.C.B. [31 (1)]→Remove 1 screws. [54]
(P.C.B. to front panel assy)
→Remove FRONT(3) P.C.B.. FRONT (3) P.C.B. [31 (3)]
(CDX-497 model)→Remove CN21-23.
→Remove 4 screws. [57]
(CD mechanism to bottom frame)
→
Remove CD mechanism.
CD Mechanism [38]
→Unlock tray lid and close tray. →Open tray. (See HOW TO MANUALLY
EJECT THE TRAY)
CD Mechanism
FRONT (4) P.C.B. FRONT (2) P.C.B.FRONT (2) P.C.B.CN71
CN22
CN52 CN23
CN21 CN41
(MAIN (1) P.C.B.) FRONT (5) P.C.B.
(R model)
CN41
(FRONT (2) P.C.B.)CN44
CN42
FRONT (1) P.C.B.
FRONT (3) P.C.B.
(CDX-497 model) CN43
(R model)
View A
A
Front Panel Assy

DISASSEMBLY PROCEDURES
See REPLACEMENT PARTS LIST for item numbers. 
						

							CDX-497/CDX-397
12
CDX-497/CDX-397
~

						

							CDX-497/CDX-397
13
CDX-497/CDX-397

TEST MODE
•Starting Test Mode
a. Connect the power cable to the AC power outlet.
b. Press the “POWER” key while simultaneously pressing “
W WW W
W / 
D DD D
D” (PLAY/PAUSE) and “
A AA A
A” (STOP) keys of the main
unit.
c. When in the TEST mode, the “TEST MODE” is displayed for 2 seconds.
2. Function list of remote control keys.
•Canceling Test Mode
Press the “POWER” key of the main unit. F FF F
F
 (OPEN/CLOSE)
W WW W
W / D DD D
D (PLAY/PAUSE)
A AA A
A (STOP)
T TT T
T / E EE E
E (SKIP-/SEARCH-)
R RR R
R / Y YY Y
Y (SKIP+/SEARCH+)Tray open/close.
Playback/Pause.
Stop.
Move traverse reverse.
Move traverse forward.
1. Function list of panel keys.
F FF F
F (OPEN/CLOSE)
W WW W
W (PLAY)
D DD D
D (PAUSE)
A AA A
A (STOP)
T TT T
T (SKIP-)
Y YY Y
Y (SKIP+)
TIME/INFO
SPACE
RANDOM
OUTPUT LEVEL +
OUTPUT LEVEL -Tray open/close.
Playback.
Pause.
Stop.
Move traverse reverse.
Move traverse forward.
Check FL display. (*1)
EEPROM write/read test.
Spindle servo on/off.
Output level up.
(CDX-497 model)
Output level down.
(CDX-497 model)
Starting TEST mode
This part is always displayed when in the TEST mode.2 seconds
*1 Check FL display
The display condition varies as shown below accord-
ing to the “TIME/INFO” key of the remote control.
Initial display
Icon (left)
Icon (right)
Pattern 1
Pattern 2
Pattern 3
Pattern 4
Pattern 5
Pattern 6
Pattern 7
Icon (left)
Panel key Function
Panel key Function 
						

							CDX-497/CDX-397
14
CDX-497/CDX-397
~ 
						

							CDX-497/CDX-397
15

IC DATAIC21: TC94A54 (MAIN P.C.B)
DSP
* No replacement part available.
I
3AI/F
–
O
3AI/F
O
3AI/F
O
3AI/F
O
3AI/F
I
3AI/F
–
O
3AI/F
O
3AI/F
O
3AI/F
O
3AI/F
O
3AI/F
O
3I/F
O
3I/F
O
3I/F
O
3I/F
O
3I/F
I/O
3I/F
–
–
–
I
3AI/F
O
3AI/F
–
–
O
3AI/F
–
O
O
3AI/F
–
–
– I/O
To be connected to the RFRP via
0.033 uF.
–
–
Monitor pin for various signals.
To be connected to the TEI via
0.033 uF.
–
–
–
Connected to the VRO and
PVREF within the IC.
To be connected 0.1 uF.
PWM ternary output (AVDD3,
GND, and VREF).
“H” at S1 when Subcode Sync is
detected.
–
–
7.35kHz (At this pin, flags in the
DSP and PLL-circuit clock can be
monitored, using microcontroller
commands. The pin also outputs
text data serially.)
Valid also for 1-bit DAC external
inputs.
General-purpose I/O (input after a
reset).
–
–
–
–
Input to the internal MCK.
–
–
No capacitor is required at the
DVR pin unless the built-in 1-bit
DAC is used.
3.3V must be applied across the
DVDD3 and DVSS3 pins, how-
ever.
–
–
–
IC21: TC94A54 (MAIN P.C.B)
DSP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33RFZI
AVSS3
RFRP
FEI
SBAD/RFDC
TEI
TEZI
AVDD3
FOO
TRO
VREF
FMO
DMO
SBSY
(SPCK)
SBOK
(FOK)
(CLCK)
(MBOV)
IPF
(SPDA)
SFSY
(EMPH)
(LOCK)
(MONIT)
ZDET
(DATA)
(COFS)
GPIN
VSS1
VDD1
XVSS3
XI
XO
XVDD3
DVSS3
RO
DVDD3
DVR
LO
DVSS3
VSS3
VDD3Input pin for the RF ripple zero-cross signal.
Grounding pin for 3.3V analog circuits.
RF ripple signal output pin.
Focus error signal input pin.
Subbeam addition signal input pin.
Tracking error signal input pin.
Input pin for tracking error signal zero-cross.
Supply voltage pin for 3.3V analog circuit.
Forcus equalizer output pin.
Tracking equalizer output pin.
Analog reference supply voltage pin.
Speed error/feed equalizer output pin.
Disc equalizer output pin.
Pin for outputting the subcode block sync signal. It is “H” at
position S1 when the subcode sync signal is detected.
(CD Processor Status Read Clock (176.4 kHz) output)
Pin for outputting the CRCC check result of a subcode Q data
check. It is “H” when the check result is OK.
(Focus OK signal)
(Input/output pin for the clock used in reading the subcode P
to W data.)
(CD Buffer memory overflow output)
Correction flag output pin.
“H” if the AOUT pin outputs an uncorrectable symbol in C2
correction.
(CD Processor Status signal output)
Pin for outputting the playback frame sync signal.
(Emphasis fiag output pin. ENPH on: “H”. EMPH off: “L”. The
output polarity can be switched, using a command.)
(LOCk signal)
(Pin for monitoring signals in the DSP.)
Output pin for zero detection flag for the 1-bit DAC.
(Pin for outputting subcode P to W data)
(Error Correstion Frame Clock 7.35 kHz output)
General-purpose I/O (DSP)
1.5V grounding pin dedicated to the Digital circuit.
1.5V supply voltage pin dedicated to the Digital circuit.
Grounding pin for the system clock oscillation circuit.
Input pin for the system clock oscillation circuit.
Output pin for the system clock oscillation circuit.
3.3V supply voltage pin for the system clock oscillation circuit.
Grounding pin for the 1-bit DAC.
Output pin for normal R-channel data for the 1-bit DAC.
3.3V supply voltage pin for the 1-bit DAC.
Reference voltage pin for the 1-bit DAC.
Output pin for normal L-channel data for the 1-bit DAC.
Grounding pin for the 1-bit DAC.
3.3V grounding pin dedicated to the I/F circuit
3.3V supply voltage pin dedicated to the I/F circuit.
Pin No. Pin name Description
Remark
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2575 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
26272829303132333435363738394041424344454647484950
100FTE
TNI
TPI
FPI1
FPI2
PNI1
PNI2
RVSS3
MDI
LDO
RVDD3
PNSEL
RFO999897969594939291908988
DVSS3
ROCLOCK
GEN
PWM
ADRRESS CIRCUIT
CORRECTION
CIRCUIT
1-bit
DACSUBCODE
DEMOCULA
TION
CDRCUIT ANA
LPF
CPU
I/F
PULL-UP16k
RAM
DIGITAL
OUTAUDIO
OUTPLL
TMAX AWRC
VCORFRP RFEQVROAGC RFDCRFFE TE 10-bit
SAR ADC 5-bit
R-2R DAC
SERVO
CONTROL
DIGITAL EQ
AUTO ADJ ROM
CAV SERVO
SYNC SIGNAL PROTECTION
EFM DEMODULATIONCLV SERVO RANAPC
RF
BLOCK
EFM SLICE DVDD3
DV R
LO
DVSS3
VSS3
VDD3
VDDM
VSS1S
BUS0
BUS2
BUS3 BUS1
BUCK
/CCE
/RST
STBY
VDDT
FGIN
IO0
IO1
TESTD
VSSP
VCOI
VDDP
TESTC
PIO0
PIO1
PIO2
PIO3
DOUT
AOUT
BCKO
LRCKO
AIN
BCKI
LRCKI
VDD1S
VSS1S
AWRC
PVDD3
PDO
TMAX
LPPN
LPFO
PVREF
VCOF
VCOREF
PVSS3XVDD3
XO
XI
XVSS3
VDD1
VSS1S
GPIN
ZDET
SFSY
IPF
SBSY SBOK
DMO
PMO
VREF
TRO
FOO
AVDD3
TEZI
TEI
SBAD/RFDC
FEI
RFRP
AVSS3
RFZI
878685848382818079787776 
						

							CDX-497/CDX-397
16
–
–
To be fixed at “H” or “L” when com-
munication is not in progress, so
that the pin will not become HiZ.
To be fixed at “H” when communi-
cation is not in progress, so that
the pin will not become HiZ.
To be connected to 0.1 uF.
–
–
–
Genelal-purpose I/O (input after a
reset).
The playback speed mode flag
output can be switched, using
command bits.
–
–
–
–
–
General-purpose I/O (input after a
reset).
As per CP-1201
–
Normal speed: 32fs = 1.4112 MHz
Normal speed: 44.1kHz
1-bit DAC external input
Controllable in CLV/CAV.
–
Quaternary output (PVDD3, HiZ,
VSS, and PVREF).
Ternary output (PVDD3, VSS, and
Hiz). 34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69VDDM
VSS1
BUS0
BUS1
BUS2
BUS3
BUCK
/CCE
/RST
STBY
VDDT
FGIN
IO0A
(/HSO)
IO1A
(/UHSO)
TESTD
VSSP
VCOI
VDDP
TESTC
PIO0
PIO1
PIO2
PIO3
DOUT
AOUT
BCK
LRCK
AIN
BCKI
LRCKI
VDD1
VSS1
AWRC
PVDD3
PDO
TMAX1.5V supply voltage pin dedicated to the DSP/1Mbit SRAM
circuit.
1.5V groundind pin dedicated to the DSP/1Mbit SRAM circuit.
Data input/output pin for the microcontroller interface.
Clock input pin for the microcontroller interface.
Chip enable signal input pin for the microcontroller interface.
BUS3 to BUS0 are active if this pin is “L”.
Reset signal input pin. The internal registers and servo section
registers are reset, respectively, when the reset signal is “L”
and on the positive-going edge of the reset signal.
STANDBY control pin dedicated to the DSP/1Mbit SRAM
circuit.
3.3V supply voltage pin dedicated to the Digital I/O circuit.
FG signal input pin for CAV.
CLV: “L”. CAV: FG input.
Genelal-purpose input/output pins.
(Pin for outputting the playback speed mode flag.)
DSP/Test input pin. Usually fixed at “L”.
1.5V grounding pin dedicated to the DSP/VCO circuit.
PD output pin dedicated to the DSP/VCO circuit.
1.5V supply voltage pin dedicated to the DSP/VCO circuit.
CD/Test input pin. Usually fixed at “L”.
General-purpose I/O (CD/DSP)
General-purpose I/O (CD/DSP)
General-purpose I/O (DSP)
General-purpose I/O (DSP)
Digital-out output pin. Digital data for up to double speed can
be output when a frequency of 16.9344 MHz is used.
Audio data output pin. Which bit is first (MSB first or LSB first)
can be selected, using a command.
Bit clock output pin. 32fs, 48fs, and 64fs can be selected,
using a command.
LR channel clock output pin. L for the L-channel and “H” for
the R-channel. The output polarity can be inverted, using a
command.
1-bit DAC external input: AIN
1-bit DAC external input: BCKI
1-bit DAC external input: LRCKI
1.5V supply voltage pin dedicated to the DSP circuit.
1.5V grounding pin dedicated to the DSP circuit.
VCO control pin for active wide range.
3.3V supply voltage pin dedicated to the PLL circuit.
Pin for outputting a phase difference signal between the EFM
signal and PLCK signal.
Pin for outputting the result of TMAX detection.
The TMAX pin output the same signal. –
–
I/O
3I/F
I/O
3I/F
I/O
3I/F
I/O
3I/F
I
3I/F
I
3I/F
I
3I/F
I
3I/F
–
I
3AI/F
I/O
3I/F
I/O
3I/F
I
3I/F
–
O
1.5AI/F
–
I
3I/F
I/O
3I/F
I/O
3I/F
I/O
3I/F
I/O
3I/F
O
3I/F
O
3I/F
O
3I/F
O
3I/F
I
3I/F
I
3I/F
I
3I/F
–
–
O
3AI/F
–
O
3AI/F
O
3AI/FRemark
IC21: TC94A54 (MAIN P.C.B)
DSPPin No. Pin name Function
Pin name
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100LPFN
LPFO
PVREF
VCOF
VCOREF
PVSS3
SLCO
RFI
RFRPI
RFEQO
RESIN
VRO
VMDIR
TESTR
INVSEL
AGCI
AGCI
RFO
PNSEL
EQSET
RVDD3
LDO
MDI
RVSS3
FNI2
FNI1
FPI2
FPI1
TPI
TNI
FTEI
3AI/F
O
3AI/F
–
O
3AI/F
I
3AI/F
–
O
3AI/F
I
3AI/F
I
3AI/F
O
3AI/F
I
3AI/F
O
3AI/F
–
O
3AI/F
I
3AI/F
I
3AI/F
I
3AI/F
O
3AI/F
I
3AI/F
O
3AI/F
–
O
3AI/F
I
3AI/F
–
I
3AI/F
I
3AI/F
I
3AI/F
I
3AI/F
I
3AI/F
I
3AI/F
O
3AI/FPin for receiving an inverted output of the PLL-circuit low-pass
filter amp.
Pin for the PLL-circuit low-pass filter amp output.
1.65V reference supply voltage pin dedicated to the PLL
circuit.
VCO filter pin.
Input pin for the VCO center frequency reference level.
3.3V grounding pin dedicated to the PLL circit.
EFM slice level output pin.
For both analog and digital slice modes, the output impedance
= 2.5 k-ohms.
RF signal input pin.
The input resistance can be selected, using a command.
RF ripple signal input pin.
RF equalizer circuit output pin.
Pin for connecting a reference current generating resistance.
1.65V reference voltage output pin.
Reference voltage poutput pin for the APC circuit.
LPF pin for RFEQO offset correction.
Test pin, usually fixed at “L”.
Pin for RF signal amplitude adjustment amp input.
RF signal peak detsction input pin.
RF signal generation amp output pin.
Test pin, usually fixed at “H”.
External connection pin for the RF signal equalizer.
3.3V supply voltage pin for the Rfamp core section.
Laser diode amp output pin.
Monitor photodiode amp input pin.
3.3V grounding pin for the RF amp core section.
Main beam input pin.
Connected to PIN diode C.
Main beam input pin.
Connected to PIN diode A.
Main beam input pin.
Connected to PIN diode D.
Main beam input pin.
Connected to PIN diode B.
Subbeam input pin.
Connected to PIN diode F.
Subbeam input pin.
Connected to PIN diode E.
Focus /tracking signal output.
(Test pin for servo characteristic measurement.)The resistance side is connected.
See an applicable circuit diagram.
The capacitor side is connected.
See an spplicable circuit diagram.
Connected to the VREF and PVREF
within the IC.
A 0.1 uF capacitor is connected.
–
To be connected to the PVREF if
the AWRC is not used.
–
A capacitor to be connected is se-
lected according to the servo op-
eration band.
Zin: 20 k-ohms, 10 k-ohms, 5 k-
ohms
–
To be connected to the RFRPI via
0.1 uF and to the RFI via 4700 pF
or higher.
To be connected to 22 k-ohms
and 680 pF in parallel.
Connected to the VREF and
PVREF within the IC
To be connected to 0.1uF anf 100
uF.
To be connected to 0.1uF.
To be connected to 0.015 uF or
higher.
–
–
–
To be connected directly to the
RFDCI.
To ne connected to the AGCI via
0.1 uF.
To be kept open when the RFEQ
is used.
–
Reference to 178 mV (typ.)
–
–
–
–
–
–
–
Switchable using a command. I/OPin No. Pin name Description
Remark
Note:“3AI/F : 3V circuit analog input/output pin.”
“3I/F : 3V circuit digital input/output pin.”
“1.5AI/F : 1.5V circuit analog input/output pin.” IC21: TC94A54 (MAIN P.C.B)
DSP 
						

							CDX-497/CDX-397
17
CDX-497/CDX-397
IC22: TA2125 (MAIN P.C.B)
Motor driver
* No replacement part available.
36 35 34 33 32 31 30 29 28 FINRL4 RL3
RL2 RL5RL1 27 26 25 24 23 22 21 20 19
123456789 FINTSD lref STBY STBY
10 11 12 13 14 15 16 17 18 V
RRIN FIN IN3 IN4REG
STB 4ch
Driver
STB
N.C. N.C. N.C.N.C. REG OUT V
CC
IN2 GND
IN1 VCIN+
++
N.C.x 3 x 3 x 3 x 3 x 3 x 3 x 3 x 3
Control
Logic
No. Symbol Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36OUT5A
VM
OUT5B
VCIN
IN1
N.C.
N.C.
N.C.
N.C.
N.C.
IN2
N.C.
N.C.
VCC1
OUT2M
OUT2P
OUT1M
OUT1P
OUT3P
OUT3M
OUT4P
OUT4M
VCC2
N.C.
REG OUT
REG OUT
N.C.
N.C.
N.C.
REG STBY
IN4
IN3
STBY
FIN
RIN
VROutput terminal
Supply voltage terminal for Logic
Output terminal
Input reference voltage
Input for ch1
Open
Open
8, 9, 10, 27, 28, 29 are connected to PW GND (FIN)
8, 9, 10, 27, 28, 29 are connected to PW GND (FIN)
8, 9, 10, 27, 28, 29 are connected to PW GND (FIN)
Input for ch2
Open
Open
Supply voltage terminal for ch 1/ch2
Inverted output for ch2
Non-inverted output for ch2
Inverted output for ch1
Non-inverted output for ch1
Non-inverted output for ch3
Inverted output for ch3
Non-inverted output for ch4
Inverted output for ch4
Supply voltage terminal for ch3/ch4
Open
Connection with BASE of PNP Tr
Output for regulator (5V)
8, 9, 10, 27, 28, 29 are connected to PW GND (FIN)
8, 9, 10, 27, 28, 29 are connected to PW GND (FIN)
8, 9, 10, 27, 28, 29 are connected to PW GND (FIN)
Standby control for regulator
Input for ch4
Input for ch3
Standby control for 4ch BTL
Logic control input
Logic control input
Supply voltage terminal for motor driverH-bridge
H-bridge
H-bridge
4ch BTL
4ch BTL
–
–
–
–
–
4ch BTL
–
–
4ch BTL
4ch BTL
4ch BTL
4ch BTL
4ch BTL
4ch BTL
4ch BTL
4ch BTL
4ch BTL
4ch BTL
–
Regulator
Regulator
–
–
–
Regulator
4ch BTL
4ch BTL
4ch BTL
H-bridge
H-bridge
H-bridge 
						

							CDX-497/CDX-397
18
CDX-497/CDX-397
IC71: CS4392 (MAIN P.C.B)
DAC
* No replacement part available.
1 20 AMUTECMCLK MODE SELECT
(CONTROL PORT)EXTERNAL
MUTE CONTROLREFERENCE
SERIAL
PORT
VOLUME
CONTROLVOLUME
CONTROL
INTERPOLATION
FILTER
INTERPOLATION
FILTER∆∑
DAC
∆∑
DACANALOG
FILTER
ANALOG
FILTER MIXERFILT+
AOUTA+
AOUTA-
AOUTB-
AOUTB- LRCKSCLK
S D ATACMOUT BMUTEC AMUTEC M3 M1
(SDA/CDIN)M2
(CL/CCLK)M0
(AD0/CS)
RST RST
AOUTA- VL
AOUTA+ S D ATA
VA SCLK
AGND LRCK
AOUTB+ MCLK
AOUTB- M3
BMUTEC (SCL/CCLK) M2
CMOUT (SDA/CDIN) M1
FILT+ (AD0/CS) M0219
318
417
516
615
714
813
912
10 11 
						

							CDX-497/CDX-397
19
1
2
3
4
5
6
11
12
20
13
14
15
18
19
16
17RST
VL
SDATA
SCLK
LRCK
MCLK
FILT+
CMOUT
AMUTEC
BMUTEC
AOUTB-
AOUTB+
AOUTA+
AOUTA
AGND
VA
IC71: CS4392 (MAIN P.C.B)
DACNo. Symbol Function
Reset (Input) - Powers down device and resets all intemal registers to their default settings.
Logic Power (Input) - Positive power for the digital input/output.
Serial Audio Data (Input) - Input for two’s complement serical audio data.
Serial Clock (input/output) - Serial clock for the serial audio interface.
Left Right Clock (Input/output) - Determines which channel, Left or Right, is currently active on the serial audio
data line.
Master Clock (Input) -Clock source for the delta-sigma moudukafor and digital filters.
Positive Voltage Reference (Output) - Positive reference voltage for the intemal sampling circuits.
Common Mode Voltage (Output) - Filter connection for internal quiescent voltage.
Mute Control (output) - The Mute Confrol pin goes high during power-up initialization, reset, muting, power-down
or if the master clock to left/right clock frequency ratio is incorrect.
Differential Analog Output (Outputs) - The full scale differential analog output level is specified in the Analog
Characteristics specification table.
Ground (Input)
Analog Power (Input) - Positive power for the analog section.7
8
9
10M3
SCL/CCLK
SDA/CDIN
AD0/CSNo. Symbol Function
Mode Selection (Input) -This pins should be tied to GND level during control port mode.
Serial Control Port Clock (input) - Serial clock for the serial control port.
Serial Control Data (input/output) - SDA is a data l/O line in  l
2C mode.CDIN is the input data line for the control
port interface in SPI mode.
Address Bit 0 (I
2C) / Control Port Chip Select (SPI) (Input/Output) - AD0 is a chip address pin in I
2C mode, 
CS is
the chip select signal for SPI format.
Control Port mode Definitions
7
8
9
10M3
M2
M1
M0No. Symbol Function
Mode Selection (Input) - Determines the operational mode of the device.Stand-Alone Mode Definitions 
						

							2
ABCDE FGH I J
1
3
4
5
7CDX-497/CDX-397
6
20

BLOCK DIAGRAM
 POWER
ON/OFF AC IN
CDX-497 model
CD Mechanism
MAIN•See page 25 → 
SCHEMATIC DIAGRAM
FRONT
•See page 26 → 
SCHEMATIC DIAGRAM
DIGITAL OUT
COAXIAL
OPTICAL
JK75
JK52 IC75
IC73
IC74
IC72 IC71
JK73
LINE OUT
L
R
IC22
IC21X201 IC51X501
RS51
SW41Q401 IC45 IC43 IC44 IC42IC41
D401, 403
D402, 404
D405, 406 T401FL51