ViewSonic Va703m4 Service Manual

							
ViewSonic Corporation 18  Confidential - Do Not Copy   VA703b-4_VA703m-4 
4. Circuit Description 
A. AC-DC CONVERTER 
The power supply with a high-integ rated green-mode PWM controller provides several features to 
enhance the performance of  power flyback converters. 
U801 is a PWM controller and provides many protection functions. 
U802 is a photo couple to transfer the feedback signa l from the second side which U803 detected both of 
the output DC voltage on 5V and 24V. 
Z802 detected the working voltage on U801 and Q 802 would pull down the voltage on U801 pin5 to 
shut down U801 if feedback loop was failed. 
R828 would be a dynamic load which was active wh ile backlight was turned off and system still 
working on, this kept 24V output voltage under 32V to  protect the panel.        After system went to 
power saving mode, the R828 would no loaded. This  was detected by Z803 active the R828 to load or 
not. 
B ， Scaling Controller 
Overview 
Realtek RTD2523B series products are all-in-one LCD monitor controllers support up to 
SXGA/XGA(optional), and integrate Realtek high performance ADC, TMDS Rx(optional), scaling engine, 
OSD engine, LVDS TX, RSDS TX and so on. Moreover, all products are pin compatible in low pin count 
package to save cost and make the design easier 
General 
z   Embedded dual DDC support DDC1, DDC2B, DDC/CI 
z   Zoom scaling up and down 
z   Embedded Pattern Generator 
z   No external memory required.  
z   Require only one crystal to generate all timing   
z   Embedded reset control output 
z   Embedded crystal output to MICROP 
z   3 channels 8 bits PWM output, and selectable PWM clock frequency. 
     Pin Description 
(I/O Legend:    A = Analog, I = Input, O = Output, P = Power, G = Ground)    
						

							
ViewSonic Corporation 19  Confidential - Do Not Copy   VA703b-4_VA703m-4 
„  ADC: 15 pins 
    Name 
I/O Pin No  Description  Note 
ADC_GND AG 27 ADC ground   
ADC_REFIO  AP  28  ADC band-gap voltage de-coupling  1.20V 
ADC_VDD AP 29 Analog power  (3.3V) 
BLUE+  AI  30  Analog input from BLUE channel   
BLUE-  AI  31  Analog input ground from BLUE channel  
ADC_GND AG 32 ADC ground   
SOG/ADC_TEST  AIO 33  SOG in/ADC test pin   
GREEN+  AI  34  Analog input from GREEN channel   
GREEN-  AI  35  Analog input ground from GREEN 
channel  
ADCB_VDD AP 36 Analog power  (3.3V) 
RED+  AI  37  Analog input from RED channel   
RED-  AI  38  Analog input ground from RED channel   
ADC_GND AG 39 Analog ground   
ADC_GND AG 40 Analog ground   
ADC_VDD AP 41 Analog power  (3.3V) 
AHS  AI  42  Analog HS input 
(10), (4), (5) 
AVS  AI  43  Analog VS input    (2), (4), (5) 
 
 
„  
PLL: 8 pins 
    Name  I/O Pin No  Description  Note 
XO AI 1 Reference clock output 
 
XI  AO  2  Reference clock input  
DPLL_GND  AG  3  Ground for digital PLL     
DPLL_VDD  AP  4  Power for digital PLL  (3.3V) 
APLL_VDD  AP  5  Power for multi-phase PLL    (3.3V) 
PLL_TEST1  AIO 6  Test Pin 1 / IRQ# 
 
PLL_TEST2  AIO 7  Test Pin 2/Power-on-latch for crystal out 
Frequency   
APLL_GND  AG  8  Ground for multi-phase PLL   
 
 
„   Control Interface: 7 pins 
    Name  I/O  Pin No  Description  Note 
SDIO [0]  IO  54  Serial control I/F data in / Parallel port 
data [0] (2), (3), / 2mA 
SDIO [1] / TCON [4] / 
BBLU [0] IO  53  Parallel port data [1] / TCON [4] / TTL 
BBLU [0]  (1), (2), (3), / 2mA 
SDIO [2] / TCON [3] / 
BBLU [1] IO  52  Parallel port data [2] / TCON [3] / TTL 
BBLU [1]  (1), (2), (3), / 2mA 
SDIO [3] / PWM2 / 
TCON [2] IO  51  Parallel port data [1] / TCON [4] / PWM2 (1), (2), (3), / 2mA 
SCLK    I  50  Serial control I/F clock    (2), (3), (5) 
SCSB    I  111  Serial control I/
F chip select  (2), (3), (5) 
RESET    O  56  RESET output for Micron  (2), (5), (6) / 2mA 
  
						

							
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„ Display & TCON/VIDEO-8 Port: 54 pins 
■:LVDS+RSDS+TTLO  ■:RSDS+TTLO  ■:RSDS+TTLIO ■:TTLO  ■:TTLIO  
Pin 
NO.  6-bits 
Dual RSDS  6 bits   
Single RSDS  8/6 bits 
Dual/Single  LV D S   8 bits 
Dual/Single  TTL  6 bits 
Dual/Single  TTL  Note 
51 S[3] / 
TCON[2] / 
PWM2 
S[3] / 
TCON[2] / 
PWM2 
S[3] / 
TCON[2] / 
PWM2 
S[3] / 
TCON[2] / 
PWM2 
S[3] / 
TCON[2] / 
PWM2 
(1), (2), (3)/ 
2mA 
52 S[2] / 
TCON[3] 
S[2] / 
TCON[3] 
S[2] / 
TCON[3] 
 S[2] 
/BBLU[1] / 
TCON[3] 
S[2] / 
TCON[3] 
(1), (2), (3)/ 
2mA 
53 S[1] / 
TCON[4] 
S[1] / 
TCON[4] 
S[1] / 
TCON[4] 
S[1]/ BBLU[0] 
/ TCON[4] 
S[1] / 
TCON[4] 
(1), (2), (3)/ 
2mA 
55 PWM2 / 
COUT / 
TCON[13]  
PWM2 / 
COUT / 
TCON[13]  
PWM2 / 
COUT / 
TCON[13]  
PWM2 / 
COUT / 
TCON[13]  
PWM2 / 
COUT / 
TCON[13]  
(1), (2), (3)/ 
2mA 
59 BB3P  BB3P NC BBLU [7] BBLU [7]  
60 BB3N BB3N NC BBLU [6] BBLU [6]  
61 BB2P BB2P NC BBLU [5] BBLU [5]  
62 BB2N BB2N NC BBLU [4] BBLU [4]  
63 BB1P BB1P NC BBLU [3]/T0 BBLU [3]  
64 BB1N BB1N NC BBLU [2]/T1 BBLU [2]  
65 BCLKP BCLKP NC BGRN [1]/T2 TCON [6]  
66 BCLKN BCLKN NC BGRN [0]/T3 TCON [5]  
67 BG3P BG3P NC BGRN [7] BGRN [7]  
68 BG3N BG3N NC BGRN [6] BGRN [6]  
73 BG2P BG2P TODP BGRN [5]/T4 BGRN [5]  
74 BG2N BG2N TODN BGRN [4]/T5 BGRN [4]  
75 BG1P BG1P TOCLKP BGRN [3]/T6 BGRN [3]  
76 BG1N BG1N TOCLKN BGRN [2]/T7 BGRN [2]  
77 BR3P BR3P TOCP BRED [7]/T8 BRED [7]  
78 BR3N BR3N TOCN BRED [6]/T9 BRED [6]  
79 BR2P BR2P TOBP BRED [5]/T10BRED [5]  
80 BR2N BR2N TOBP BRED [4]/T11BRED [4]  
81 BR1P BR1P TOAP BRED [3]/T12BRED [3]  
82 BR1N BR1N TOAP BRED [2]/T13BRED [2]  
85 AB3P NC TEDP ABLU [7]/T14ABLU [7]  
86 AB3N NC TEDN ABLU [6]/T15ABLU [6]  
87 AB2P NC TECLKP ABLU [5]/T16ABLU [5]  
88 AB2N NC TECLKN ABLU [4]/T17ABLU [4]   
						

							
ViewSonic Corporation 21  Confidential - Do Not Copy   VA703b-4_VA703m-4 
89 AB1P NC TECP ABLU [3]/T18ABLU [3]  
90 AB1N NC TECN ABLU [2]/T19ABLU [2]  
91 ACLKP NC TEBP ABLU [1]/T20TCON [1]  
92 ACLKN NC TEBN ABLU [0]/T21TCON [0]  
93 AG3P NC TEAP AGRN [7]/T22AGRN [7]  
94 AG3N NC TEAN AGRN [6]/T23AGRN [6]  
99 AG2P TCON [11] NC AGRN [5]/T24AGRN [5]  
100 AG2N TCON [10] NC AGRN [4]/T25AGRN [4]  
101 AG1P TCON [9] NC AGRN [3]/T26AGRN [3]  
102 AG1N TCON [8] NC  AGRN [2]/T27AGRN [2]  
103 AR3P TCON [7] NC ARED [7]/T28ARED [7]  
104 AR3N TCON [6] NC ARED [6]/T29ARED [6]  
105 AR2P TCON [5] NC ARED [5]/TH ARED [5]  
106 AR2N TCON [1] NC ARED [4]/TV ARED [4]  
107 AR1P TCON [0] NC ARED [3]/TE ARED [3]  
108 AR1N NC NC ARED [2]/TK ARED [2]  
113 PWM2 / 
COUT / 
TCON[12]  
PWM2 / 
COUT / 
TCON[12]  
PWM2 / 
COUT / 
TCON[12]  
ARED [1] PWM2 / 
COUT / 
TCON[12]  
(9) 
114 TCON [11] 
/V[0]  
V [0] V [0] ARED [0] TCON [11] (1), (7), (8) 
115 TCON [10] 
/V[1]  
V [1] V [1] BRED [1] TCON [10] (1), (7), (8) 
116 TCON [9] / 
V[2]  
V [2] V [2] BRED [0] TCON [9] (1), (7), (8) 
117 TCON [8] / 
V[3] 
V [3]   V [3]   AGRN [1] TCON [8] (1), (7), (8) 
118 TCON [7] / 
V[4] 
V [4]   V [4] AGRN [0] TCON [7] (1), (7), (8) 
119 TCON [6] / 
V[5]  
V [5]   V [5]   DHS  DHS (1), (7), (8) 
122 TCON [5] / 
V[6]  
V [6]   V [6]   DVS  DVS (1), (7), (8) 
123 TCON [1] / 
V[7]  
V [7]   V [7] DENA  DENA (1), (7), (8) 
124 TCON [0] / 
VCLK 
VCLK VCLK DCLK / TCLKDCLK / TCLK (1), (7), (8) 
 
  
						

							
ViewSonic Corporation 22  Confidential - Do Not Copy   VA703b-4_VA703m-4 
„  TMDS: 18 pins 
    Name  I/O  Pin No  Description 
Note 
TMDS_TST/ PWM1  AIO 9  TMDS_TEST Pin / PWM1 / 
Power-on-latch for serial / parallel port  
TMDS_GND G 10    
TMDS_VDD P 11   (3.3V) 
EXT_RES    A  12  Impedance Match Reference.     
TMDS_VDD P 13   (3.3V) 
RX2P  I  14  Differential Data Input   
RX2N  I  15  Differential Data Input   
TMDS_GND G 16    
RX1P  I  17  Differential Data Input   
RX1N  I  18  Differential Data Input   
TMDS_VDD P 19   (3.3V) 
RX0P  I  20  Differential Data Input   
RX0N  I  21  Differential Data Input   
TMDS_GND G 22    
RXCP  I  23  Differential Data Input   
RXCN  I  24  Differential Data Input   
TMDS_GND G 25    
TMDS_VDD P 26   (3.3V) 
 
 
„
  PWM  Interface: 3-2=1 pin (PWM1, PWM2 can be  selected from 1 of 3 possible pins.) 
Name 
I/O Pin No Description  Note 
PWM2 / TCON [2] / S [3]  O  51  PWM2 / TCON [2] / SDIO [3]  (1), (2), (3), (5), (8), 
PWM2 / TCON [13] / COUT  O  55  PWM2 / TC
ON [13] / Crystal out  (2), (8), (9) 
PWM2 / TCON [12] / COUT  O  113  PWM2 / TCON [12] / Crystal out  (2), (8), (9) 
PWM1 / TMDS_TST  AIO  9 PWM1/ TMDS_TEST Pin / 
Power-on-latch for serial / parallel port  (2), (7), (8) 
PWM1 / DDCSDA / TCON [1] / 
BBLU [0]  IO 47 PWM1 / DDC serial control I/F data input 
/ output / TCON [4]  (1), (2), (3), (5), (8), 
PWM1 / DDCSDA2 (HDCP) / 
TCON [7]  IO 125 PWM1 / DDC serial control I/F data input 
/ output / TCON [7]  (1), (2), (3), (5), (8), 
PWM0 / REFCLK  IO  112 
PWM0 / (In / out) test pin for DCLK / 
Video8 even-odd signal  (2), (9) 
 
  
						

							
ViewSonic Corporation 23  Confidential - Do Not Copy   VA703b-4_VA703m-4 
„  DDC Channel: 4 pins 
    Name  I/O  Pin No  Description  Note 
DDCSCL / TCON [0] / 
BBLU [1]  I  46  DDC serial control I/F clock / TCON [0] / 
TTL BBLU [1]  (2), (3), (5) 
DDCSDA / TCON [1] / 
PWM1 / BBLU [0] IO  47  DDC serial control I/F data input / output 
/ TCON [1] / PWM1 / TTL BBLU [0]  (1), (2), (3), (5), (6), 
(8)/ 8mA /no slew 
DDCSCL2 (HDCP) / 
TCON [5] I  126  DDC serial control I/F cl
ock / TCON [5]  (2), (3), (5) 
DDCSDA2 (HDCP) / 
TCON [7] /PWM1 IO  125  DDC serial control I/F data input / output 
/ TCON [7] / PWM1  (1), (2), (3), (5), (6), 
(8)/ 8mA /no slew 
 
 
„
  Power & Ground: 22 pins 
Name 
I/O Pin No  Description 
3.3V Power  P  49,121  VCCIO: 2 
3.3V Ground  G  48,120  GNDIO: 2 
3.3V Power  P  58,71,83,95,110  PVCC: 5 
3.3V Ground  G  57,72,84,96,109  PGND: 5 
2.5V Power  P  45,69,98,127  VCCK: 4 
2.5V Ground  G  44,70,97,128  GNDIK: 4 
Note: (1) TTL compatible CMOS Input (Vt=1.7V); VCC=3.3V; 
(2) 5V tolerance pad; 
(3) Internal 75K Ohms pull high resistor. 
(4) Internal 75K Ohms pull low resistor. 
(5) Schmitt trigger CMOS Input (Vt=1.4-~2.2V); 
(6) Open-Drain, Output Drive low & Pull-high. 
(7) Bi-directional input/output 
(8) Programmable driving current (2~10mA) 
(9) TTL output 5V & 3.3V 
(10) 4V tolerance pad 
  
						

							
ViewSonic Corporation 24  Confidential - Do Not Copy   VA703b-4_VA703m-4 
C, MTV512M 
The MTV512M micro-controller is an 8051 CPU core 
embedded device especially tailored for flat panel 
display applications. It includes an 8051 CPU core, 
768-byte SRAM, 4 channels of 6-bit ADC, 3 external 
counters/timers, 6 channels of PWM DAC, VESA 
DDC interface, and a 64K-byte internal program 
Flash-ROM memory in 44-pin PLCC package 
FEATURES 
• 8051 core, 12MHz operating frequency with 
single/double CPU clock option 
• 0.35um process; 3.3V power supply 
• 768-byte RAM; 64K-byte program Flash memory 
• Maximum 6 channels of PWM DAC 
• Compliant with VESA DDC1/2B/2Bi/2B+ standard 
• Dual slave IIC addresses; two H/W auto transfer 
DDC1/DDC2x data for both D-sub and DVI 
interfaces 
• Watchdog timer with programmable interval 
• Support external counters/timers, 1 & 2 
• Single/double frequency clock output 
• Two external interrupts, INT1 is shared with Slave 
IIC interrupt source. 
• Maximum 4 channels of 6-bit ADC 
• Flash-ROM code protection selection 
• 44-pin PLCC package 
 
D. INVERTER 
In order to drive the CCFLs embedded in the panel module, there is a push-pull inverter to convert by the controller. from 
input 24V up to hundreds of AC voltage output peak to peak. 
The inverter is formed by symmetric in order to drive the separate lamp modules. 
The input stage consists of a PWM controller, push-pull inverter, and switching MOSFET to convert DC input into AC output. 
The output stage consists of a tuning capacitor, transformer, and push-pull MOSFET pair to boost AC output up to hundreds of 
voltage peak to peak. 
And one resister is serial to la mp for output voltage feedback. 
There are two signals which control the inverter come from system to turn on the inverter and control brightness. Logic “low” 
level which send to U901 is turn on the inverter. 
BL-ADJ signal control brightness by DC level which was integral from PWM signal. 
  
						

							
ViewSonic Corporation 25 
5. Adjustment Procedure 
 
 1. Function test 
1.1 products 17” LCD Monitor 
1.2 test equipment 
Color video Signal& pattern (Or PC with SXGA resolution and a sound card) 
1.3 Test Condition  Before function test and alignment ,each L CD Monitor should be warmed up at least 
30 minutes with the following conditions:  A: in roon temperature 
B with full white screen ,RGB ,and black 
C. with cycled display model: 
1280 x 1024 @ 60Hz 
1.4 Test display& Pattern  1.4.1 Compatible model 
Item Timing  Analog 
1  640 x 350 @ 70Hz, 31.5kHz 
Ye s 
2  640 x 480 @ 50Hz, 24.68KHZ 
Yes 
3  640 x 480 @ 60Hz, 31.5kHz Ye s 
4  MAC 640 x 480 @ 67Hz, 35.0kHz 
Ye s 
5  640 x 480 @ 72Hz, 37.9kHz 
Ye s 
6  640 x 480 @ 75Hz, 37.5kHz 
Ye s 
7  640 x 480 @ 85Hz, 43.27kHz 
Ye s 
8  720 x 400 @ 70Hz, 31.5kHz 
Ye s 
9  800 x 600 @ 56Hz, 35.1kHz 
Ye s 
10  800 x 600 @ 60Hz, 37.9kHz 
Ye s 
11  800 x 600 @ 72Hz, 48.1kHz 
Ye s 
12  800 x 600 @ 75Hz, 46.9kHz 
Ye s 
13  800 x 600 @ 85Hz, 53.7kHz 
Ye s 
14  MAC 832 x 624 @ 75Hz, 49.7kHz 
Ye s 
15  1024 x 768 @ 60Hz, 48.4kHz 
Ye s 
16  1024 x 768 @ 70Hz, 56.5kHz 
Ye s 
17  1024 x 768 @ 72Hz, 58.1kHz 
Ye s 
18  1024 x 768 @ 75Hz, 60.0kHz 
Ye s 
19  1024 x 768 @ 85Hz, 68.67KHZ 
Ye s 
20  1152 x 864 @ 75Hz, 67.5KHZ 
Ye s 
21  MAC 1152x870@75HZ, 68.68KHZ 
Ye s 
22  1280 x 960 @ 60Hz, 44.93KHZ 
Ye s 
23  1280 x 960 @75Hz, 56.25KHZ 
Ye s 
24  1280 x 1024 @ 60Hz, 63.98KHZ 
Ye s 
25  1280 x 1024 @ 75Hz, 79.97KHZ 
Ye s 
*1. Tolerance  ≧ ± 2kHz. 
*2. Any timing not in the list, it should display as norm al or show on “OUT OF RANGE” OSD message without 
blanking. 
*3. The image quality of 85Hz mode might be worse than 75Hz. 
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