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shema Acer Aspire 4720Z Z01 E3C User Manual

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Page 1

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REV 3A
MB ASSYS P/N : 31Z01MB00XX
2
PROJECT : ZO1
REV:
APPROVE BY: JIM HSU DRAWING BY:JACKY CHENG
MODEL:
TOZ01 
MotherBoard
PROJECT LEADER: JIM HSU DOCUMENT NO: 204
1
CHANGE LIST:
DATE :2007/04/14
FROM
COVER SHEET 1 OF 1
PAGE3
4
5
6
7
8
9
19
22 11
13
21 15
251A
24 17
23 16
20 18 12 10
14MODEL : Z01 MB
FIRST RELEASE 1A
1B
PAGE03. 1. STUFF HOLE23,25 P/N:FBZ01003010 , 2. STUFF HOLE18  P/N:FBZ01004010 , 3. STUFF HOLE31  P/N:FBZ01005010 PAGE03. 1. STUFF HOLE6  P/N:FBZ01007010 ,...

Page 2

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AzaliaPCI Bus interface
PATA ODD
FSB
MDC
Y3
32.768K
Speaker
PATA
Y5
14.318MHZ
Y4
32.768KHZ
PCI-e X1 X4 DMI
interface
USB Port x 2
SATA0
KBC PC8769L
LPC
Z01 SYSTEM BLOCK DIAGRAM
SPDIF
Merom CPU
Line in
USB 2.0
Clock Generator
SLG8SP512T
Thermal Sensor
ICH8M
Realtek
Audio Codec
ALC268
BIOS
MIC InCrestline
New Card
GIGA LAN BroadCom
USB4
Bluetooth
SATA HDD
Transformer RJ45
Internal
MIC
USB3,5
Intel NB
Intel SB
667/800 Mhz
CPU
CIR
K/B Touch PadWinbond
AMP
479 Pin...

Page 3

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Clock Gen I2C Clock Generator
SLG8SP512T: AL8SP512K05
CPU Clock select
0
0
00
0
0 00
0 0
0BSEL Frequency Select Table1
1 1 11
1
1
11
1
1 1133Mhz
166Mhz 200Mhz
400Mhz
Reserved 100Mhz 333Mhz FSC FSB FSA Frequency
266Mhz 0
Each Power pin have one 0.1u Capacitor
1 : Pin 46,47 as CPU output SILEGO
0 : Pin 46,47 as SRC output CK505 0 : Pin 37,38 as SRC5 output
0 : Pin 46,47 as SRC output 1 : pin 37,38 as PCI_STOP & CPU_STOP0 : Pin 13,14 & 17,18 for Internal VGA CK505
1 : 27M &...

Page 4

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SMBUS Address : 98
MAXIM 6657 : AL006657020
GMT    G781 : AL000781101
HOLE13,HOLE14 use FBZ01031010 UMA MODE:
MXM MODE:
HOLE13,HOLE14 use FBZ01001010
REV:C
MODIFY
REV:C
MODIFY
REV:D MODIFY for EMI reserved
CPU(1 of 2)/Thermal
3A
426 Thursday, May 17, 2007 Size Document Number Rev
Date: Sheet
of H_A#4 H_A#3
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#19
H_A#22 H_A#17
H_A#20
H_A#21
H_A#24
H_A#25
H_A#28
H_A#29 H_A#18
H_A#23
H_A#26
H_A#27...

Page 5

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CPU(Power)
EMI
REV:C Modify
CPU(2 of 2)Power
2B  
 
  
  
  
526 Thursday, May 17, 2007 Size Document Number Rev
Date: Sheet
of
VCC_CORE
VCC_CORE
+1.05V
+1.5V
VCC_CORE
10u/6.3V_8 C103
10u/6.3V_8
C442
.1u/16V_4
C106
.1u/16V_4
C89
R30 100/F_4
10u/6.3V_8
C124
10u/6.3V_8
C448
Quanta Computer Inc.PROJECT : ZO1
10u/6.3V_8 C445
10u/6.3V_8
C437
10u/6.3V_8
C78
10u/6.3V_8
C446
10u/6.3V_8
C432
+C110
330u/2.5V_734312
10u/6.3V_8 C79
10u/6.3V_8
C43910u/6.3V_8
C438
U21C...

Page 6

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For IV@
Connect to 150ohm:
CRT R/G/B
TV A/B/C
Connect to 30ohm:
HSYNC/VSYNC 
For EV@
Connect to GND
CRT R/G/B
TV A/B/C
HSYNC/VSYNC
0OHM (PD) FOR EV (RGB) 0OHM (PD) FOR EV (TV)

For Calero : 1.5K
For Cresstline:2.4K

Flexible and safe 
For Calero : 255
For Cresstline:1.3K/F
For external VGA:0IV&EV Dis/Enable setting
W: 10 mil / S: 20 milW: 10 mil /
S: 20 mil
HVREF
Width : 20mil
Length <
100mil
W: 10 mil
PM965 QN14 : AJ0QN140T04 GM965 QN12 : AJ0QN120T04
REV:C MODIFY
REV:B...

Page 7

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If no use DREFCLK PD and DREFCLK# PU

R Value select
For Calero : 80.6ohm
For Cresstline:20ohm
But check list use 80.6ohm
Any CFG signal strapping option not list below should be left NC Pin CFG[17:3] Have internal Pull-up All strap are sampled with respect to the leading edge of the GMCH PWROK Signal
CFG[2:0]
010 = FSB 800 MHz
011 = FSB 667 MHz FSB Frequency Select CFG[18:19] Have internal Pull-down
CFG[13:12] CFG[11:10] CFG9
CFG8
0 = Only SDVO or PCIE x1 is...

Page 8

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GM965 QN12 : AJ0QN120T04
PM965 QN14 : AJ0QN140T04
REV:B MODIFY
REV:B MODIFYREV:C MODIFY REV:C MODIFY
GMCH DDR & GND
2B
826 Thursday, May 17, 2007 Size Document Number Rev
Date: Sheet
of SMA_MD1
SMA_MD2
SMA_MD3
SMA_MD4
SMA_MD5
SMA_MD6
SMA_MD7
SMA_MD8
SMA_MD9
SMA_MD10
SMA_MD11
SMA_MD12
SMA_MD13
SMA_MD14
SMA_MD15
SMA_MD16
SMA_MD17
SMA_MD18
SMA_MD19
SMA_MD20
SMA_MD21
SMA_MD22
SMA_MD23
SMA_MD24
SMA_MD25
SMA_MD26
SMA_MD27
SMA_MD28
SMA_MD29
SMA_MD30
SMA_MD31
SMA_MD32
SMA_MD33...

Page 9

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Stuff 0 ohm for
External VGA
Stuff 0 ohm for
External VGA Stuff 0 ohm for
External VGA
EXTERNAL INTERNALIf SDVO enable
LVDS enable
GND GND
GND
LVDS Disable/Enable guidelineVCCTX_LVDSIf SDVO enable
LVDS Disable
1.8V GND 1.8V Signal
1.8V 1.8V If SDVO Disable
LVDS Disable
VCCD_LVDSExternal VGA with EV@part,Internal VGA with IV@ partVCCA_LVDSGND
External VGA with EV@part, Internal VGA with IV@ partCRT/TV Disable/Enable guideline
GND Ball
VCCA_A_TVOGND VCCABG_DAC
GND GND 3.3V...

Page 10

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CLOCK 3,4,5
SMbus address A1
CKE 3,4
CLOCK 0,1,2CKE 0,1
SMbus address A0
DDR2 SO-DIMM SOCKET DDR2 TERMINATOR
TERMINATOR DECOUPLING CAPACITOR
CLOSE SO-DIMM SOCKET CAPACITORS CLOSE SO-DIMM SOCKET CAPACITORS
REV:B MODIFYDDR SO-DIMM(200P)
2A  
 
  
  
  
10 26 Thursday, May 17, 2007 Size Document Number Rev
Date: Sheet
of SMB_MA11
SMB_MA2
SMB_MA0 SMB_MA4
SMB_DQS5 SMB_MA3
SMB_MA13 SMB_MA1 SMB_MA5SMB_DQS3#
SMB_MA10SMB_DQS3
SMB_MD41 SMB_BA0
SMB_WE#SMB_DM1
SM_CS3#SMB_DM0...
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