Motorola Gm Series Low Band Info Manual

							Low Band Transmitter Power Amplifier (PA) 25-60 W 2-5
3.0 Low Band Transmitter Power Amplifier (PA) 25-60 W
The radio’s 60 W PA is a three-stage amplifier used to amplify the output from the VCO to the radio 
transmit level. The line-up consists of three stages which utilize LDMOS technology. The first stage 
is pre-driver (U1401) that is controlled by pin 4 of PCIC (U1503) via Q1504 and Q1505 
(CNTLVLTG). It is followed by driver stage Q1401, and final stage utilizing two devices (Q1402 and 
Q1403) connected in parallel. Q1402 and Q1403 are in direct contact with the heat sink. 
To prevent damage to the final stage devices, a safety switch has been installed to prevent the 
transmitter from being keyed with the cover removed.
Figure 2-2 LowBand Transmitter Block Diagram 
3.1Power Controlled Stage
The first stage (U1401) is a 20dB gain integrated circuit containing two LDMOS FET amplifier 
stages. It amplifies the RF signal from the VCO (TXINJ). The output power of stage U1401 is 
controlled by a DC voltage applied to pin 1 from the power control circuit (U1503 pin 4, with 
transistors Q1504-5 providing current gain and level-shifting). The control voltage simultaneously 
varies the bias of two FET stages within U1401. This biasing point determines the overall gain of 
U1401 and therefore its output drive level to Q1401, which in turn controls the output power of the 
PA .
3.2Driver Stage
The next stage is an LDMOS device (Q1401) providing a gain of 13dB. This device requires a 
positive gate bias and a quiescent current flow for proper operation. The voltage of the line 
MOSBIAS_1 is set during transmit mode by the PCIC pin 24, and fed to the gate of Q1401 via 
resistors R1402, R1447, R1449, R1458, R1459 and R1463, The bias voltage is tuned in the factory.
The circuitry associated with U1402-2 and Q1404 limits the variation in the output power of the 
driver stage resulting from changes in the input impedance of the final stage due to changes at the 
Pin Diode 
Antenna 
Switch
RF JackAntennaHarmonic 
Filter
PA - F i n a l
StagePADriver Fr o m V COControlled
Stage
BIAS
To Microprocessor
Temperature
Sense DC AMP
PASUPLVLTG(2 Lines)
SPI Bus
TXINJ
Sense Current
Sense Current
ASFIC_CMPPCICINT
24
4295
6
BIAS Powe r 
						

							2-6THEORY OF OPERATION
antenna of the radio. The variation in the driver’s output power is limited by controlling its DC 
current. The driver’s DC current is monitored by measuring the voltage drop across current-sense 
resistors R1473-6, and this voltage is compared to a reference voltage on pin 6 of U1402-2. If the 
current through the sense resistors decreases, the circuit increases the bias voltage on the gate of 
Q1401 via Q1404. If the current increases, then the bias voltage decreases in order to keep the 
driver’s current constant. Since the current must increase with increasing control voltage, an input 
path is provided to U1402-2 pin 5 from control line VCNTRL to enable this.
3.3 Final Stage
The final stage uses two LDMOS FET devices operating in parallel. Each device has its own 
adjustable gate bias voltage, MOSBIAS_2 and MOSBIAS_3, obtained from D/A outputs of the 
ASFIC. These bias voltages are also factory-tuned. If these transistors are replaced, the bias 
voltage must be tuned using the Tuner Software. Care must be taken not to damage the device by 
exceeding the maximum allowed bias voltage. The device’s drain current is drawn directly from the 
radio’s DC supply voltage input, PASUPVLTG, via current-measurement resistor R1409.
A matching network combines the output of the two devices and provides a 50-ohm source for the 
antenna switch and harmonic filter.
3.4 Antenna Switch
The antenna switch is operated by the 9T1 voltage source which forward biases diodes D1401 and 
D1402 during transmit, causing them to appear as a low impedance. D1401 allows the RF output 
from final stages Q1402 and Q1403 to be applied to the input of the low-pass harmonic filter 
(L1421-3 and associated components). D1402 appears as a short circuit at the input of the receiver 
(RXINJ), preventing transmitter RF power from entering the receiver. L1420 and C1456 appear as a 
broadband _-wave transmission line, making the short circuit presented by D1402 appear as open 
circuit at the junction of D1401 and the harmonic filter input.
During receive mode, the 9T1 voltage is not present, and D1401 and D1402 do not conduct and 
appear as open circuits. This allows signals from the antenna jack to pass to the receiver input, and 
disconnects the transmitter final stages from this path.
3.5 Harmonic Filter
Components L1421-L1423 and C1449-C1455 form a seven-pole elliptic low-pass filter to attenuate 
harmonic energy of the transmitter to specifications level. R1411 is used to drain electrostatic 
charge that might otherwise build up on the antenna. The harmonic filter also prevents high level RF 
signals above the receiver passband from reaching the receiver circuits, improving spurious 
response rejection.
3.6 Power Control
The transmitter uses the Power Control IC (PCIC, U1503) to control the power output of the radio. A 
differential DC amplifier U1502-1 compares the voltage drop across current-measuring resistor 
R1409, which is proportional to the transmitter final stage DC current, with the voltage drop across 
resistor R1508 and R1535, which is proportional to the current through transistor Q1503. This 
transistor is controlled by the output of the differential amplifier, which varies the transistor Q1503. 
This transistor is controlled by the output of the differential amplifier, which varies the transistor  
						

							Low Band Frequency Synthesis2-7
current until equilibrium of the two compared voltages is reached. The current through Q1503 
develops a voltage across R1513 which is exactly propor tional to the DC current of the final stages. 
This voltage is applied to the RF IN port of the PCIC (pin 1). 
The PCIC has internal digital to analog converters (DACs) which provide a reference voltage of the 
control loop. The reference voltage level is programmable through the SPI line of the PCIC. This 
reference voltage is proportional to the desired power setting of the transmitter, and is factory 
programmed at several points across the frequency range of the transmitter to offset frequency 
response variations of the transmitter’s power detector circuitry.
The PCIC provides a DC output voltage at pin 4 (INT) which is amplified and shifted in DC level by 
stages Q1504 and Q1505. The 0 to 4 volt DC range at pin 4 of U1503 is translated to a 0 to 8 volt 
DC range at the output of Q1505, and applied as VCNTRL to the power-adjust input pin of the first 
transmitter stage U1401. This adjusts the transmitter power output to the intended value. Variations 
in antenna impedance cause variations in the DC current of the final stages, and the PCIC adjusts 
the control voltage above or below its nominal value to reduce power if current drain increases, or 
raise power if current drain decreases.
Capacitors C1503-4 and C1525, in conjunction with resistors and integrators within the PCIC, 
control the transmitter power-rise (key-up) and power-decay (de-key) characteristic to minimize 
splatter into adjacent channels.
U1501 is a temperature-sensing device which monitors the circuit board temperature in the vicinity 
of the transmitter circuits and provides a dc voltage to the PCIC (TEMP, pin 29) proportional to 
temperature. If the DC voltage produced exceeds the set threshold in the PCIC, the transmitter 
output power will be reduced so as to reduce the transmitter temperature.
3.7 TX Safety Switch
The TX Safety Switch consists of S1501, Q1506, and diode pairs D1502 and D1503 providing 
protection to the Þnal stage divices Q1402 and Q1403. These Þnal stage devices can be degraded 
or destroyed if the radio is keyed without the cover in place due to the lack of a good thermal path to 
the chassis.
Switch S1501 is closed when the radio´s cover is screwed in place by means of the carbonized 
reqion on the cover´s pressure pad making contact with the Þnger plating on the radio´s PCB. With 
the cover in place, transistor Q1506 is off, back-biasing diodes D1502 and D1503, enabling proper 
transmitter operation. When the cover is not in place, S1501 opens, causing Q1506 to rurn on, 
pulling the cathodes of D1502 and D1503 to ground, resulting in the shorting of the transmitter´s 
bias lines and control voltage.
4.0 Low Band Frequency Synthesis
The frequency synthesizer subsystem consists of the reference oscillator crystal (Y1201), the Low 
Voltage Fractional-N synthesizer (LVFRAC-N, U1201), and the receive and transmit VCOs and 
buffers (Q1303 through Q1308 and associated components).
4.1 Fractional-N Synthesizer
The LVFRAC-N synthesizer IC (U1201) consists of a reference oscillator, pre-scaler, a 
programmable loop divider, control divider logic, a phase detector, a charge pump, an A/D converter  
						

							2-8THEORY OF OPERATION
for low frequency digital modulation, a balance attenuator to balance the high frequency analog 
modulation and low frequency digital modulation, a 13V positive voltage multiplier, a serial interface 
for control, and finally a super filter for the regulated 9.3 volt supply.
Regulated 9.3 volts DC applied to the super filter input (U1201 pin 30) delivers a very low noise 
output voltage of 8.3 volts DC (VSF) at pin 28. External device Q1201 allows greater current 
sourcing capability. The VSF source supplies the receive and transmit VCOs and first buffer stages. 
The synthesizer IC supply voltage is provided by a dedicated 5V regulator (U1250) to minimize 
power supply noise.
In order to generate a high voltage to supply the phase detector (charge pump) output stage at pin 
VCP (U1201 pin 47), a capacitive voltage multiplier circuit (CR1202 and C1209) generates a voltage 
of 13 volts DC. This multiplier is driven by two 1.05 MHz clock signals from U1201 pins 15 and 14 
(VMULT1 and VMULT2) which are 180° out of phase.
Figure 2-3 LowBand Synthesizer Block Diagram
Output LOCK (U1201-4) provides information about the lock status of the synthesizer loop. A high 
level at this output indicates a stable loop. A buffered output of the 16.8 MHz reference frequency is 
provided at pin 19.
The operating frequency of the synthesizer is loaded serially from the microprocessor via the data 
line (DATA, U1201-7), clock line (CLK, U1201-8) and chip select line (CSX, U1201-9).
The reference oscillator circuit within U1201 uses an external 16.8 MHz crystal (Y1201). Varactor 
CR1201 allows software-controlled frequency adjustment (warp) and temperature compensation of 
the oscillator frequency. Warp adjustment is performed using serial data from the microprocessor. 
This controls the setting of an A/D converter, with its output (WARP, pin 25) applied to CR1201.
DATA
CLK
CEX
MODIN
SFIN
XTAL1
XTAL2
WARP
PREIN
VCP
REFERENCE
OSCILLATOR
 VOLTAGE
MULTIPLIER
DATA (U0101 PIN 100)
CLOCK (U0101 PIN 1)
CSX (U0101 PIN 2)
MOD IN (U0221 PIN 40)
9,3V (U641 PIN 5)7
8
9
10
 30
23
24
25
32
47
VMULT2 VMULT1BIAS1 SFOUTAUX3 AUX4 IADAPTIOUTGND FREFOUTLOCK4
19
6, 22, 33, 44
43
45
3
2
28
       14
 1540FILTERED 8,3VSTEERING LOCK (U0101 PIN 56)
PRESCALER INFREF (U0221 PIN 34)
39 BIAS2
41
 48 5, 13, 20, 34, 36
+5V (U3211 PIN 1)
AUX1 VDD, DC5VMODOUT U1201 
LOW VOLTAGE
FRACTIONAL-N
SYNTHESIZER
AUX2
TX RF INJECTION
(1ST STAGE OF PA)LO RF INJECTION
VOLTAGE 
CONTROLLED 
OSCILLATORLINE
2-POLE
LOOP
FILTER1
Q1202
BUFFERBWSELECT
VCTRL
N.C.
N.C. 
						

							Low Band Frequency Synthesis2-9
4.2 Voltage Controlled Oscillator (VCO)
Separate VCO and buffer circuits are used for receiver injection and transmitter carrier frequency 
generation. Since the receiver uses high-side injection, the receiver VCO frequency range is 10.7 
MHz above the transmit VCO range. The VCO/buffers are bandsplit into three ranges depending on 
radio model, covering radio operating frequencies of 29.7 to 36.0 MHz, 36.0 to 42.0 MHz, or 42.0 to 
50.0 MHz. The corresponding three frequency ranges for the receive VCO are 40.4 to 46.7 MHz, 
46.7 to 52.7 MHz, and 52.7 to 60.7 MHz.
The VCOs, together with Fractional-N synthesizer U1201, generate the required frequencies for 
transmit and receive mode. The TRB line (U1201 pin 2) determines which VCO/buffer circuit is to be 
enabled. A high level on TRB will turn on the transistors in U1378 to turn on via R1376, applying the 
8.3 volt VSF source to the receiver VCO and first buffer. The second buffer in each string operates 
from the 9V3 source and become active when RF is applied to their inputs. 
The RF signal at the bases of the second buffers are combined and fed back to the Fractional-N 
synthesizer via PRE_IN where it is compared to the reference frequency as described below in 
“Synthesizer Operation”. The Fractional-N IC provides a DC steering voltage VCTRL to adjust and 
maintain the VCO at the correct frequency. 
With a steering voltage from 2.5V to 11V at the appropriate varactor diode (CR1302 for the RX VCO, 
or CR1310 for the TX VCO), the full VCO tuning range is obtained. Each VCO uses and AGC circuit 
to maintain a constant VCO output level across the frequency band. A diode (CR1306 in the receive 
VCO, or CR1314 in the transmit VCO) is configured as a voltage doubler which rectifies the RF level 
sampled at the VCO drain and applies a proportional negative DC voltage to the VCO gate. 
Increased RF level reduces the VCO gain to compensate.
Figure 2-4 LowBand VCO/Buffer Block Diagram
STEERINGLINE
(VCTRL)RXVCO
Q1303
Q1306 TXVCOAGC 
AGC Q1304
Q1307 Q1308Q1305 BUFFER BUFFER
BUFFER
BUFFER1ST RX
2ND RX
2ND TX
1ST TX
TXINJ RXINJ
TO Q1202
PRESCALER BUFFER(TO 1ST MIXER)
(TO U1401 PIN16)
SFOUT
(U1201 PIN28)U1377-8
DC SWITCH
RX (TO Q1303-5)
TX (TO Q1306-8)
(U1201 PIN2)
~
~ 
						

							2-10THEORY OF OPERATION
The VCO output is taken from the source and applied to the first buffer transistor (Q1304 receive, 
Q1307 transmit). The first buffer output is further amplified by the second buffer transistor (Q1305 
Rx, Q1308 Tx) before being applied to the receiver first mixer or transmitter first stage input.
In TX mode the modulation signal coming from the LVFRAC-N synthesizer IC (MODOUT, U1201 pin 
41) is superimposed on the DC steering line voltage by capacitive divider C1215, C1208 and 
C1212, causing modulation of the TX VCO using the same varactor as used for frequency control.
4.3 Synthesizer Operation
The complete synthesizer subsystem comprises mainly of low voltage LVFRAC-N synthesizer IC, 
Reference Oscillator (crystal oscillator with temperature compensation), charge pump circuitry, loop 
filter circuitry, and voltage-controlled oscillators and buffers. A sample of the VCO operating signal 
PRE_IN is amplified by feedback buffer Q1202, low-pass filtered by L1205, C1222 and C1224, and 
fed to U1201 pin 32  (PREIN).
The pre-scaler in the synthesizer (U1201) is basically a dual modulus pre-scaler with selectable 
divider ratios. This divider ratio of the pre-scaler is controlled by the loop divider, which in turn 
receives its inputs via the serial interface to the microprocessor. The output of the pre-scaler is 
applied to the loop divider. The output of the loop divider is connected to the phase detector, which 
compares the loop divider´s output signal with the reference signal. The reference signal is 
generated by dividing down the signal of the reference oscillator, whose frequency is controlled by 
Y1201.
The output signal of the phase detector is a pulsed DC signal which is routed to the charge pump. 
The charge pump outputs a current at pin 43 of U1201 (I OUT). The loop filter (which consists of 
R1205-6, R1208, C1212-14) transforms this current into a voltage that is applied to the varactor 
diodes (CR1310 for transmit, CR1302 for receive) and alters the output frequency of the appropriate 
VCO. The current can be set to a value fixed in the LVFRAC-N IC or to a value determined by the 
currents flowing into BIAS 1 (U1201-40) or BIAS 2 (U1201-39). The currents are set by the value of 
R1211 or R1207 respectively. The selection of the three different bias sources is done by software 
programming.
To reduce synthesizer lock time when new frequency data has been loaded into the synthesizer the 
magnitude of the loop current is increased by enabling the IADAPT  (U1201-45) for a certain 
software programmable time (Adapt Mode). The adapt mode timer is started by a low to high 
transient of the CSX line. When the synthesizer is within the lock range the current is determined 
only by the resistors connected to BIAS 1, BIAS 2, or the internal current source. A settled 
synthesizer loop is indicated by a high level of signal LOCK  (U1201-4). 
In order to modulate the PLL the two spot modulation method is utilized. Via pin 10 (MODIN) on 
U1201, the audio signal is applied to both the A/D converter (low frequency path) and the balanced 
attenuator (high frequency path). The A/D converter converts the low frequency analog modulating 
signal into a digital code that is applied to the loop divider, thereby causing the carrier to deviate. 
The balance attenuator is used to adjust the VCO’s deviation sensitivity to high frequency 
modulating signals. The output of the balance attenuator is present at the MODOUT port (U1201-
41) and superimposed on the VCO steering line voltage by a divider consisting of C1215, C1208 
and C1212. 
						

							Chapter 3
LOW BAND TROUBLESHOOTING CHARTS
1.0 Troubleshooting Flow Chart for Transmitter
No
 DC
@ Gate of
Q1401 Voltage
?
No
Ye s
              START
        No or Low 
  
  TX
 DC
      @Drains of 
Q1402 &
Q1403 Voltage 
?
@ Cathode of 
D1401 &
D1402DC
Voltage
?
Drains of Q1402 &AC
Q1403 both sine or
both distortedVoltages @
?
Check 9T1 and
Diode Bias Circuit
Verify RF Continuity
   to gates of
Q1402 & Q1403
 
Check circuitry
between Q1402 &
Q1403 and 
Antenna Port
CheckMOSBIAS_1
Supply and
Feed Network
No
 1A
Look for
   short on
Supply Line
R1414
Voltage
?
TXSafety
SwitchCheck Pressure Pad
and/or
Switch Circuitry 
						

							3-2Low Band TROUBLESHOOTING CHARTS
2.0 Troubleshooting Flow Chart for Receiver
(Sheet 1 of 2)
Audio
at pin 8 of 
U1103
?
Audio 
heard
?
 Check
voltages on 
U1103.
OK? Bad SINAD
Bad 20dB Quieting
No Recovered AudioSTARTCheck Controller (in the case of no audio).
Or else go to “B” Ye s
No
Spray or inject 10.7MHz 
into XTAL Filter FL1102.
BYe s
No
Check 2nd LO 
(10.245MHz) at C1129. 
LO
present
BYe s
Biasing 
OK
No
No
A
Ye sCheck Q1106 bias 
for faults.
Replace Q1106.
Go to B
Ye s
No
Check 
circuitry 
around 
U1103. 
Replace 
U1103 if 
defect.
Check circuitry around Y1101. 
Replace Y1101 if defect. 
						

							Troubleshooting Flow Chart for Receiver3-3
Troubleshooting Flow Chart for Receiver (Sheet 2 of 2)
Check for detailed mixer.
Is
9V3 present
? RF
Signal at 
pin 3 of 
U1051
?
RF
Signal at 
C1002
?
RF
Signal at
C1013
?
IF 
Signal at 
pin 2 of 
U1051
?
No
RF
Signal at 
C1017
?
No
No
No or 
Check harmonic filters J1401
and ant.switch 
Check preselector 
and RF amp.
Inject RF into J1401
No
Ye s
Check RF amp (Q1001) 
Stage.
Check filter between 
C1017 & mixer U1051
Ye s
Ye s
1st
LO level OK?
Locked
?Ye s
Check FGU
Ye s
Trace IF signal 
from C1036 to 
Q1106. Check for 
bad XTAL filter.
No
Ye sIF
signal at 
Q1106 
collector
?
Before replacing 
U1103, check 
U1103 voltages.
Ye s
Check Supply Voltage 
circuitry. Check U0681, 
U3211 and U0641.
No
No
Ye s
A
B
weak RF 
						

							3-4Low Band TROUBLESHOOTING CHARTS
3.0 Troubleshooting Flow Chart for Synthesizer
Is
U1201 pin 2
>4.5 VDC in Tx &