Motorola Gm Series Detailed 6864115b62 A Manual

Controller Board Audio and Signalling Circuits 1-9
1.14 Electrically Erasable Programmable Memory (EEPROM)
The external 16 Kbyte EEPROM (U0111) contains additional radio operating parameters such as 
operating frequency and signalling features, commonly know as the codeplug. It is also used to store 
radio operating state parameters such as current mode and volume. This memory can be written to 
in excess of 100,000 times and will retain the data when power is removed from the radio. The 
memory access...

1-10THEORY OF OPERATION
2.2 Transmit Audio Circuits
Refer to Figure 3-1 for reference for the following sections.
Figure 3-1 Transmit Audio Paths
2.2.1 Mic/Data Input Path
The radio supports 2 distinct microphone paths known as internal (from controlhead) and external 
mic (from accessory connector J0501-2) and an auxiliary path (FLAT TX AUDIO, from accessory 
connector J0501-5). The microphones used for the radio require a DC biasing voltage provided by a 
resistive network.
These two microphone audio...

Controller Board Audio and Signalling Circuits 1-11
C0254 serves as a DC blocking capacitor. Multi switch U0251 controlled by ASFIC CMP port GCB4 
selects either the external microphone input signal or the voice storage playback signal for entering 
the ASFIC CMP at pin 48. The audio signal at U0221-48 (TP0222) should be approximately 14mV 
for 1.5kHz or 3kHz of deviation with 12.5kHz or 25kHz channel spacing.
The FLAT TX AUDIO path is used for transmitting data signals and has therefore no limiter or...

1-12THEORY OF OPERATION
Secure board contains circuitry to amplify, encrypt, and filter the audio. The encrypted signal is then 
fed back from J0551-32 to the ASFIC CMP TX RTN input (U0221-36). The signal level at this pin 
should be about 65mVrms. The signal is then routed through the TX path in the ASFIC CMP and 
emerges at MOD IN pin 40.
2.2.4 Option Board Transmit Audio
The audio follows the normal transmit audio processing until it emerges from the ASFIC CMP TX 
SND pin (U0221-44), which is fed to...

Controller Board Audio and Signalling Circuits 1-13
may be as high as 250 Hz, which is audible to the human ear. However, the radio receiver filters out 
any audio below 300Hz, so these tones are never heard in the actual system.
Only one type of sub-audible data can be generated by U0221 (ASFIC CMP) at any one time. The 
process is as follows, using the SPI BUS, the µP programs the ASFIC CMP to set up the proper low-
speed data deviation and select the PL or DPL filters. The µP then generates a square...

1-14THEORY OF OPERATION
2.4 Receive Audio Circuits
Refer to Figure5-5 for reference for the following sections.
Figure 4-1 Receive Audio Paths
2.4.1 Squelch Detect
The radio’s RF circuits are constantly producing an output at the discriminator (IF IC). This signal 
(DISC AUDIO) is routed to the ASFIC CMP’s squelch detect circuitry input DISC (U0221-2). All of 
the squelch detect circuitry is contained within the ASFIC CMP. Therefore from a user’s point of view, 
DISC AUDIO enters the ASFIC CMP, and the...

Controller Board Audio and Signalling Circuits 1-15
2.4.2 Audio Processing and Digital Volume Control
The receiver audio signal enters the controller section from the IF IC on DISC AUDIO. The signal is 
DC coupled by R0228 and enters the ASFIC CMP via the DISC pin U0221-2.
Inside the ASFIC CMP, the signal goes through 2 paths in parallel, the audio path and the PL/DPL 
path.
The audio path has a programmable amplifier, whose setting is based on the channel bandwidth 
being received, then a LPF filter to...

1-16THEORY OF OPERATION
2.4.4 Handset Audio
Certain hand held accessories have a speaker within them which require a different voltage level 
than that provided by U0271. For those devices HANDSET AUDIO is available at controlhead 
connector J0401-7.
The received audio from the output of the ASFIC CMP’s digital volume attenuator and buffered by 
U0211-1 is also routed to U0211-3 pin 9 where it is amplified 20 dB; this is set by the 10k/100k 
combination of R0261 and R0262. This signal is routed from the...

Controller Board Audio and Signalling Circuits 1-17
2.5 RECEIVE SIGNALLING CIRCUITS
Refer to Figure 5-6 for reference for the following sections.
Figure 4-2 Receive Signalling Paths
2.5.1 Sub-audible (PL/DPL) and High Speed Data Decoder
The ASFIC CMP (U0221) is used to filter and limit all received data. The data enters the ASFIC CMP 
at input DISC (U0221-2). Inside U0221 the data is filtered according to data type (HS or LS), then it 
is limited to a 0-5V digital level. The MDC and trunking high speed...

1-18THEORY OF OPERATION
2.6 Voice Storage (optional)
The Voice Storage (VS) option can be used to store audio signals coming from the receiver or from 
the microphone. Any stored audio signal can be played back over the radio’s speaker or sent out via 
the radio’s transmitter.
The Voice Storage option can by placed on the controller section or on an additional option board 
which resides on option board connector J0551. Voice Storage IC U0301 provides all required 
functionality and is powered from 3.3...