Motorola Gm Controller Manual

							Controller Circuits1-7
DIG OUT 2 can be used as normal output or external alarm output, set by the CPS. Transistor Q0173 
is controlled by the µP via ASFIC CMP pin 14.
DIG IN 3 is read by µP pin 61 via resistor R0176
DIG IN 5 can be used as normal input or emergency input, set by the CPS. The µP reads this port via 
R0179 and µP pin 60. Diode D0179 limits the voltage to protect the µP input.
DIG IN 6 can be used as normal input, set by the CPS. The µP reads this port via pin 74 and Q0181.
DIG IN OUT 4,7,8 are bi-directional and use the same circuit configuration. Each port uses an output 
transistor Q0177, Q0183, Q0185 controlled by µP pins 46, 47, 53. The ports are read by µP pins 75, 
54, 76. To use one of the ports as input the µP must turn off the corresponding output transistor.
In addition the signals from DIG IN 1, DIG IN OUT 4 are fed to the option board connector J0551 and 
the expansion board connector J0451.
1.12 Normal Microprocessor Operation
For this radio, the µP is configured to operate in one of two modes, expanded and bootstrap. In 
expanded mode the µP uses external memory devices to operate, whereas in bootstrap operation 
the µP uses only its internal memory. In normal operation of the radio the µP is operating in 
expanded mode as described below.
In expanded mode on this radio, the µP (U0101) has access to 3 external memory devices; U0121 
(FLASH EEPROM), U0122 (SRAM), U0111 (EEPROM). Also, within the µP there are 3Kbytes of 
internal RAM, as well as logic to select external memory devices.
The external EEPROM (U0111) space contains the information in the radio which is customer 
specific, referred to as the codeplug. This information consists of items such as: 1) what band the 
radio operates in, 2) what frequencies are assigned to what channel, and 3) tuning information. (See 
the particular device subsection for more details.)
The external SRAM (U0122) as well as the µP’s own internal RAM space are used for temporary 
calculations required by the software during execution. All of the data stored in both of these 
locations is lost when the radio powers off (See the particular device subsection for more details).
The FLASH EEPROM contains the actual Radio Operating Software. This software is common to all 
open architecture radios within a given model type. For example Trunking radios may have a different 
version of software in the FLASH EEPROM than a non Trunking radio (See the particular device 
subsection for more details).
The µP provides an address bus of 16 address lines (ADDR 0 - ADDR 15), and a data bus of 8 data 
lines (DATA 0 - DATA 7). There are also 3 control lines; CSPROG (U0101-38) to chip select U0121-
30 (FLASH EEPROM), CSGP2 (U0101-41) to chip select U0122-20 (SRAM) and PG7 R W (U0101-
4) to select whether to read or to write. The external EEPROM (U0111-1), the OPTION BOARD and 
EXPANSION BOARD are selected by 3 lines of the µP using address decoder U0141. The chips 
ASFIC CMP / FRAC-N / PCIC are selected by line CSX (U0101-2).
When the µP is functioning normally, the address and data lines should be toggling at CMOS logic 
levels. Specifically, the logic high levels should be between 4.8 and 5.0V, and the logic low levels 
should be between 0 and 0.2V. No other intermediate levels should be observed, and the rise and fall 
times should be 
						

							1-8THEORY OF OPERATION
On the µP the lines XIRQ (U0101-48), MODA LIR (U0101-58), MODB VSTPY (U0101-57) and 
RESET (U0101-94) should be high at all times during normal operation. Whenever a data or address 
line becomes open or shorted to an adjacent line, a common symptom is that the RESET line goes 
low periodically, with the period being in the order of 20msecs. In the case of shorted lines you may 
also detect the line periodically at an intermediate level, i.e. around 2.5V when 2 shorted lines 
attempt to drive to opposite rails.
The MODA LIR (U0101-58) and MODB VSTPY (U0101-57) inputs to the µP must be at a logic 1 for 
it to start executing correctly. After the µP starts execution it will periodically pulse these lines to 
determine the desired operating mode. While the Central Processing Unit (CPU) is running, MODA 
LIR is an open-drain CMOS output which goes low whenever the µP begins a new instruction (an 
instruction typically requires 2-4 external bus cycles, or memory fetches). However, since it is an 
open-drain output, the waveform rise assumes an exponential shape similar to an RC circuit.
There are 8 analogue to digital converter ports (A/D) on U0101. They are labelled within the device 
block as PE0-PE7. These lines sense the voltage level ranging from 0 to 5V of the input line and 
convert that level to a number ranging from 0 to 255 which can be read by the software to take 
appropriate action.
For example U0101-67 is the battery voltage detect line. R0671 and R0672 form a resistor divider on 
INT SWB+. With 30K and 10K and a voltage range of 11V to 17V, that A/D port would see 2.74V to 
4.24V which would then be converted to ~140 to 217 respectively.
U0101-69 is the high reference voltage for the A/D ports on the µP. Capacitor C0101 filters the +5V 
reference. If this voltage is lower than +5V the A/D readings will be incorrect. Likewise U0101-68 is 
the low reference for the A/D ports. This line is normally tied to ground. If this line is not connected to 
ground, the A/D readings will be incorrect.
1.13 FLASH Electronically Erasable Programmable Memory (FLASH EEPROM)
The 512KByte FLASH EEPROM (U0121) contains the radio’s operating software. This software is 
common to all open architecture radios within a given model type. For example Trunking radios may 
have a different version of software in the FLASH EEPROM than a non Trunking radio. This is, as 
opposed to the codeplug information stored in EEPROM (U0111) which could be different from one 
user to another in the same company.
In normal operating mode, this memory is only read, not written to. The memory access signals (CE, 
OE and WE) are generated by the µP.
To upgrade/reprogram the FLASH software, the µP must be set in bootstrap operating mode. This is 
done by pulling microprocessor pins MODA LIR (U0101-58) and MODB VSTBY (U0101-57) to low 
during power up. When accessory connector pin 18 is at ground level, diode D0151 will pull both 
microprocessor pins to low. The same can be done by a level of 12 volts on line ON OFF CONTROL 
from the controlhead. Q0151 pulls diode D0151 and in turn both microprocessor pins to low. Diode 
VR0151 prevents entering bootstrap operating mode during normal power up.
In bootstrap operating mode the µP controls the FLASH EN OE (U0121-32) input by µP pin 86. Chip 
select (U0121-30) and read or write operation (U0121-7) are controlled by µP pins 38 and 4.
The FLASH device may be reprogrammed 1,000 times without issue. It is not recommended to 
reprogram the FLASH device at a temperature below 0°C.
Capacitor C0121 serves to filter out any AC noise which may ride on +5V at U0121. 
						

							Controller Board Audio and Signalling Circuits 1-9
1.14 Electrically Erasable Programmable Memory (EEPROM)
The external 16 Kbyte EEPROM (U0111) contains additional radio operating parameters such as 
operating frequency and signalling features, commonly know as the codeplug. It is also used to store 
radio operating state parameters such as current mode and volume. This memory can be written to 
in excess of 100,000 times and will retain the data when power is removed from the radio. The 
memory access signals (SI, SO and SCK) are generated by the µP and chip select (CS) is generated 
by address decoder U0141-15.
1.15 Static Random Access Memory (SRAM)
The SRAM (U0121) contains temporary radio calculations or parameters that can change very 
frequently, and which are generated and stored by the software during its normal operation. The 
information is lost when the radio is turned off. 
The device allows an unlimited number of write cycles. SRAM accesses are indicated by the CS 
signal U0122-20 (which comes from U0101-CSGP2) going low. U0122 is commonly referred to as 
the external RAM as opposed to the internal RAM which is the 3 Kbytes of RAM which is part of the 
68HC11FL0. Both RAM spaces serve the purpose. However, the internal RAM is used for the 
calculated values which are accessed most often.
Capacitor C0122 serves to filter out any ac noise which may ride on +5V at U0122.
2.0 Controller Board Audio and Signalling Circuits
2.1 General - Audio Signalling Filter IC with Compander (ASFIC CMP)
The ASFIC CMP (U0221) used in the controller has 4 functions;
1) RX/TX audio shaping, i.e. filtering, amplification, attenuation
2) RX/TX signalling, PL/DPL/HST/MDC/MPT
3) Squelch detection
4) Microprocessor clock signal generation (see Microprocessor Clock Synthesizer Description).
The ASFIC CMP is programmable through the SPI BUS (U0221-20/21/22), normally receiving 19 
bytes. This programming sets up various paths within the ASFIC CMP to route audio and/or 
signalling signals through the appropriate filtering, gain and attenuator blocks. The ASFIC CMP also 
has 6 General Control Bits GCB0-5 which are CMOS level outputs and used for NOISE BLANKER 
(GCB0) in Low Band radios, EXTERNAL ALARM (GCB1) and DC POWER ON (GCB2) to switch the 
voltage regulators (and the radio) on and off. GCB3 controls U0251 pin 11 to output either RX FLAT 
AUDIO or RX FILTERED AUDIO on the accessory connector pin 11. GCB4 controls U0251 pin 10 to 
use either the external microphone input or the voice storage playback signal. GCB5 is used to 
switch the audio PA on and off. 
						

							1-10THEORY OF OPERATION
2.2 Transmit Audio Circuits
Refer to Figure 3-1 for reference for the following sections.
Figure 3-1 Transmit Audio Paths
2.2.1 Mic/Data Input Path
The radio supports 2 distinct microphone paths known as internal (from controlhead) and external 
mic (from accessory connector J0501-2) and an auxiliary path (FLAT TX AUDIO, from accessory 
connector J0501-5). The microphones used for the radio require a DC biasing voltage provided by a 
resistive network.
These two microphone audio input paths enter the ASFIC CMP at U0221-48 (external mic) and 
U0221-46 (internal mic). Following the internal mic path; the microphone is plugged into the radio 
controlhead and is connected to the controller board via J0401-9.
From here the signal is routed via R0409 and line INT MIC to R0205. R0201 and R0202 provide the 
9.3VDC bias. Resistive divider R0205 / R0207 divide the input signal by 5.5 and provide input 
protection for the CMOS amplifier input. R0202 and C0201 provide a 560 ohm AC path to ground 
that sets the input impedance for the microphone and determines the gain based on the emitter 
resistor in the microphone’s amplifier circuit.
C0204 serves as a DC blocking capacitor. The audio signal at U0221-46 (TP0221) should be 
approximately 14mV for 1.5kHz or 3kHz of deviation with 12.5kHz or 25kHz channel spacing.
The external microphone signal enters the radio on accessory connector J0501 pin 2 and is routed 
via line EXT MIC to R0206. R0203 and R0204 provide the 9.3VDC bias. Resistive divider R0206 / 
R0208 divide the input signal by 5.5 and provide input protection for the CMOS amplifier input. 
R0204 and C0202 provide a 560 ohm AC path to ground that sets the input impedance for the 
microphone and determines the gain based on the emitter resistor in the microphone’s amplifier 
circuit.
MIC 
IN
MOD IN
TO
RF
SECTION
(SYNTHESIZER)
36 44
33
40
J0501
ACCESSORY
CONNECTOR
J0401
CONTROL HEAD
CONNECTOR
MIC
EXT MIC
FLAT TX
AUDIO4232
548
46 9
2
IN
OUT
OPTION
BOARD
FILTERS AND
PREEMPHASIS
HS SUMMER
SPLATTER
FILTER
LS SUMMERLIMITER
ATTENUATORVCO 
ATN TX RTN TX SND
MIC
INT
AUX 
TX
ASFIC_CMP 
 U0221
TP0221
TP0222MIC
EXT
J0451J0551
18 FLAT
TX RTN
EXPANSION BOARD31
IN/OUT
39
OUT
FROM
µ
P Pin3U0211-4 
						

							Controller Board Audio and Signalling Circuits 1-11
C0254 serves as a DC blocking capacitor. Multi switch U0251 controlled by ASFIC CMP port GCB4 
selects either the external microphone input signal or the voice storage playback signal for entering 
the ASFIC CMP at pin 48. The audio signal at U0221-48 (TP0222) should be approximately 14mV 
for 1.5kHz or 3kHz of deviation with 12.5kHz or 25kHz channel spacing.
The FLAT TX AUDIO path is used for transmitting data signals and has therefore no limiter or filters 
enabled inside the ASFIC CMP. When this path is enabled via CPS and DATA PTT is asserted, any 
signal on this path is directly fed to the modulator. Signals applied to this path either via accessory 
connector J0501, expansion board connector J0451 or option board connector J0551 must be 
filtered and set to the correct level externally or on the option board in order not to exceed the 
maximum specified transmit deviation and transmitted power in the adjacent channels. The 
attenuator inside the ASFIC CMP changes the FM deviation of the data signal according to the 
channel spacing of the active transmit channel.
The FLAT TX AUDIO signal from accessory connector J0501-5 is fed to the ASFIC CMP (U0221) 
pin42 through C0541 and line FLAT TX RTN, switch U0251 and buffer U0211-4. When the radio 
switches from receive to transmit mode the µP opens switch U0251 for a short period to prevent that 
any applied signal can cause a transmit frequency offset. Buffer U0211-4 sets the correct DC level 
and ensures a short settle period when the radio is switched on. Inside the ASFIC CMP the signal is 
routed directly to the attenuator, which sets the FM deviation according to the channel spacing of the 
active transmit channel and emerges from the ASFIC CMP at U0221-40, at which point it is routed to 
the RF section.
The ASFIC has an internal AGC that can control the gain in the mic audio path. The AGC can be 
disabled / enabled by the µP. Another feature that can be enabled or disabled in the ASFIC is the 
VOX. This circuit, along with the capacitor at U0221-7, provides a DC voltage that can allow the µP to 
detect microphone audio. The ASFIC can also be programmed to route the microphone audio to the 
speaker for public address operation.
2.2.2 PTT Sensing and TX Audio Processing
Microphone PTT coming from the controlhead is sent via SBEP bus to the microprocessor. An 
external PTT can be generated by grounding pin 3 on the accessory connector if this input is 
programmed for PTT by the CPS. When microphone PTT is sensed, the µP will always configure the 
ASFIC CMP for the internal mic audio path, and external PTT will result in the external mic audio 
path being selected.
Inside the ASFIC CMP, the mic audio is filtered to eliminate frequency components outside the 300-
3000Hz voice band, and pre-emphasized if pre-emphasis is enabled. The signal is then limited to 
prevent the transmitter from over deviating. The limited mic audio is then routed through a summer, 
which is used to add in signalling data, and then to a splatter filter to eliminate high frequency 
spectral components that could be generated by the limiter. The audio is then routed to an 
attenuator, which is tuned in the factory or the field to set the proper amount of FM deviation. The TX 
audio emerges from the ASFIC CMP at U0221-40 MOD IN, at which point it is routed to the RF 
section.
Dependent on the radio model, input pin 3 on the accessory connector can be programmed for DATA 
PTT by the CPS. When DATA PTT is sensed, the µP will always configure the ASFIC CMP for the flat 
TX audio path. Limiter and any filtering will be disabled. The signal is routed directly to the attenuator, 
which sets the FM deviation according to the channel spacing of the active transmit channel and 
emerges from the ASFIC CMP at U0221-40, at which point it is routed to the RF section.
2.2.3 TX Secure Audio (optional)
The audio follows the normal transmit audio processing until it emerges from the ASFIC CMP TX 
SND pin (U0221-44), which is fed to the Secure board residing at option connector J0551-33. The  
						

							1-12THEORY OF OPERATION
Secure board contains circuitry to amplify, encrypt, and filter the audio. The encrypted signal is then 
fed back from J0551-32 to the ASFIC CMP TX RTN input (U0221-36). The signal level at this pin 
should be about 65mVrms. The signal is then routed through the TX path in the ASFIC CMP and 
emerges at MOD IN pin 40.
2.2.4 Option Board Transmit Audio
The audio follows the normal transmit audio processing until it emerges from the ASFIC CMP TX 
SND pin (U0221-44), which is fed to the option board residing at option connector J0551-33. The 
option board contains circuitry to process the audio. The processed signal is then fed back from 
J0551-32 to the ASFIC CMP TX RTN input (U0221-36). The signal level at this pin should be about 
65mVrms. The signal is then routed through the TX path in the ASFIC CMP and emerges at MOD IN 
pin 40.
2.3 Transmit Signalling Circuits
Refer to Figure 4-1 for reference for the following sections.
Figure 4-1 Transmit Signalling Paths
From a hardware point of view, there are 3 types of signalling:
1) sub-audible data (PL / DPL / Connect Tone) that gets summed with transmit voice or signalling,
2) DTMF data for telephone communication in trunked and conventional systems, and
3) Audible signalling including Select 5, MPT-1327, MDC, High speed Trunking.
NOTE: All three types are supported by the hardware while the radio software determines which 
signalling type is available.
2.3.1 Sub-audible Data (PL/DPL)
Sub-audible data implies signalling whose bandwidth is below 300Hz. PL and DPL waveforms are 
used for conventional operation and connect tones for trunked voice channel operation. The trunking 
connect tone is simply a PL tone at a higher deviation level than PL in a conventional system. 
Although it is referred to as sub-audible data, the actual frequency spectrum of these waveforms 
19
18
40
MOD INTO RF
SECTION
(SYNTHESIZER)
8044
HIGH SPEED
CLOCK IN
(HSIO)
LOW SPEED 
CLOCK IN
(LSIO)
ASFIC_CMP U0221
MICRO
CONTROLLER
U0101
HS
SUMMER
5-3-2 STATE 
ENCODER
DTMF 
ENCODERSPLATTER
FILTER
PL
ENCODERLS
SUMMER
ATTENUATOR
8582
SPI
BUS 
						

							Controller Board Audio and Signalling Circuits 1-13
may be as high as 250 Hz, which is audible to the human ear. However, the radio receiver filters out 
any audio below 300Hz, so these tones are never heard in the actual system.
Only one type of sub-audible data can be generated by U0221 (ASFIC CMP) at any one time. The 
process is as follows, using the SPI BUS, the µP programs the ASFIC CMP to set up the proper low-
speed data deviation and select the PL or DPL filters. The µP then generates a square wave which 
strobes the ASFIC PL / DPL encode input LSIO U0221-18 at twelve times the desired data rate. For 
example, for a PL frequency of 103Hz, the frequency of the square wave would be 1236Hz.
This drives a tone generator inside U0221 which generates a staircase approximation to a PL sine 
wave or DPL data pattern. This internal waveform is then low-pass filtered and summed with voice or 
data. The resulting summed waveform then appears on U0221-40 (MOD IN), where it is sent to the 
RF board as previously described for transmit audio. A trunking connect tone would be generated in 
the same manner as a PL tone.
2.3.2 High Speed Data
High speed data refers to the 3600 baud data waveforms, known as Inbound Signalling Words 
(ISWs) used in a trunking system for high speed communication between the central controller and 
the radio. To generate an ISW, the µP first programs the ASFIC CMP (U0221) to the proper filter and 
gain settings. It then begins strobing U0221-19 (HSIO) with a pulse when the data is supposed to 
change states. U0221’s 5-3-2 State Encoder (which is in a 2-state mode) is then fed to the post-
limiter summer block and then the splatter filter. From that point it is routed through the modulation 
attenuators and then out of the ASFIC CMP to the RF board. MPT 1327 and MDC are generated in 
much the same way as Trunking ISW. However, in some cases these signals may also pass through 
a data pre-emphasis block in the ASFIC CMP. Also these signalling schemes are based on sending 
a combination of 1200 Hz and 1800 Hz tones only. Microphone audio is muted during High Speed 
Data signalling.
2.3.3 Dual Tone Multiple Frequency (DTMF) Data
DTMF data is a dual tone waveform used during phone interconnect operation. It is the same type of 
tones which are heard when using a Touch Tone telephone.
There are seven frequencies, with four in the low group (697, 770, 852, 941Hz) and three in the high 
group (1209, 1336, 1477Hz).
The high-group tone is generated by the µP (U0101-44) strobing U0221-19 at six times the tone 
frequency for tones less than 1440Hz or twice the frequency for tones greater than 1440Hz. The low 
group tone is generated by the ASFIC CMP, controlled by the µP via SPI bus. Inside U0221 the low-
group and high-group tones are summed (with the amplitude of the high group tone being 
approximately 2 dB greater than that of the low group tone) and then pre-emphasized before being 
routed to the summer and splatter filter. The DTMF waveform then follows the same path as was 
described for high-speed data. 
						

							1-14THEORY OF OPERATION
2.4 Receive Audio Circuits
Refer to Figure5-5 for reference for the following sections.
Figure 4-1 Receive Audio Paths
2.4.1 Squelch Detect
The radio’s RF circuits are constantly producing an output at the discriminator (IF IC). This signal 
(DISC AUDIO) is routed to the ASFIC CMP’s squelch detect circuitry input DISC (U0221-2). All of 
the squelch detect circuitry is contained within the ASFIC CMP. Therefore from a user’s point of view, 
DISC AUDIO enters the ASFIC CMP, and the ASFIC CMP produces two CMOS logic outputs based 
on the result. They are CH ACT (U0221-16) and SQ DET (U0221-17).
The squelch signal entering the ASFIC CMP is amplified, filtered, attenuated, and rectified. It is then 
sent to a comparator to produce an active high signal on CH ACT. A squelch tail circuit is used to 
produce SQ DET (U0221-17) from CH ACT. The state of CH ACT and SQ DET is high (logic 1) when 
carrier is detected, otherwise low (logic 0).
CH ACT is routed to the µP pin 84 while SQ DET is routed to the µP pin 83.
SQ DET is used to determine all audio mute / unmute decisions except for Conventional Scan. In 
this case CH ACT is a pre-indicator as it occurs slightly faster than SQ DET.
FLT/FLAT RX AUDIO
J050111
16
1EXTERNAL
SPEAKER
INTERNAL
SPEAKER ACCESSORY
CONNECTOR
CONTROLHEAD
CONNECTOR
HANDSET
AUDIO 7 2 3
J0401 INT
SPKR-
SPKR +
SPKR -1
9
2
J0551
41 10
INT
SPKR+
4
6
DISC
ASFIC_CMP
U0221
AUDIO 
PA
U0271
IN
OPTION
BOARD
IN OUT
VOLUME
ATTEN.
FILTER AND
DEEMPHASIS
17
MICRO 
CONTROLLER
U010180 FROM
RF
SECTION
(IF IC)
LIMITER, RECTIFIER
FILTER, COMPARATOR
SQ DETSQUELCH
CIRCUIT
16
PL  FILTER 
LIMITER
CH ACT
AUX RX43
18
LS IO
U IOAUDIO
8384
39URX OUT
17
J0451
EXPANSION
BOARDDISC
AUDIO34 28
35
85
IN
7 
						

							Controller Board Audio and Signalling Circuits 1-15
2.4.2 Audio Processing and Digital Volume Control
The receiver audio signal enters the controller section from the IF IC on DISC AUDIO. The signal is 
DC coupled by R0228 and enters the ASFIC CMP via the DISC pin U0221-2.
Inside the ASFIC CMP, the signal goes through 2 paths in parallel, the audio path and the PL/DPL 
path.
The audio path has a programmable amplifier, whose setting is based on the channel bandwidth 
being received, then a LPF filter to remove any frequency components above 3000Hz and then an 
HPF to strip off any sub-audible data below 300Hz. Next, the recovered audio passes through a de-
emphasis filter if it is enabled (to compensate for Pre-emphasis which is used to reduce the effects of 
FM noise). The IC then passes the audio through the 8-bit programmable attenuator whose level is 
set depending on the value of the volume control. Finally the filtered audio signal passes through an 
output buffer within the ASFIC CMP. The audio signal exits the ASFIC CMP at pin AUDIO (U0221-
41).
The µP programs the attenuator, using the SPI BUS, based on the volume setting. The minimum / 
maximum settings of the attenuator are set by codeplug parameters.
Since sub-audible signalling is summed with voice information on transmit, it must be separated from 
the voice information before processing. Any sub-audible signalling enters the ASFIC CMP from the 
IF IC at DISC U0221-2. Once inside it goes through the PL/DPL path. The signal first passes through 
one of 2 low pass filters, either PL low pass filter or DPL/LST low pass filter. Either signal is then 
filtered and goes through a limiter and exits the ASFIC CMP at LSIO (U0221-18). At this point the 
signal will appear as a square wave version of the sub-audible signal which the radio received. The 
microprocessor U0101-80 will decode the signal directly to determine if it is the tone / code which is 
currently active on that mode.
2.4.3 Audio Amplification Speaker (+) Speaker (-)
The output of the ASFIC CMP’s digital volume pot, U0221-41 is routed through dc blocking capacitor 
C0265 to a buffer formed by U0211-1. Resistors R0265 and R0268 set the correct input level to the 
audio PA (U0271). This is necessary because the gain of the audio PA is 46 dB, and the ASFIC CMP 
output is capable of overdriving the PA unless the maximum volume is limited. Resistor R0267 and 
capacitor C0267 increase frequency components below 350 Hz.
The audio then passes through R0269 and C0272 which provides AC coupling and low frequency 
roll-off. C0273 provides high frequency roll-off as the audio signal is routed to pins 1 and 9 of the 
audio power amplifier U0271.
The audio power amplifier has one inverted and one non-inverted output that produces the 
differential audio output SPK+ / SPK- (U0271-4/6). The inputs for each of these amplifiers are pins 1 
and 9 respectively; these inputs are both tied to the received audio. The audio PA’s DC biases are 
not activated until the audio PA is enabled at pin 8.
The audio PA is enabled via the ASFIC CMP (U0221-38). When the base of Q0271 is low, the 
transistor is off and U0271-8 is high, using pull up resistor R0273, and the Audio PA is ON. The 
voltage at U0273-8 must be above 8.5VDC to properly enable the device. If the voltage is between 
3.3 and 6.4V, the device will be active but has its input (U0273-1/9) off. This is a mute condition which 
is used to prevent an audio pop when the PA is enabled.
The SPK+ and SPK- outputs of the audio PA have a DC bias which varies proportionately with FLT 
A+ (U0271-7). FLT A+ of 11V yields a DC offset of 5V, and FLT A+ of 17V yields a DC offset of 8.5V. 
If either of these lines is shorted to ground, it is possible that the audio PA will be damaged. SPK+ 
and SPK- are routed to the accessory connector (J0501-16 and 1) and to the controlhead (connector 
J0401-2 and 3). 
						

							1-16THEORY OF OPERATION
2.4.4 Handset Audio
Certain hand held accessories have a speaker within them which require a different voltage level 
than that provided by U0271. For those devices HANDSET AUDIO is available at controlhead 
connector J0401-7.
The received audio from the output of the ASFIC CMP’s digital volume attenuator and buffered by 
U0211-1 is also routed to U0211-3 pin 9 where it is amplified 20 dB; this is set by the 10k/100k 
combination of R0261 and R0262. This signal is routed from the output of the op amp U0211-3 pin 8 
to J0401-7. The controlhead sends this signal directly out to the microphone jack. The maximum 
value of this output is 6.6Vp-p.
2.4.5 Filtered Audio and Flat Audio
The ASFIC CMP has an audio whose output at U0221-39 has been filtered and de-emphasized, but 
has not gone through the digital volume attenuator. From ASFIC CMP U0221-39 the signal is routed 
via R0251 through gate U0251-12 and AC coupled to U0211-2. The gate controlled by ASFIC CMP 
port GCB3 (U0221-35) selects between the filtered audio signal from the ASFIC CMP pin 39 
(URXOUT) or the unfiltered (flat) audio signal from the ASFIC CMP pin 10 (UIO). R0251 and R0253 
determine the gain of op-amp U0211-2 for the filtered audio while R0252 and R0253 determine the 
gain for the flat Audio. The output of U0253-7 is then routed to J0501-11 via dc blocking capacitor 
C0542 and R0531. Note that any volume adjustment of the signal on this path must be done by the 
accessory
2.4.6 RX Secure Audio (optional)
Discriminator audio, which is now encrypted audio, follows the normal receive audio processing until 
it emerges from the ASFIC CMP UIO pin (U0221-10), which is fed to the Secure board residing at 
option connector J0551-35. On the Secure board, the encrypted signal is converted back to normal 
audio format, and then fed back through (J0551-34) to AUX RX of the ASFIC CMP (U0221-43). 
From then on it follows a path identical to conventional receive audio, where it is filtered (0.3 - 3kHz) 
and de-emphasized. The signal URX SND from the ASFIC CMP (U0221-39), also routed to option 
connector J0551-28, is not used for the Secure board but for other option boards.
2.4.7 Option Board Receive Audio
Unfiltered audio from the ASFIC CMP pin UIO (U0221-10) enters the option board at connector 
J0551-35. Filtered audio from the ASFIC CMP pin URXOUT (U0221-39) enters the option board at 
connector J0551-28. On the option board, the signal may be processed, and then fed back through 
J0551-34 to AUX RX of the ASFIC CMP (U0221-43). From then on it follows a path identical to 
conventional receive audio, where it may be filtered (0.3 - 3kHz) and de-emphasized.